INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT93 4-bit binary ripple counter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 4-bit binary ripple counter FEATURES • Various counting modes • Asynchronous master reset • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT93 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT93 are 4-bit binary ripple counters. The devices consist of four master-slave flip-flops internally connected to provide a 74HC/HCT93 divide-by-two section and a divide-by-eight section. Each section has a separate clock input (CP0 and CP1) to initiate state changes of the counter on the HIGH-to-LOW clock transition. State changes of the Qn outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. A gated AND asynchronous master reset (MR1 and MR2) is provided which overrides both clocks and resets (clears) all flip-flops. Since the output from the divide-by-two section is not internally connected to the succeeding stages, the device may be operated in various counting modes. In a 4-bit ripple counter the output Q0 must be connected externally to input CP1. The input count pulses are applied to clock input CP0. Simultaneous frequency divisions of 2, 4, 8 and 16 are performed at the Q0, Q1, Q2 and Q3 outputs as shown in the function table. As a 3-bit ripple counter the input count pulses are applied to input CP1. Simultaneous frequency divisions of 2, 4 and 8 are available at the Q1, Q2 and Q3 outputs. Independent use of the first flip-flop is available if the reset function coincides with reset of the 3-bit ripple-through counter. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay CP0 to Q0 fmax maximum clock frequency CI input capacitance CPD power dissipation capacitance per package CL = 15 pF; VCC = 5 V notes 1 and 2 12 15 ns 100 77 MHz 3.5 3.5 pF 22 22 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF; VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 HCT Philips Semiconductors Product specification 4-bit binary ripple counter 74HC/HCT93 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 CP1 clock input 2nd, 3rd and 4th section (HIGH-to-LOW, edge-triggered) 2, 3 MR1, MR2 asynchronous master reset (active HIGH) 4, 6, 7, 13 n.c. not connected 5 VCC positive supply voltage 10 GND ground (0 V) 12, 9, 8, 11 Q0 to Q3 flip-flop outputs 14 CP0 clock input 1st section (HIGH-to-LOW, edge-triggered) Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification 4-bit binary ripple counter 74HC/HCT93 FUNCTION TABLE OUTPUTS COUNT Fig.4 Functional diagram. Q0 Q1 Q2 Q3 0 1 2 3 L H L H L L H H L L L L L L L L 4 5 6 7 L H L H L L H H H H H H L L L L 8 9 10 11 L H L H L L H H L L L L H H H H 12 13 14 15 L H L H L L H H H H H H H H H H Notes 1. Output Q0 connected to CP1. H = HIGH voltage level L = LOW voltage level MODE SELECTION RESET INPUTS Fig.5 Logic diagram. December 1990 4 OUTPUTS MR1 MR2 Q0 Q1 Q2 Q3 H L H L H H L L L L L L count count count Philips Semiconductors Product specification 4-bit binary ripple counter 74HC/HCT93 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. typ. max. −40 to +85 −40 to +125 min. max. min. max. UNIT V CC WAVEFORMS (V) tPHL/ tPLH propagation delay CP0 to Q0 41 15 12 125 25 21 155 31 26 190 38 32 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay CP1 to Q1 49 16 13 135 27 23 170 34 29 205 41 35 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay CP1 to Q2 61 22 18 185 37 31 230 46 39 280 56 48 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay CP1 to Q3 80 29 23 245 49 42 305 61 52 370 71 63 ns 2.0 4.5 6.0 Fig.6 tPHL propagation delay MRn to Qn 50 18 14 155 31 26 195 39 33 235 47 40 ns 2.0 4.5 6.0 Fig.7 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.6 trem removal time MRn to CP0, CP1 50 10 9 8 3 2 65 13 11 75 15 13 ns 2.0 4.5 6.0 Fig.7 tW pulse width CP0, CP1 80 16 14 14 5 4 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.6 tW master reset pulse width 80 MRn 16 14 14 5 4 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.7 fmax maximum clock pulse frequency CP0, CP1 30 91 108 4.8 24 28 4.0 20 24 MHz 2.0 4.5 6.0 Fig.6 December 1990 6.0 30 35 5 Philips Semiconductors Product specification 4-bit binary ripple counter 74HC/HCT93 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT CP0, CP1 MRn 0.60 0.40 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. −40 to +85 typ. max. min. max. −40 to +125 UNIT V CC WAVEFORMS (V) min. max. tPHL/ tPLH propagation delay CP0 to Q0 18 34 43 51 ns 4.5 Fig.6 tPHL/ tPLH propagation delay CP1 to Q1 18 34 43 51 ns 4.5 Fig.6 tPHL/ tPLH propagation delay CP1 to Q2 24 46 58 69 ns 4.5 Fig.6 tPHL/ tPLH propagation delay CP1 to Q3 30 58 73 87 ns 4.5 Fig.6 tPHL propagation delay MRn to Qn 17 33 41 50 ns 4.5 Fig.7 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 trem removal time MRn to CP0, CP1 10 3 13 15 ns 4.5 Fig.7 tW pulse width CP0, CP1 16 7 20 24 ns 4.5 Fig.6 tW master reset pulse width 16 MRn 5 20 24 ns 4.5 Fig.7 fmax maximum clock pulse frequency CP0, CP1 70 24 20 MHz 4.5 Fig.6 December 1990 30 6 Philips Semiconductors Product specification 4-bit binary ripple counter 74HC/HCT93 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the clock (CPn) to output (Qn) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the master reset (MRn) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CPn) removal time. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 7