INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT393 Dual 4-bit binary ripple counter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Dual 4-bit binary ripple counter 74HC/HCT393 The 74HC/HCT393 are 4-bit binary ripple counters with separate clocks (1CP and 2 CP) and master reset (1MR and 2MR) inputs to each counter. The operation of each half of the “393” is the same as the “93” except no external clock connections are required. The counters are triggered by a HIGH-to-LOW transition of the clock inputs. The counter outputs are internally connected to provide clock inputs to succeeding stages. The outputs of the ripple counter do not change synchronously and should not be used for high-speed address decoding. FEATURES • Two 4-bit binary counters with individual clocks • Divide-by any binary module up to 28 in one package • Two master resets to clear each 4-bit counter individually • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The master resets are active-HIGH asynchronous inputs to each 4-bit counter identified by the “1” and “2” in the pin description. A HIGH level on the nMR input overrides the clock and sets the outputs LOW. The 74HC/HCT393 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay HCT CL = 15 pF; VCC = 5 V nCP to nQ0 12 20 ns nQ to nQn+1 5 6 ns nMR to nQn 11 15 ns fmax maximum clock frequency 99 53 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per counter 23 25 pF notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 Philips Semiconductors Product specification Dual 4-bit binary ripple counter 74HC/HCT393 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 13 1CP, 2CP clock inputs (HIGH-to-LOW, edge-triggered) 2, 12 1MR, 2MR asynchronous master reset inputs (active HIGH) 3, 4, 5, 6, 11, 10, 9, 8 1Q0 to 1Q3, 2Q0 to 2Q3 flip-flop outputs 7 GND ground (0 V) 14 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Dual 4-bit binary ripple counter 74HC/HCT393 Fig.4 Functional diagram. Fig.5 State diagram. COUNT SEQUENCE FOR 1 COUNTER OUTPUTS COUNT Q0 December 1990 Q3 L H L H L L H H L L L L L L L L 4 5 6 7 L H L H L L H H H H H H L L L L 8 9 10 11 L H L H L L H H L L L L H H H H 12 13 14 15 L H L H L L H H H H H H H H H H 1. H = HIGH voltage level L = LOW voltage level 4 Q2 0 1 2 3 Notes Fig.6 Logic diagram (one counter). Q1 Philips Semiconductors Product specification Dual 4-bit binary ripple counter 74HC/HCT393 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 min. typ. max. min. max. −40 to +125 UNIT V WAVEFORMS CC (V) min. max. tPHL/ tPLH propagation delay nCP to nQ0 41 15 12 125 25 21 155 31 26 190 38 32 ns 2.0 4.5 6.0 Fig.7 tPHL/ tPLH propagation delay nQn to nQn+1 14 5 4 45 9 8 55 11 9 70 14 12 ns 2.0 4.5 6.0 Fig.7 tPHL 39 14 11 140 28 24 175 35 30 210 42 36 ns 2.0 4.5 6.0 Fig.8 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.7 propagation delay nMR to nQn tTHL/ tTLH output transition time tW clock pulse width HIGH or LOW 80 16 14 17 6 5 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.7 tW master reset pulse width; HIGH 80 16 14 19 7 6 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.8 trem removal time nMR to nCP 5 5 5 3 1 1 5 5 5 5 5 5 ns 2.0 4.5 6.0 Fig.8 fmax maximum clock pulse frequency 6 30 35 30 90 107 5 24 28 4 20 24 MHz 2.0 4.5 6.0 Fig.7 December 1990 5 Philips Semiconductors Product specification Dual 4-bit binary ripple counter 74HC/HCT393 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT 1CP 2CP 1MR 2MR 0.4 0.4 1.0 1.0 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. typ. −40 to +85 −40 to +125 max. min. max. min. UNIT V WAVEFORMS CC (V) max. tPHL/ tPLH propagation delay nCP to nQ0 15 25 31 38 ns 4.5 Fig.7 tPHL/ tPLH propagation delay nQn to nQn+1 6 10 13 15 ns 4.5 Fig.7 tPHL propagation delay nMR to nQn 18 32 40 48 ns 4.5 Fig.8 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.7 tW clock pulse width HIGH or LOW 19 11 24 29 ns 4.5 Fig.7 tW master reset pulse width; HIGH 16 6 20 24 ns 4.5 Fig.8 trem removal time nMR to nCP 5 0 5 5 ns 4.5 Fig.8 fmax maximum clock pulse frequency 27 48 22 18 MHz 4.5 Fig.7 December 1990 6 Philips Semiconductors Product specification Dual 4-bit binary ripple counter 74HC/HCT393 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the clock (nCP) to output (1Qn, 2Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the master reset (nMR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (nCP) removal time. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 7