MOTOROLA MC14569BCP

SEMICONDUCTOR TECHNICAL DATA
!
#
#
" L SUFFIX
CERAMIC
CASE 620
The MC14569B is a programmable divide–by–N dual 4–bit binary or BCD
down counter constructed with MOS P–channel and N–channel enhancement mode devices (complementary MOS) in a monolithic structure.
This device has been designed for use with the MC14568B phase
comparator/counter in frequency synthesizers, phase–locked loops, and
other frequency division applications requiring low power dissipation and/or
high noise immunity.
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
• Speed–up Circuitry for Zero Detection
• Each 4–Bit Counter Can Divide Independently in BCD or Binary Mode
• Can be Cascaded With MC14568B, MC14522B or MC14526B for
Frequency Synthesizer Applications
• All Outputs are Buffered
• Schmitt Triggered Clock Conditioning
ORDERING INFORMATION
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
– 0.5 to + 18.0
V
Vin, Vout
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current (DC or Transient),
per Pin
± 10
mA
PD
Power Dissipation, per Package†
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
260
_C
TL
Lead Temperature (8–Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
BLOCK DIAGRAM
P0 P1 P2 P3
CTL = Low for Binary Count
3
CTL = High for BCD Count
CLOCK
9
CASCADE 7
FEEDBACK
4
5
6
BINARY/BCD
COUNTER #1
CTL1 CTL2
2
10
P4 P5 P6 P7
11 12 13
CLOCK
LOAD
ZERO DETECT ENCODER
14
BINARY/BCD
COUNTER #2
VDD = PIN 16
VSS = PIN 8
15
Q
1 ZERO
DETECT
REV 3
1/94
MOTOROLA
Motorola, Inc. 1995
CMOS LOGIC DATA
MC14569B
1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
IT
5.0
10
15
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
(VO = 0.5 or 4.5 Vdc) “1” Level
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
Vdc
mAdc
IT = (0.58 µA/kHz) f + IDD
IT = (1.20 µA/kHz) f + IDD
IT = (1.95 µA/kHz) f + IDD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
MC14569B
2
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
All Types
VDD
Vdc
Min
Typ #
Max
Unit
Output Rise Time
tTLH
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Output Fall Time
tTHL
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Turn–On Delay Time
Zero Detect Output
tPLH
5.0
10
15
—
—
—
420
175
125
700
300
250
5.0
10
15
—
—
—
675
285
200
1200
500
400
5.0
10
15
—
—
—
380
150
100
600
300
200
5.0
10
15
—
—
—
530
225
155
1000
400
300
ns
tWH
5.0
10
15
300
150
115
100
45
30
—
—
—
ns
fcl
5.0
10
15
—
—
—
3.5
9.5
13.0
2.1
5.1
7.8
MHz
tTLH, tTHL
5.0
10
15
Q Output
Turn–Off Delay Time
Zero Detect Output
ns
ns
tPHL
Q Output
Clock Pulse Width
Clock Pulse Frequency
Clock Pulse Rise and Fall Time
ns
NO LIMIT
µs
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
SWITCHING WAVEFORMS
20 ns
20 ns
CLOCK
10%
90%
50%
fin = fmax
tWH
tPLH
Q
10%
tPHL
90%
50%
tTLH
tTHL
Figure 1.
20 ns
20 ns
CLOCK
10%
90%
50%
tWH
tPLH
tPHL
90%
ZERO DETECT
10%
tTLH
tTHL
Figure 2.
MOTOROLA CMOS LOGIC DATA
MC14569B
3
PIN DESCRIPTIONS
INPUTS
CONTROLS
P0, P1, P2, P3 (Pins 3, 4, 5, 6) — Preset Inputs. Programmable inputs for the least significant counter. May be binary
or BCD depending on the control input.
Cascade Feedback (Pin 7) — This pin is normally set
high. When low, loading of the preset inputs (P0 through P7)
is inhibited, i.e., P0 through P7 are “don’t cares.” Refer to
Table 1 for output characteristics.
P4, P5, P6, P7 (Pins 11, 12, 13, 14) — Preset Inputs. Programmable inputs for the most significant counter. May be
binary or BCD depending on the control input.
Clock (Pin 9) — Preset data is decremented by one on
each positive transition of this signal.
OUTPUTS
CTL1 (Pin 2) — This pin controls the counting mode of the
least significant counter. When set high, counting mode is
BCD. When set low, counting mode is binary.
CTL2 (Pin 10) — This pin controls the counting mode of
the most significant counter. When set high, counting mode
is BCD. When set low, counting mode is binary.
SUPPLY PINS
Zero Detect (Pin 1) — This output is normally low and
goes high for one clock cycle when the counter has decremented to zero.
VSS (Pin 18) — Negative Supply Voltage. This pin is usually connected to ground.
Q (Pin 15) — Output of the last stage of the most significant counter. This output will be inactive unless the preset
input P7 has been set high.
VDD (Pin 16) — Positive Supply Voltage. This pin is connected to a positive supply voltage ranging from 3.0 volts to
18.0 volts.
OPERATING CHARACTERISTICS
The MC14569B is a programmable divide–by–N dual 4–bit
down counter. This counter may be programmed (i.e., preset) in BCD or binary code through inputs P0 to P7. For each
counter, the counting sequence may be chosen independently by applying a high (for BCD count) or a low (for binary
count) to the control inputs CTL1 and CTL2.
The divide ratio N (N being the value programmed on the
preset inputs P0 to P7) is automatically loaded into the
counter as soon as the count 1 is detected. Therefore, a division ratio of one is not possible. After N clock cycles, one
pulse appears on the Zero Detect output. (See Timing Diagram.) The Q output is the output of the last stage of the most
significant counter (See Tables 1 through 5, Mode Controls.)
When cascading the MC14569B to the MC14568B,
MC14522B or the MC14526B, the Cascade Feedback input,
Q, and Zero Detect outputs must be respectively connected
to “0”, Clock, and Load of the following counter. If the
MC14569B is used alone, Cascade Feedback must be connected to VDD.
18
CL = 50 pF
f, FREQUENCY (MHz), TYPICAL
16
PIN ASSIGNMENT
14
12
VDD = 15 V
10
8.0
10 V
6.0
4.0
5.0 V
2.0
0
– 40
– 20
MC14569B
4
0
+ 20
+ 40
+ 60
TA, AMBIENT TEMPERATURE (°C)
+ 80
ZERO
DETECT
CTL1
1
16
VDD
2
15
Q
P0
3
14
P7
P1
4
13
P6
P2
5
12
P5
P3
CASCADE
FEEDBACK
VSS
6
11
P4
7
10
CTL2
8
9
CLOCK
+ 100
MOTOROLA CMOS LOGIC DATA
Table 1. Mode Controls (Cascade Feedback = Low)
Counter Control Values
Divide Ratio
CTL1
CTL2
Zero Detect
Q
0
0
1
1
0
1
0
1
256
160
160
100
256
160
160
100
NOTE: Data Preset Inputs (P0–P7) are “Don’t Cares” while Cascade Feedback is
Low.
Table 2. Mode Controls (CTL1 = Low, CTL2 = Low, Cascade Feedback = High)
Preset Inputs
Divide Ratio
P7
P6
P5
P4
P3
P2
P1
P0
Zero
Detect
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
256
X
2
3
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
15
16
0
0
1
0
0
0
0
0
32
0
1
0
0
0
0
0
0
64
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
27
1
26
128
64
Q
Comments
Max Count
Illegal State
Min Count
127
128
256
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
128
0
0
0
136
136
1
25
1
24
1
23
1
22
1
21
1
20
255
255
32
16
8
4
2
1
Counter #2
Binary
Counter #1
Binary
Q Output Active
Bit Value
Counting
Sequence
X = No Output (Always Low)
MOTOROLA CMOS LOGIC DATA
MC14569B
5
Table 3. Mode Controls (CTL1 = High, CTL2 = Low, Cascade Feedback = High)
Divide Ratio
Preset Inputs
P7
P6
P5
P4
P3
P2
P1
P0
Zero
Detect
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
160
X
2
3
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
9
10
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
0
19
20
0
0
1
1
0
0
0
0
30
0
1
0
0
0
0
0
0
40
0
1
0
1
0
0
0
0
50
0
1
1
0
0
0
0
0
60
0
1
1
1
0
0
0
0
70
1
0
0
0
0
0
0
0
1
0
0
1
0
1
1
Q
Comments
Max Count
Illegal State
Min Count
80
160
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
80
0
0
0
90
90
1
1
0
0
0
0
150
150
1
1
1
1
1
0
0
1
159
159
80
40
20
10
8
4
2
1
Counter #2
Binary
Counter #1
BCD
Q Output Active
Bit Value
Counting
Sequence
X = No Output (Always Low)
MC14569B
6
MOTOROLA CMOS LOGIC DATA
Table 4. Mode Controls (CTL1 = Low, CTL2 = High, Cascade Feedback = High)
Divide Ratio
Preset Values
P7
P6
P5
P4
P3
P2
P1
P0
Zero
Detect
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
160
X
2
3
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
15
16
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
31
32
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
Q
Comments
Max Count
Illegal State
Min Count
48
160
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
64
X
0
1
0
0
0
0
80
X
0
1
1
1
0
0
0
0
112
X
1
0
0
0
0
0
0
0
128
128
1
0
0
1
0
0
0
0
144
144
1
27
0
26
0
25
1
24
1
23
1
22
1
21
1
20
159
159
64
32
16
8
4
2
1
128
Counter #2
BCD
Counter #1
Binary
Q Output Active
Bit Value
Counting
Sequence
X = No Output (Always Low)
MOTOROLA CMOS LOGIC DATA
MC14569B
7
Table 5. Mode Controls (CTL1 = High, CTL2 = High, Cascade Feedback = High)
Divide Ratio
Preset Values
P7
P6
P5
P4
P3
P2
P1
P0
Zero
Detect
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
100
X
2
3
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
9
10
0
0
1
1
0
0
0
0
30
0
1
0
0
0
0
0
0
40
0
1
0
1
0
0
0
0
50
0
1
1
1
0
0
0
0
70
1
0
0
0
0
0
0
0
1
0
0
1
0
1
0
80
40
Q
Comments
Max Count
illegal state
Min Count
80
100
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
80
0
0
0
90
90
0
1
1
0
0
1
99
99
20
10
8
4
2
1
Counter #2
BCD
Q Output Active
Bit Value
Counter #1
BCD
Counting
Sequence
X = No Output (Always Low)
TIMING DIAGRAM MC14569B
CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DIVIDE
BY 2
ZERO
DETECT
OUTPUT
DIVIDE
BY 3
DIVIDE
BY 4
DIVIDE
BY 12
MC14569B
8
MOTOROLA CMOS LOGIC DATA
LOGIC DIAGRAM
CTL1
2
DP Q
D
DP Q
P0
P1
P2
3
D
DP Q
4
5
P3
PE
C
D
PE
C
DP Q
PE
D
C
DP Q
D
6
PE
C
DP Q
D
DP Q
D
DP Q
D
IU
PE
C
PE
C
PE
C
PE
C
VDD
CASCADE 7
FEEDBACK
CLOCK
P4
P5
P6
P7
CTL2
11
12
13
14
VDD
9
1 ZERO
DETECT
DP D
Q
PE
DP D
Q
PE
DP D
Q
PE
DP D
Q
PE
C
C
C
C
10
MOTOROLA CMOS LOGIC DATA
15
MC14569B
9
TYPICAL APPLICATIONS
fin
C
CF
Q
C
MC14569B
PE
ZERO DETECT
CF
MC14522B
OR
MC14526B
Q4
C
“0”
PE
DP0 – – – – – – DP3
CF
MC14522B
OR
MC14526B
Q4
Q1/C2
“0”
PE
MC14568B
DP0 – – – – – – DP3
“0”
DP0 – – – – – – DP3
LSD
fout
MSD
Figure 3. Cascading MC14568B and MC14522B or MC14526B with MC14569B
(40 kHz)
PCin
C1
CT1
VSS
“0”
fout
VCO
PCout
G
(144 – 146 MHz)
VSS
VSS
F
Q1/C2
PE
VDD
DP0 – – – – DP3
MC14011
CF
Q
MC14569B
C
ZERO DETECT
MIXER
2k
2M
CRYSTAL
OSCILLATOR
Frequencies shown in parenthesis are given as an example
(143.5 MHz)
Figure 4. Frequency Synthesizer with MC14568B and MC14569B Using a Mixer
(Channel Spacing 10 kHz)
MC14569B
10
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
C
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
–––
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
–––
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
S
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
J
16 PL
0.25 (0.010)
MOTOROLA CMOS LOGIC DATA
M
T A
M
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MC14569B
11
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–02
ISSUE A
–A–
16
9
–B–
8X
P
0.010 (0.25)
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
M
B
M
8
16X
J
D
0.010 (0.25)
M
T A
S
B
S
F
R X 45 _
C
–T–
14X
G
K
SEATING
PLANE
M
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
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MC14569B
12
◊
*MC14569B/D*
MOTOROLA CMOS LOGIC
DATA
MC14569B/D