MOTOROLA MC14541BCP

SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14541B programmable timer consists of a 16–stage binary
counter, an integrated oscillator for use with an external capacitor and two
resistors, an automatic power–on reset circuit, and output control logic.
Timing is initialized by turning on power, whereupon the power–on reset is
enabled and initializes the counter, within the specified VDD range. With the
power already on, an external reset pulse can be applied. Upon release of
the initial reset command, the oscillator will oscillate with a frequency
determined by the external RC network. The 16–stage counter divides the
oscillator frequency (fosc) with the nth stage frequency being fosc/2n.
• Available Outputs 28, 210, 213 or 216
• Increments on Positive Edge Clock Transitions
• Built–in Low Power RC Oscillator (± 2% accuracy over temperature
range and ± 20% supply and ± 3% over processing at < 10 kHz)
• Oscillator May Be Bypassed if External Clock Is Available (Apply
external clock to Pin 3)
• External Master Reset Totally Independent of Automatic Reset
Operation
• Operates as 2n Frequency Divider or Single Transition Timer
• Q/Q Select Provides Output Logic Level Flexibility
• Reset (auto or master) Disables Oscillator During Resetting to Provide
No Active Power Dissipation
• Clock Conditioning Circuit Permits Operation with Very Slow Clock Rise
and Fall Times
• Automatic Reset Initializes All Counters On Power Up
• Supply Voltage Range = 3.0 Vdc to 18 Vdc with Auto Reset
Disabled (Pin 5 = VDD)
= 8.5 Vdc to 18 Vdc with Auto Reset
Enabled (Pin 5 = VSS)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
Value
Unit
– 0.5 to + 18.0
V
– 0.5 to VDD + 0.5
V
Input Current (DC or Transient), per Pin
± 10
mA
Iout
Output Current (DC or Transient), per Pin
± 45
mA
PD
Power Dissipation, per Package†
Tstg
Storage Temperature
VDD
Vin, Vout
Iin
TL
Parameter
DC Supply Voltage
Input or Output Voltage (DC or Transient)
Lead Temperature (8–Second Soldering)
500
mW
– 65 to + 150
_C
260
_C
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
PIN ASSIGNMENT
Rtc
1
14
VDD
Ctc
2
13
B
RS
3
12
A
NC
4
11
NC
AR
5
10
MODE
MR
6
9
Q/Q SEL
VSS
7
8
Q
NC = NO CONNECTION
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
REV 3
1/94
MOTOROLA
Motorola, Inc. 1995
CMOS LOGIC DATA
MC14541B
1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
10
15
– 7.96
– 4.19
– 16.3
—
—
—
– 6.42
– 3.38
– 13.2
– 12.83
– 6.75
– 26.33
—
—
—
– 4.49
– 2.37
– 9.24
—
—
—
IOL
5.0
10
15
1.93
4.96
19.3
—
—
—
1.56
4.0
15.6
3.12
8.0
31.2
—
—
—
1.09
2.8
10.9
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Pin 5 is High)
Auto Reset Disabled
IDD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
Auto Reset Quiescent Current
(Pin 5 is low)
IDDR
10
15
—
—
250
500
—
—
30
82
250
500
—
—
1500
2000
µAdc
Supply Current**†
(Dynamic plus Quiescent)
ID
5.0
10
15
Vin = 0 or VDD
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
“1” Level
VIH
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
mAdc
ID = (0.4 µA/kHz) f + IDD
ID = (0.8 µA/kHz) f + IDD
ID = (1.2 µA/kHz) f + IDD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†When using the on chip oscillator the total supply current (in µAdc) becomes: IT = ID + 2 Ctc V DD f x 10–3 where ID is in µA, C tc is in pF,
VDD in Volts DC, and f in kHz. (see Fig. 3) Dissipation during power–on with automatic reset enabled is typically 50 µA @ VDD = 10 Vdc.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
MC14541B
2
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
VDD
Min
Typ #
Max
5.0
10
15
—
—
—
100
50
40
200
100
80
5.0
10
15
—
—
—
3.5
1.25
0.9
10.5
3.8
2.9
5.0
10
15
—
—
—
6.0
3.5
2.5
18
10
7.5
tWH(cl)
5.0
10
15
900
300
225
300
100
85
—
—
—
ns
fcl
5.0
10
15
—
—
—
1.5
4.0
6.0
0.75
2.0
3.0
MHz
tWH(R)
5.0
10
15
900
300
225
300
100
85
—
—
—
ns
trem
5.0
10
15
420
200
200
210
100
100
—
—
—
ns
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
Propagation Delay, Clock to Q (28 Output)
tPLH, tPHL = (1.7 ns/pF) CL + 3415 ns
tPLH, tPHL = (0.66 ns/pF) CL + 1217 ns
tPLH, tPHL = (0.5 ns/pF) CL + 875 ns
Propagation Delay, Clock to Q (216 Output)
tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns
tPHL, tPLH = (0.66 ns/pF) CL + 3467 ns
tPHL, tPLH = (0.5 ns/pF) CL + 2475 ns
tPLH
tPHL
tPHL
tPLH
Clock Pulse Width
Clock Pulse Frequency (50% Duty Cycle)
MR Pulse Width
Master Reset Removal Time
Unit
ns
µs
µs
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
VDD
PULSE
GENERATOR
VDD
PULSE
GENERATOR
RS
AR
Q/Q SELECT
MODE
RS
AR
Q/Q SELECT
MODE
A
B
MR
Q
A
B
MR
CL
VSS
20 ns
20 ns
RS
90% 50%
10%
50%
DUTY CYCLE
Figure 1. Power Dissipation Test Circuit
and Waveform
MOTOROLA CMOS LOGIC DATA
CL
VSS
(Rtc AND Ctc OUTPUTS ARE LEFT OPEN)
20 ns
Q
20 ns
90% 50%
10%
50%
tPHL
tPLH
50%
Q
tTLH
90%
10%
50%
tTHL
Figure 2. Switching Time Test Circuit
and Waveforms
MC14541B
3
EXPANDED BLOCK DIAGRAM
A 12
B 13
1 OF 4
MUX
Rtc 1
Ctc 2
OSC
RS 3
RESET
AUTO RESET
5
8 Q
210 213 216
C 8–STAGE
COUNTER
RESET
8–STAGE 8
2
C
COUNTER
RESET
POWER–ON
RESET
6
MASTER RESET
10
MODE
9
Q/Q
SELECT
VDD = PIN 14
VSS = PIN 7
FREQUENCY SELECTION TABLE
TRUTH TABLE
State
A
B
Number of
Counter Stages
n
0
0
13
8192
0
1
10
1024
1
0
8
256
1
1
16
65536
Count
2n
Pin
0
1
Auto Reset Operating
Auto Reset Disabled
Master Reset, 6
Timer Operational
Master Reset On
Q / Q,
9
Output Initially Low
After Reset
Output Initially High
After Reset
Mode,
10
Single Cycle Mode
Recycle Mode
Auto Reset,
5
3
TO CLOCK
CIRCUIT
INTERNAL
RESET
2
1
Ctc
RS
RTC
Figure 3. Oscillator Circuit Using RC Configuration
MC14541B
4
MOTOROLA CMOS LOGIC DATA
TYPICAL RC OSCILLATOR CHARACTERISTICS
8.0
100
VDD = 15 V
0
10 V
– 4.0
– 8.0
5.0 V
– 12
RTC = 56 kΩ,
C = 1000 pF
– 16
– 55
– 25
VDD = 10 V
50
f, OSCILLATOR FREQUENCY (kHz)
FREQUENCY DEVIATION (%)
4.0
RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C
RS = 120 kΩ, f = 7.8 kHz @ VDD = 10 V, TA = 25°C
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS ≈ 2RTC)
20
10
5.0
2.0
1.0
f AS A FUNCTION
OF C
(RTC = 56 kΩ)
(RS = 120 kΩ)
0.5
0.2
0.1
1.0 k
0.0001
Figure 4. RC Oscillator Stability
10 k
100 k
RTC, RESISTANCE (OHMS)
1.0 m
0.001
0.01
C, CAPACITANCE (µF)
0.1
Figure 5. RC Oscillator Frequency as a
Function of Rtc and Ctc
OPERATING CHARACTERISTICS
With Auto Reset pin set to a “0” the counter circuit is initialized by turning on power. Or with power already on, the
counter circuit is reset when the Master Reset pin is set to a
“1”. Both types of reset will result in synchronously resetting
all counter stages independent of counter state. Auto Reset
pin when set to a “1” provides a low power operation.
The RC oscillator as shown in Figure 3 will oscillate with a
frequency determined by the external RC network i.e.,
f=
1
2.3 RtcCtc
if (1 kHz
v f v 100 kHz)
and RS ≈ 2 Rtc
where RS ≥ 10 kΩ
The time select inputs (A and B) provide a two–bit address
to output any one of four counter stages (28, 210, 213 and
216). The 2n counts as shown in the Frequency Selection
Table represents the Q output of the Nth stage of the counter.
When A is “1”, 216 is selected for both states of B. However,
when B is “0”, normal counting is interrupted and the 9th
counter stage receives its clock directly from the oscillator
(i.e., effectively outputting 28).
The Q/Q select output control pin provides for a choice of
output level. When the counter is in a reset condition and
Q/Q select pin is set to a “0” the Q output is a “0”, correspondingly when Q/Q select pin is set to a “1” the Q output is
a “1”.
When the mode control pin is set to a “1”, the selected
count is continually transmitted to the output. But, with mode
pin “0” and after a reset condition the RS flip–flop (see Expanded Block Diagram) resets, counting commences, and
after 2n–1 counts the RS flip–flop sets which causes the output to change state. Hence, after another 2n–1 counts the
output will not change. Thus, a Master Reset pulse must be
applied or a change in the mode pin level is required to reset
the single cycle operation.
DIGITAL TIMER APPLICATION
Rtc
Ctc
NC
RS
AR
MR
INPUT
1
14
2
13
VDD
B
3
12
A
4
11
5
10
6
9
7
8
N.C.
MODE
Q/Q
VDD
OUTPUT
tMR
When Master Reset (MR) receives a positive pulse, the internal counters and latch are reset. The Q output goes high
and remains high until the selected (via A and B) number of
clock pulses are counted, the Q output then goes low and remains low until another input pulse is received.
This “one shot” is fully retriggerable and as accurate as the
input frequency. An external clock can be used (pin 3 is the
clock input, pins 1 and 2 are outputs) if additional accuracy is
needed.
Notice that a setup time equal to the desired pulse width
output is required immediately following initial power up, during which time Q output will be high.
t + tMR
MOTOROLA CMOS LOGIC DATA
MC14541B
5
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
C
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
–––
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
–––
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
S
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
L
S
–T–
K
H
G
D
J
16 PL
0.25 (0.010)
MC14541B
6
SEATING
PLANE
M
T A
M
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B–
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
–T–
SEATING
PLANE
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
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MOTOROLA CMOS LOGIC DATA
◊
*MC14541B/D*
MC14541B
MC14541B/D
7