MOTOROLA MC14527BCL

SEMICONDUCTOR TECHNICAL DATA
The MC14527B BCD rate multiplier (DRM) provides an output pulse rate
based upon the BCD input number. For example, if 6 is the BCD input
number, there will be six output pulses for every ten input pulses. This part
may be used for arithmetic operations including multiplication and division.
Typical applications include digital filters, motor speed control and frequency
synthesizers.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Output Clocked on the Negative Going Edge of Clock
• Strobe for Inhibiting or Enabling Outputs
• Enable and Cascade Inputs for Cascade Operation of Two or More
DRMs
• “9” Output for the Parallel Enable Configuration and DRMs in Cascade
• Complementary Outputs
• Clear and Set to Nine Inputs
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
Parameter
VDD
DC Supply Voltage
Value
Unit
– 0.5 to + 18.0
V
Vin, Vout
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current (DC or Transient),
per Pin
± 10
mA
500
mW
– 65 to + 150
_C
PD
Power Dissipation, per Package†
Tstg
Storage Temperature
TL
Lead Temperature (8–Second Soldering)
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
TA = – 55° to 125°C for all packages.
BLOCK DIAGRAM
4
12
RATE INPUT
Output
MULTIPLIER
Number of Pulses
Inputs
11
9
10
14
TRUTH TABLE (X = Don’t Care, *D = Most Significant Bit)
Logic Level
D*
C
B
A
No. of
Clock
Pulses
Ein
Strobe
Cascade
Clear
Set
Out
Out
Eout
“9”
0
0
0
0
0
0
0
1
10
10
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
10
10
10
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
3
4
5
6
2
3
4
5
6
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
0
0
1
0
0
1
1
1
0
1
0
1
10
10
10
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
8
9
8
9
7
8
9
8
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
1
1
1
1
X
0
0
1
1
X
0
1
0
1
X
10
10
10
10
10
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
9
8
9
—
8
9
8
9
—
1
1
1
1
—
1
1
1
1
—
X
X
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
10
10
10
10
10
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
10
0
0
1
0
10
1
1
1
1
1
1
0
1
1
0
0
1
Plastic
Ceramic
SOIC
15
2
3
S
Eout
CASC
Ein
CLOCK OUT
ST
A
OUT
B
C
“9”
D
CLEAR
7
6
5
1
13
VDD = PIN 16
VSS = PIN 8
REV 3
1/94
MOTOROLA
Motorola, Inc. 1995
CMOS LOGIC DATA
MC14527B
1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
“1” Level
VIH
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
mAdc
IT = (0.85 µA/kHz) f + IDD
IT = (1.75 µA/kHz) f + IDD
IT = (2.60 µA/kHz) f + IDD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.0012.
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14527B
2
PIN ASSIGNMENT
“9”
1
16
VDD
C
2
15
B
D
3
14
A
S
4
13
CLEAR
OUT
5
12
CASC
OUT
6
11
Ein
Eout
7
10
ST
VSS
8
9
CLOCK
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
Propagation Delay Time
Clock to Out
tPLH, tPHL = (1.7 ns/pF) CL + 115 ns
tPLH, tPHL = (0.66 ns/pF) CL + 67 ns
tPLH, tPHL = (0.5 ns/pF) CL + 45 ns
tPHL,
tPHL
Clock to Out
tPLH, tPHL = (1.7 ns/pF) CL + 40 ns
tPLH, tPHL = (0.66 ns/pF) CL + 32 ns
tPLH, tPHL = (0.5 ns/pF) CL + 20 ns
tPLH,
tPHL
Clock to Eout
tPLH, tPHL = (1.7 ns/pF) CL + 210 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 60 ns
tPLH.
tPHL
Clock to “9”
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns
tPLH, tPHL = (0.66 ns/pF) CL + 122 ns
tPLH, tPHL = (0.5 ns/pF) CL + 85 ns
tPLH,
tPHL
Set or Clear to Out
tPHL = (1.7 ns/pF) CL + 295 ns
tPHL = (0.66 ns/pF) CL + 132 ns
tPHL = (0.5 ns/pF) CL + 85 ns
tPHL
Cascade to Out
tPHL = (1.7 ns/pF) CL + 40 ns
tPHL = (0.66 ns/pF) CL + 32 ns
tPHL = (0.5 ns/pF) CL + 20 ns
tPLH
Strobe to Out
tPHL = (1.7 ns/pF) CL + 145 ns
tPHL = (0.66 ns/pF) CL + 72 ns
tPHL = (0.5 ns/pF) CL + 45 ns
tPLH
VDD
Min
Typ #
Max
5.0
10
15
—
—
—
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
—
—
—
200
100
70
400
200
140
5.0
10
15
—
—
—
125
65
45
250
130
90
5.0
10
15
—
—
—
295
130
85
590
260
170
5.0
10
15
—
—
—
400
155
110
800
310
220
5.0
10
15
—
—
—
380
165
110
760
330
220
5.0
10
15
—
—
—
125
65
45
250
130
90
5.0
10
15
—
—
—
230
105
70
260
210
140
tWH
5.0
10
15
500
200
150
250
110
80
—
—
—
ns
fcl
5.0
10
15
—
—
—
2.0
4.5
6.0
1.2
2.5
3.5
MHz
Clock Pulse Rise and Fall Time
tTLH,
tTHL
5.0
10
15
—
—
—
—
—
—
15
5
4
µs
Set or Clear Pulse Width
tWH
5.0
10
15
240
100
75
80
35
30
—
—
—
ns
Set Removal Time
trem
5.0
10
15
0
0
0
– 20
– 10
– 7.5
—
—
—
ns
tsu
5.0
10
15
400
150
120
175
60
45
—
—
—
ns
Clock Pulse Width
Clock Pulse Frequency
Enable In Setup Time
ns
ns
ns
ns
ns
ns
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MOTOROLA CMOS LOGIC DATA
MC14527B
3
0 1234 5678 90 123 4
CLOCK
VDD
Qa
Qb
Qc
S
CASC Eout
Ein
CLOCK
OUT
ST
A
OUT
B
C
“9”
D
CLEAR
PULSE
GENERATOR
MULTIPLIER
PRESET NO.
Qd
R1
R2
R3
R4
OUTPUT (PIN 6)
A ENABLED
VSS
B ENABLED
C ENABLED
D ENABLED
Figure 1. Test Circuit and Timing Diagram
Eout
OUTPUT (PIN 6)
(PRESET NO. OF 1)
(PRESET NO. OF 2)
(PRESET NO. OF 3)
(PRESET NO. OF 4)
VDD
S
CASC
Ein
CLOCK
ST
A
B
C
D
CLEAR
PROGRAMMABLE
PULSE
GENERATOR
(PRESET NO. OF 5)
Eout
(PRESET NO. OF 6)
(PRESET NO. OF 7)
OUT
(PRESET NO. OF 8)
OUT
CL
“9”
CL
CL
VSS
20 ns
20 ns
tTLH
CLOCK
(PRESET NO. OF 9)
CL
1
fcl
tTHL
90%
10%
50%
SET
trem
ENABLE IN
50%
tsu
SET
tWH
50%
tPHL
90%
10%
50%
OUT
tPLH
tTLH
tPHL
tTHL
Figure 2. Switching Time Test Circuit and Waveforms
MC14527B
4
MOTOROLA CMOS LOGIC DATA
VDD
0.01 µF
CERAMIC
500
pF
ID
VDD
PULSE
GENERATOR
S
CASC Eout
Ein
CLOCK
OUT
ST
A
OUT
B
C
D
“9”
CLEAR
VSS
20 ns
CLOCK
CL
CL
20 ns
VDD
90%
50%
10%
VARIABLE WIDTH
VSS
50% DUTY CYCLE
CL
CL
Figure 3. Power Dissipation Test Circuit and Waveform
LOGIC DIAGRAM
ENABLE IN
11
3
STROBE CASCADE
10
12
D C B A
2 15 14
Q
T
C a
R
Q
R1
CLOCK
R2
T
9
6 OUT
Q
5 OUT
C b
R
R3
R4
T
S
Q
VDD = PIN 16
VSS = PIN 8
C c
R
Q
T S Q
1 “9”
C d
R
Q
7 ENABLE OUT
CLEAR
13
SET TO NINE
MOTOROLA CMOS LOGIC DATA
4
MC14527B
5
MOST SIGNIFICANT
DIGIT
1
0
0
1
A
OUT
B
C
1
D
Eout
CLOCK
CASC
Ein
“9”
ST
CLEAR S
LEAST SIGNIFICANT
DIGIT
0
0
1
0
A
OUT
B
C
2
D
Eout
CLOCK
CASC
Ein
“9”
ST
CLEAR S
NOTE: More than two MC14527Bs
may be cascaded using this
configuration.
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
CLOCK
CLOCK
OUT
DRM 2
One of four output pulses contributed by DRM 2 to
output for every 100 clock pulses in for preset No. of 94.
Figure 4. Two MC14527Bs in Cascade with Preset No. of 94
MC14527B
6
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
C
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
–––
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
–––
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
S
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
J
16 PL
0.25 (0.010)
MOTOROLA CMOS LOGIC DATA
M
T A
M
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MC14527B
7
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–02
ISSUE A
–A–
16
9
–B–
8X
P
0.010 (0.25)
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
M
B
M
8
16X
J
D
0.010 (0.25)
M
T A
S
B
S
F
R X 45 _
C
–T–
14X
G
K
SEATING
PLANE
M
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,
Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered
trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: [email protected] – TOUCHTONE 602–244–6609
INTERNET: http://Design–NET.com
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MC14527B
8
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*MC14527B/D*
MOTOROLA CMOS LOGIC
DATA
MC14527B/D