SEMICONDUCTOR TECHNICAL DATA The MC14510B synchronous up/down BCD counter is constructed with MOS P–channel and N–channel enhancement mode devices in a monolithic structure. The counter consists of type D flip–flop stages with a gating structure to provide type T flip–flop capability. This counter can be preset by applying the desired value in BCD to the Preset inputs (P1, P2, P3, P4) and then bringing the Preset Enable (PE) high. The direction of counting is controlled by applying a high (for up counting) or a low (for down counting) to the UP/DOWN input. The state of the counter changes on the positive transition of the clock input. Cascading can be accomplished by connecting the Carry Out to the Carry In of the next stage while clocking each counter in parallel. The outputs (Q1, Q2, Q3, Q4) can be reset to a low state by applying a high to the Reset (R) pin. This CMOS counter finds primary use in up/down and difference counting. Other applications include: (1) Frequency synthesizer applications where low power dissipation and/or high noise immunity is desired, (2) Analog–to– digital and digital–to–analog conversions, and (3) Magnitude and sign generation. • • • • Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Internally Synchronous for High Speed Logic Edge–Clocked Design — Count Occurs on Positive Going Edge of Clock • Asynchronous Preset Enable Operation • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Parameter DC Supply Voltage Value Unit – 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient), per Pin ± 10 mA PD Power Dissipation, per Package† Tstg Storage Temperature TL Lead Temperature (8–Second Soldering) 500 mW – 65 to + 150 _C 260 _C * Maximum Ratings are those values beyond which damage to the may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C TRUTH TABLE Carry In Up/Down Preset Enable Reset Clock Action 1 X 0 0 X No Count 0 1 0 0 Count Up 0 0 0 0 X X 1 0 X Count Down Preset X X X 1 X Reset L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC TA = – 55° to 125°C for all packages. BLOCK DIAGRAM 1 5 9 10 15 4 12 13 3 Q1 PE CARRY IN R Q2 UP/DOWN CLOCK Q3 P1 P2 Q4 P3 CARRY P4 OUT 6 11 14 2 7 VDD = PIN 16 VSS = PIN 8 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. v v X = Don’t Care NOTE: When counting up, the Carry Out signal is normally high, and is low only when Q1 and Q4 are high and Carry In is low. When counting down, Carry Out is low only when Q1 through Q4 and Carry In are low. REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14510B 351 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol – 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — 5.0 5.0 10 15 – 3.0 – 0.64 – 1.6 – 4.2 — — — — – 2.4 – 0.51 – 1.3 – 3.4 – 4.2 – 0.88 – 2.25 – 8.8 — — — — – 1.7 – 0.36 – 0.9 – 2.4 — — — — IOL 5.0 10 15 0.64 1.6 4.2 — — — 0.51 1.3 3.4 0.88 2.25 8.8 — — — 0.36 0.9 2.4 — — — mAdc Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) IDD 5.0 10 15 — — — 5.0 10 20 — — — 0.005 0.010 0.015 5.0 10 20 — — — 150 300 600 µAdc IT 5.0 10 15 Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc IOH Source Sink Total Supply Current**† (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) mAdc IT = (0.58 µA/kHz) f + IDD IT = (1.20 µA/kHz) f + IDD IT = (1.70 µA/kHz) f + IDD µAdc #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. ** The formulas given are for the typical characteristics only at 25_C. ā †To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001. PIN ASSIGNMENT MC14510B 352 PE 1 16 VDD Q4 2 15 C P4 3 14 Q3 P1 4 13 P3 CARRY IN 5 12 P2 Q1 6 11 Q2 CARRY OUT 7 10 U/D VSS 8 9 R MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C, See Figure 2) All Types Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time Clock to Q tPLH, tPHL = (1.7 ns/pF) CL + 230 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = (0.5 ns/pF) CL + 75 ns Symbol tTLH, tTHL tPLH, tPHL Clock to Carry Out tPLH, tPHL = (1.7 ns/pF) CL + 230 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = (0.5 ns/pF) CL + 75 ns tPLH, tPHL Carry In to Carry Out tPLH, tPHL = (1.7 ns/pF) CL + 230 ns tPLH, tPHL = (0.66 ns/pF) CL + 47 ns tPLH, tPHL = (0.5 ns/pF) CL + 35 ns tPLH, tPHL Preset or Reset to Q tPLH, tPHL = (1.7 ns/pF) CL + 230 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = (0.5 ns/pF) CL + 75 ns tPLH, tPHL VDD Min Typ # Max 5.0 10 15 — — — 100 50 40 200 100 80 Unit ns ns 5.0 10 15 — — — 315 130 100 630 260 200 5.0 10 15 — — — 315 130 100 630 260 200 5.0 10 15 — — — 180 80 60 360 160 120 5.0 10 15 — — — 315 130 100 630 260 200 5.0 10 15 — — — 550 225 150 1100 450 300 ns ns ns Preset or Reset to Carry Out tPLH, tPHL = (1.7 ns/pF) CL + 465 ns tPLH, tPHL = (0.66 ns/pF) CL + 192 ns tPLH, tPHL = (0.5 ns/pF) CL + 125 ns Reset Pulse Width tPLH, tPHL tw(H) 5.0 10 15 360 210 160 180 105 80 — — — ns Clock Pulse Width tw(H) 5.0 10 15 350 170 140 200 100 75 — — — ns fcl 5.0 10 15 — — — 3.0 6.0 8.0 1.5 3.0 4.0 MHz Preset or Reset Removal Time The Preset or Reset Signal must be low prior to a positive–going transition of the clock. trem 5.0 10 15 650 230 180 325 115 90 — — — ns Clock Rise and Fall Time tTLH, tTHL 5.0 10 15 — — — — — — 15 5 4 µs Setup Time Carry In to Clock tsu 5.0 10 15 260 120 100 130 60 50 — — — ns Hold Time Clock to Carry In th 5.0 10 15 0 10 10 – 50 – 15 –5 — — — ns Setup Time Up/Down to Clock tsu 5.0 10 15 500 200 175 250 100 75 — — — ns Hold Time Clock to Up/Down th 5.0 10 15 – 70 – 30 – 20 – 140 – 80 – 50 — — — ns Setup Time Pn to PE tsu 5.0 10 15 – 50 – 30 – 25 – 100 – 65 – 55 — — — ns Hold Time PE to Pn th 5.0 10 15 480 410 410 240 205 205 — — — ns tWH 5.0 10 15 200 100 80 100 50 40 — — — ns Clock Pulse Frequency Preset Enable Pulse Width ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. MOTOROLA CMOS LOGIC DATA MC14510B 353 VDD 0.01 µF CERAMIC ID 500 pF Q1 PE CARRY IN Q2 R UP/DOWN CLOCK Q3 PULSE GENERATOR CL P1 P2 P3 Q4 P4 CARRY OUT CL CL CL CL 20 ns CLOCK 20 ns 50% VDD 90% 10% VSS VARIABLE WIDTH Figure 1. Power Dissipation Test Circuit and Waveform VDD PE Q1 CARRY IN Q2 R UP/DOWN CLOCK Q3 PROGRAMMABLE PULSE GENERATOR CL P1 P2 P3 Q4 P4 CARRY OUT CL CL CL CL VSS tsu CARRY IN OR UP/DOWN trem 1 fcl VDD 50% VSS VDD 50% CLOCK tw(H) VSS VDD tw(H) PRESET ENABLE VSS 20 ns tTLH CARRY OUT ONLY VOH 90% 10% 90% 10% Q1 OR CARRY OUT VOL tPHL tTHL tPLH trem tPLH VDD RESET VSS tw(H) Figure 2. Switching Time Test Circuit and Waveforms MC14510B 354 MOTOROLA CMOS LOGIC DATA LOGIC DIAGRAM P1 4 Q1 6 P2 12 Q2 11 P3 13 Q3 14 P4 3 Q4 2 RESET PRESET ENABLE CLOCK PE CARRY OUT P Q C D PE P PE Q C Q D P PE Q C Q C D Q P D Q Q CARRY IN UP/DOWN STATE DIAGRAM FOR UP COUNTING 0 4 0 15 5 15 5 14 6 14 6 13 7 13 7 8 12 12 1 11 2 10 3 STATE DIAGRAM FOR DOWN COUNTING 9 MOTOROLA CMOS LOGIC DATA 1 11 2 10 3 9 4 8 MC14510B 355 PIN DESCRIPTIONS INPUTS synchronous output is active low and may also be used to indicate terminal count. P1, P2, P3, P4, Preset Inputs (Pins 4, 12, 13, 3) — Data on these inputs is loaded into the counter when PE is taken high. Carry In, (Pin 5) — Active–low input used when cascading stages. Usually connected to Carry Out of the previous stage. While high, clock is inhibited. Clock, (Pin 15) — BCD data is incremented or decremented, depending on the direction of count, on the positive transition of this signal. OUTPUTS CONTROLS PE, Preset Enable (Pin 1) — Asynchronously loads data on the Preset Inputs. This pin is active high and will inhibit the clock when high. R, Reset, (Pin 9) — Asynchronously resets the Q outputs to a low state. This pin is active high and will inhibit the clock when high. Up/Down, (Pin 10) — Controls the direction of count: high for up count, low for down count. SUPPLY PINS Q1, Q2, Q3, Q4, BCD outputs (Pins 6, 11, 14, 2) — BCD data is present on these outputs with Q1 corresponding to the least significant bit. Carry Out, (Pin 7) — Used when cascading stages, this pin is usually connected to Carry In of the next stage. This PRESET ENABLE 0 = COUNT 1 = PRESET Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q1 PE Q2 Q3 Q4 Q1 PE Q2 Q3 Q4 Cout Cin CLOCK Cin CLOCK 1 = UP 0 = DOWN L.S.D. MC14510B U/D R P2 P2 P3 P3 P4 P4 + VDD THUMBWHEEL SWITCHES (OPEN FOR “0”) + VDD P1 P5 Cout M.S.D. MC14510B U/D R P1 P1 CLOCK VSS, Negative Supply Voltage, (Pin 8) — This pin is usually connected to ground. VDD, Positive Supply Voltage, (Pin 16) — This pin is connected to a positive supply voltage ranging from 3.0 Vdc to 18.0 Vdc. P2 P6 P3 TERMINAL COUNT INDICATOR P4 P7 P8 + VDD RESISTORS = 10 kΩ RESET OPEN = COUNT Note: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant Digit (M.S.D.) does not change while Cin is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 9 (count up mode), Cout goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count. The L.S.D. now counts through another cycle (10 clock pulses) and the above cycle is repeated. Figure 3. Presettable Cascaded 8–Bit Up/Down Counter MC14510B 356 MOTOROLA CMOS LOGIC DATA TIMING DIAGRAM FOR THE PRESETTABLE CASCADED 8–BIT UP/DOWN COUNTER CLOCK UP/DOWN CARRY IN (MSD) PE P8 P7 P6 P5 P4 P3 P2 P1 CARRY OUT (MSD) Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 CARRY OUT (LSD) RESET COUNT MSD 6 6 6 7 7 7 7 7 7 7 6 6 6 6 9 9 9 9 9 0 0 0 0 0 0 0 0 COUNT LSD 7 8 9 0 1 2 3 2 1 0 9 8 7 6 6 6 7 8 9 0 1 2 1 0 1 0 0 PRESET ENABLE PRESET ENABLE UP COUNT MOTOROLA CMOS LOGIC DATA DOWN COUNT UP COUNT DOWN COUNT RESET UP COUNT MC14510B 357 fout Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q1 PE Q2 Q3 Q4 Q1 PE Q2 Q3 Q4 Cout Cin CLOCK Cin CLOCK L.S.D. MC14510B U/D R P0 CLOCK (fin) + VDD U/D R P1 P2 P1 P3 P2 P4 P3 + VDD THUMBWHEEL SWITCHES (OPEN FOR “0”) RESET M.S.D. MC14510B P1 P4 P2 P5 P3 P6 BUFFER Cout P4 P7 + VDD RESISTORS = 10 kΩ f fout = in n OPEN = COUNT Note: The programmable frequency divider can be set by applying the desired divide ratio, in BCD, to the preset inputs. For example, the maximum divide ratio of 99 may be obtained by applying a 10011001 to the preset inputs P0 to P7. For this divide operation, both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and should be avoided. Figure 4. Programmable Cascaded Frequency Divider MC14510B 358 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D J 16 PL 0.25 (0.010) MOTOROLA CMOS LOGIC DATA M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MC14510B 359 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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