Buffered 2:1 TMDS Switch AD8193 FEATURES FUNCTIONAL BLOCK DIAGRAM AVCC AVEE CONTROL LOGIC S_SEL VTTI IP_A[3:0] IN_A[3:0] + VTTO 4 4 – SWITCH CORE Rx IP_B[3:0] IN_B[3:0] AD8193 + – 4 Tx 4 4 + – OP[3:0] ON[3:0] 4 BUFFERED 07003-001 HIGH SPEED VTTI Figure 1. TYPICAL APPLICATION APPLICATIONS HDTV SET Advanced television (HDTV) sets Multiple input displays Projectors A/V receivers Set-top boxes HDMI RECEIVER SET-TOP BOX AD8193 DVD PLAYER 07003-002 2 inputs, 1 output HDMI/DVI high speed signal switch Pin-to-pin compatible with the AD8194 Enables HDMI 1.3-compliant receiver 4 TMDS channels per input/output Supports 250 Mbps to 2.25 Gbps data rates Supports 25 MHz to 225 MHz pixel clocks Fully buffered unidirectional inputs/outputs Supports more than 20 m of input cable at 1080i, more than 10 m of input cable at 1080p, and more than 6 meters of input cable at 1080p, 12-bit color Matched 50 Ω input and output on-chip terminations Low added jitter Single-supply operation (3.3 V) Standards compliant: HDMI receiver, DVI 32-lead, 5 mm × 5 mm, RoHS-compliant LFCSP Figure 2. Typical AD8193 Application for HDTV Sets GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD8193 is a low cost quad 2:1 TMDS® switch for high speed HDMI™/DVI video applications. Its primary function is to switch the high speed signals from one of two single-link (HDMI or DVI) sources to the single-link output. The AD8193 is a fully buffered switch solution with 50 Ω input and output terminations, providing full-swing output signal recovery and minimizing reflections for improved system signal integrity. 1. The AD8193 is provided in a space-saving, 32-lead, LFCSP, surface-mount, RoHS-compliant, plastic package and is specified to operate over the −40°C to +85°C temperature range. 4. 2. 3. 5. 6. 7. Data supports rates up to 2.25 Gbps, enabling greater than 1080p deep color (12-bit color) HDMI formats and greater than UXGA (1600 × 2300) DVI resolutions. Fully buffered unidirectional inputs and outputs. Supports more than 20 meters of a typical 24 AWG input cable at 1080i, more than 10 meters at 1080p, and more than 6 meters at 1080p, 12-bit color. Matched 50 Ω on-chip input and output terminations improve system signal integrity. Single-pin source select bit. Input terminations are automatically switched out for the unselected input. Low added jitter. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. AD8193 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................6 Applications....................................................................................... 1 Theory of Operation .........................................................................9 Functional Block Diagram .............................................................. 1 Introduction...................................................................................9 Typical Application........................................................................... 1 Input Channels ..............................................................................9 General Description ......................................................................... 1 Output Channels ........................................................................ 10 Product Highlights ........................................................................... 1 Switching Mode .......................................................................... 10 Revision History ............................................................................... 2 Application Notes ........................................................................... 11 Specifications..................................................................................... 3 Switching High Speed Signals................................................... 11 Absolute Maximum Ratings............................................................ 4 Switching Low Speed Signals.................................................... 11 Thermal Resistance ...................................................................... 4 PCB Layout Guidelines.............................................................. 11 Maximum Power Dissipation ..................................................... 4 Outline Dimensions ....................................................................... 16 ESD Caution.................................................................................. 4 Ordering Guide .......................................................................... 16 Pin Configuration and Function Descriptions............................. 5 REVISION HISTORY 11/07—Revision 0: Initial Version Rev. 0 | Page 2 of 16 AD8193 SPECIFICATIONS TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE Maximum Data Rate (DR) per Channel Bit Error Rate (BER) Added Deterministic Jitter Added Random Jitter Differential Intrapair Skew Differential Interpair Skew 1 INPUT CHARACTERISTICS Input Voltage Swing Input Common-Mode Voltage (VICM) OUTPUT CHARACTERISTICS High Voltage Level Low Voltage Level Rise/Fall Time (20% to 80%) TERMINATION Input Resistance Output Resistance POWER SUPPLY AVCC QUIESCENT CURRENT 2 AVCC VTTI VTTO POWER DISSIPATION 3 SOURCE SELECT INTERFACE Input High Voltage (VIH) Input Low Voltage (VIL) Conditions/Comments Min NRZ 2.25 Typ Max Unit Gbps 10−9 25 1 1 30 At output At output Differential 150 AVCC − 800 Single-ended high speed channel Single-ended high speed channel ps (p-p) ps (rms) ps ps 1200 AVCC mV mV AVCC − 400 178 mV mV ps AVCC AVCC − 600 75 Single-ended Single-ended 50 50 Operating range S_SEL S_SEL 3 Ω Ω 3.3 3.6 V 50 40 40 429 70 54 65 mA mA mA mW 2 0.8 1 V V Differential interpair skew is measured between the TMDS pairs of a single link. Typical value assumes only the selected HDMI/DVI link is active with nominal signal swings and that the unselected HDMI/DVI link is deactivated. Minimum and maximum limits are measured at the respective extremes of input termination resistance and input voltage swing. 3 The total power dissipation excludes power dissipated in the 50 Ω off-chip loads. 2 Rev. 0 | Page 3 of 16 AD8193 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter AVCC to AVEE VTTI VTTO Internal Power Dissipation High Speed Input Voltage High Speed Differential Input Voltage Source Select (S_SEL) Storage Temperature Range Operating Temperature Range Junction Temperature Rating 3.7 V AVCC + 0.6 V AVCC + 0.6 V 1.2 W AVCC − 1.4 V < VIN < AVCC + 0.6 V 2.0 V AVEE − 0.3 V < VIN < AVCC + 0.6 V −65°C to +125°C −40°C to +85°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. θJA is specified for the worst-case conditions: a device soldered in a 4-layer JEDEC circuit board for surface-mount packages. θJC is specified for the exposed pad soldered to the circuit board with no airflow. Table 3. Thermal Resistance Package Type 32-Lead LFCSP θJA 47 θJC 6.8 Unit °C/W MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8193 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. To ensure proper operation, it is necessary to observe the maximum power derating as determined by the coefficients in Table 3. ESD CAUTION Rev. 0 | Page 4 of 16 AD8193 26 IP_B3 25 IN_B3 28 IN_A0 27 AVEE PIN 1 INDICATOR 24 IP_B2 IP_A2 2 VTTI 3 23 IN_B2 22 AVCC IN_A3 4 AD8193 21 IP_B1 IP_A3 5 AVCC 6 TOP VIEW (Not to Scale) 20 IN_B1 19 VTTI OP0 15 ON0 16 ON1 13 VTTO 14 AVEE 11 OP1 12 17 IN_B0 OP2 9 18 IP_B0 ON2 10 OP3 7 ON3 8 NOTES 1. THE AD8193 LFCSP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE OF THE PACKAGE, WHICH AIDS IN HEAT DISSIPATION. THE ePAD MUST BE ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE TO MEET THERMAL SPECIFICATIONS. 07003-003 IN_A2 1 30 S_SEL 29 IP_A0 32 IP_A1 31 IN_A1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3, 19 4 5 6, 22 7 8 9 10 11, 27, ePAD 12 13 14 15 16 17 18 20 21 23 24 25 26 28 29 30 31 32 1 Mnemonic IN_A2 IP_A2 VTTI IN_A3 IP_A3 AVCC OP3 ON3 OP2 ON2 AVEE OP1 ON1 VTTO OP0 ON0 IN_B0 IP_B0 IN_B1 IP_B1 IN_B2 IP_B2 IN_B3 IP_B3 IN_A0 IP_A0 S_SEL IN_A1 IP_A1 Type 1 HS I HS I Power HS I HS I Power HS O HS O HS O HS O Power HS O HS O Power HS O HS O HS I HS I HS I HS I HS I HS I HS I HS I HS I HS I Control HS I HS I Description High Speed Input Complement. High Speed Input. Input Termination Supply. Nominally connected to AVCC. High Speed Input Complement. High Speed Input. Positive Power Supply. 3.3 V nominal. High Speed Output. High Speed Output Complement. High Speed Output. High Speed Output Complement. Negative Power Supply. 0 V nominal. High Speed Output. High Speed Output Complement. Output Termination Supply. Nominally connected to AVCC. High Speed Output. High Speed Output Complement. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. Source Selector Pin. High Speed Input Complement. High Speed Input. HS = high speed, I = input, O = output. Rev. 0 | Page 5 of 16 AD8193 TYPICAL PERFORMANCE CHARACTERISTICS TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. HDMI CABLE AD8193 DIGITAL PATTERN GENERATOR SERIAL DATA ANALYZER EVALUATION BOARD REFERENCE EYE DIAGRAM AT TP1 TP1 TP2 TP3 07003-004 SMA COAX CABLE 07003-007 250mV/DIV 07003-005 250mV/DIV Figure 4. Test Circuit Diagram for Rx Eye Diagrams 07003-008 07003-006 250mV/DIV 0.125UI/DIV AT 2.25Gbps Figure 7. Rx Eye Diagram at TP3 (Cable = 2 m, 30 AWG) 250mV/DIV 0.125UI/DIV AT 2.25Gbps Figure 5. Rx Eye Diagram at TP2 (Cable = 2 m, 30 AWG) 0.125UI/DIV AT 2.25Gbps 0.125UI/DIV AT 2.25Gbps Figure 6. Rx Eye Diagram at TP2 (Cable = 6 m, 24 AWG) Figure 8. Rx Eye Diagram at TP3 (Cable = 6 m, 24 AWG) Rev. 0 | Page 6 of 16 AD8193 TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. 50 0.6 0.4 40 0.3 1080p 12-BIT JITTER (ps) 1080p 8-BIT 1080i/720p 30 1.65Gbps 20 1080i/720p 480p 10 480p 0 5 10 15 20 25 HDMI CABLE LENGTH (Meters) 0 DJ (p-p) RJ (rms) 480i 0 0.2 0.4 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 DATA RATE (Gbps) Figure 9. Jitter vs. Input Cable Length (See Figure 4 for Test Setup) Figure 12. Jitter vs. Data Rate 1.2 50 1.0 40 0.8 JITTER (ps) EYE HEIGHT (V) 0.6 07003-013 0.1 0 1080p 12-BIT 1080p 8-BIT 0.2 07003-010 DETERMINISTIC JITTER (UI) 2m TO 5m = 30AWG 6m = 24AWG 10m = 28AWG 0.5 20m = 24AWG 0.6 30 20 0.4 DJ (p-p) RJ (rms) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 DATA RATE (Gbps) 0 3.0 07003-011 0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) Figure 10. Eye Height vs. Data Rate 07003-014 10 0.2 Figure 13. Jitter vs. Supply Voltage 50 0.9 0.8 40 JITTER (ps) 0.6 0.5 0.4 30 20 0.3 10 DJ (p-p) RJ (rms) 0.1 0 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 0 0 0.5 1.0 1.5 DIFFERENTIAL INPUT SWING (V) Figure 14. Jitter vs. Differential Input Swing Figure 11. Eye Height vs. Supply Voltage Rev. 0 | Page 7 of 16 2.0 07003-015 0.2 07003-012 EYE HEIGHT (V) 0.7 AD8193 50 50 40 40 30 30 JITTER (ps) JITTER (ps) TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted. 20 20 DJ (p-p) RJ (rms) 10 2.7 2.9 3.1 3.3 3.5 3.7 INPUT COMMON-MODE VOLTAGE (V) 0 –40 07003-016 –15 Figure 15. Jitter vs. Input Common-Mode Voltage 60 85 160 58 140 RISE/FALL TIME 20% TO 80% (ps) 56 54 52 50 48 46 44 120 100 RISE TIME FALL TIME 80 60 40 20 42 –15 10 35 60 85 TEMPERATURE (°C) 0 –40 07003-017 SINGLE-ENDED INPUT RESISTANCE (Ω) 35 Figure 17. Jitter vs. Temperature 60 40 –40 10 TEMPERATURE (°C) –20 0 20 40 60 80 TEMPERATURE (°C) Figure 16. Single-Ended Input Resistance vs. Temperature Figure 18. Rise and Fall Time vs. Temperature Rev. 0 | Page 8 of 16 100 07003-019 0 2.5 DJ (p-p) RJ (rms) 07003-018 10 AD8193 THEORY OF OPERATION INTRODUCTION INPUT CHANNELS The primary function of the AD8193 is to switch the high speed signals from one of two (HDMI or DVI) single-link sources to one output. Each source group consists of four differential, high speed channels. The four high speed channels include a dataword clock and three Transition Minimized Differential Signaling (TMDS) data channels running at 10× the data-word clock frequency for data rates up to 2.25 Gbps. All four high speed channels of the AD8193 are identical; that is, the pixel clock can be run on any of the four TMDS channels. The AD8193 does not provide switching of the low speed DDC and CEC signals. Each high speed input differential pair terminates to the 3.3 V VTTI power supply through a pair of single-ended 50 Ω on-chip resistors, as shown in Figure 19. These matched onchip terminations absorb reflections on the input TMDS channels, properly terminating the inputs and improving overall system signal integrity. • • • Low input capacitance. The HDMI 1.3 specification limits the total DDC link capacitance for an HDMI sink to less than 50 pF. This 50 pF limit includes the HDMI connector, the PCB, the capacitance of the CMOS switch, and whatever capacitance is seen at the input of the HDMI receiver. Low channel on resistance (RON). Switches with high on resistance degrade the quality of the DDC signals. An appropriate form factor to switch the DDC and HPD signals as necessary. No specific cable length is suggested for use with the AD8193 because cable performance varies widely between manufacturers. For a 24 AWG reference cable, the AD8193 can operate with more than 20 m of input cable at data rates equivalent to 1080i, more than 10 meters at 1080p, and more than 6 meters at 1080p, 12-bit color. A reference design that incorporates the AD8193 and a low cost CMOS switch is described in more detail in the Evaluation Board section. In addition to the AD8193, Analog Devices, Inc., offers several HDMI switches with integrated DDC, in a variety of form factors. Rev. 0 | Page 9 of 16 VTTI 50Ω IP_xx IN_xx 50Ω Rx AVEE 07003-020 The AD8193 is a buffered TMDS switch with low added jitter; the output pins are electrically isolated from the inputs. Because the AD8193 is a TMDS-only switch, a complete HDMI switch solution requires another component to switch the low speed DDC channels. Several low cost CMOS switches can be used along with the AD8193 to make an HDMI 1.3-compliant 2:1 link switch. The requirements for such a switch are as follows: The input termination resistors all have series switches, as shown in Figure 19. The state of these switches is determined by the S_SEL signal, which also controls the input selection. The termination switches for the selected input channel are closed (terminations present), whereas the termination switches for the unselected input are open (high-Z inputs). Figure 19. High Speed Input Simplified Schematic AD8193 OUTPUT CHANNELS SWITCHING MODE Each high speed output differential pair is terminated to the 3.3 V VTTO power supply through two single-ended 50 Ω on-chip resistors, as shown in Figure 20. These matched onchip back-terminations absorb reflections on the output TMDS channels and improve the overall system signal integrity. These termination resistors are always present in the outputs and they cannot be switched out. The source selector pin, S_SEL, is used to select which of the two input groups is routed to the output. Source A is selected when S_SEL is pulled up to logic high, and Source B is selected when S_SEL is pulled down to logic low. Logic levels for this pin are set in accordance with the specifications listed in Table 5. The AD8193 can be used as a single-link TMDS buffer by setting S_SEL to one fixed logic value. VTTO S_SEL also controls the switch status of the input termination resistors. The termination resistors for the selected input are always connected, whereas the termination resistors for the unselected input are always switched out (high-Z inputs). 50Ω 50Ω OP[3:0] ON[3:0] IOUT AVEE 07003-021 Table 5. S_SEL Description Figure 20. High Speed Output Simplified Schematic S_SEL 0 Selected Input Input B 1 Input A In a typical application, the AD8193 output is connected to the input of an HDMI/DVI receiver, which provides a second set of matched terminations in accordance with the HDMI 1.3 specification. If no receiver is connected, each of the AD8193 output pins should be tied to 3.3 V through a 50 Ω on-board termination resistor. Rev. 0 | Page 10 of 16 Input Termination Status Input B terminations enabled, Input A terminations disabled Input A terminations enabled, Input B terminations disabled AD8193 APPLICATION NOTES SWITCHING HIGH SPEED SIGNALS TMDS Signals The AD8193 is a quad 2:1 TMDS switch that is used to switch the high speed signals of two input HDMI links to a single HDMI output. The audiovisual (AV) data carried on these high speed channels is encoded by a technique called Transition Minimized Differential Signaling (TMDS) and, in the case of HDMI, is also encrypted according to the high bandwidth digital content protection (HDCP) standard. SWITCHING LOW SPEED SIGNALS Because the AD8193 is a TMDS-only switch, a complete HDMI switch solution requires another component to switch the low speed DDC channels. The HDMI 1.3 specification places a number of restrictions on the low speed signal path that limit the selection of a suitable low cost DDC switch. The first requirement is that the switch must be bidirectional to convey the I2C® protocol signals that pass through it. A CMOS device is the simplest switch with this capability. The second HDMI requirement for the DDC signals is that the total DDC signal path capacitance be less than 50 pF. The total capacitance comprises the HDMI connector, the PC board traces, the DDC switch, and the input capacitance of the HDMI receiver. As a practical design consideration, a suitable DDC switch has a total channel capacitance of less than 10 pF. Finally, the channel on resistance (RON) of the DDC switch must not be too high, otherwise the voltage drop across it violates the maximum VOL of the I2C signals. Any switch with an on resistance of approximately 100 Ω is sufficient in a typical application, assuming that the end application includes an I2C-compliant receiver device. Switches with lower channel on resistance have improved VOL performance. For the AD8193 evaluation board, the MC74LVX4053 was chosen to switch the low speed signals. This part has a maximum RON of 108 Ω and a maximum parasitic capacitance of 10 pF. Refer to the Evaluation Board section for details on how to use the MC74LVX4053 with the AD8193 in an application. PCB LAYOUT GUIDELINES The AD8193 is used to switch HDMI/DVI video signals, which are differential, unidirectional, and high speed (up to 2.25 Gbps). The channels that carry the video data must be controlled impedance, terminated at the receiver, and capable of operating up to at least 2.25 Gbps. It is especially important to note that the differential traces that carry the TMDS signals should be designed with a controlled differential impedance of 100 Ω. The AD8193 provides single-ended 50 Ω terminations on chip for both its inputs and outputs. Transmitter termination is not fully specified by the HDMI standard, but the inclusion of the 50 Ω output terminations improves the overall system signal integrity. In the HDMI/DVI standard, four differential pairs carry the TMDS signals. For DVI, three of these pairs are dedicated to carrying RGB video and sync data. For HDMI, audio data is also interleaved with the video data; the DVI standard does not incorporate audio information. The fourth high speed differential pair is used for the AV data-word clock and runs at one-tenth the speed of the TMDS data channels. The four high speed channels of the AD8193 are identical. No concession was made to lower the bandwidth of the fourth channel for the pixel clock, so any channel can be used for any TMDS signal. The user chooses which signal is routed over which channel. Additionally, the TMDS channels are symmetrical; therefore, the p and n of a given differential pair are interchangeable, provided the inversion is consistent across all inputs and outputs of the AD8193. However, the routing between inputs and outputs through the AD8193 is fixed. For example, Output Channel 0 always switches between Input A0 and Input B0, and so forth. The AD8193 buffers the TMDS signals, and the input traces can be considered electrically independent of the output traces. In most applications, the quality of the signal on the input TMDS traces is more sensitive to the PCB layout. Regardless of the data being carried on a specific TMDS channel, or whether the TMDS line is at the input or the output of the AD8193, all four high speed signals should be routed on a PCB in accordance with the same RF layout guidelines. Layout for the TMDS Signals The TMDS differential pairs can be either microstrip traces, routed on the outer layer of a board, or stripline traces, routed on an internal layer of the board. If microstrip traces are used, there should be a continuous reference plane on the PCB layer directly below the traces. If stripline traces are used, they must be sandwiched between two continuous reference planes in the PCB stackup. Additionally, the p and n of each differential pair must have a controlled differential impedance of 100 Ω. The characteristic impedance of a differential pair is a function of several variables, including the trace width, the distance separating the two traces, the spacing between the traces and the reference plane, and the dielectric constant of the PC board binder material. Interlayer vias introduce impedance discontinuities that can cause reflections and jitter on the signal path; therefore, it is preferable to route the TMDS lines exclusively on one layer of the board, particularly for the input traces. Additionally, to prevent unwanted signal coupling and interference, route the TMDS signals away from other signals and noise sources on the PCB. Rev. 0 | Page 11 of 16 AD8193 Any group of four TMDS channels (Input A, Input B, or the output) should have closely matched trace lengths to minimize interpair skew. Severe interpair skew can cause the data on the four different channels of a group to arrive out of alignment with one another. A good practice is to match the trace lengths for a given group of four channels to within 0.05 inches on FR4 material. The length of the TMDS traces should be minimized to reduce overall signal degradation. Commonly used PC board material such as FR4 is lossy at high frequencies; therefore, long traces on the circuit board increase signal attenuation, resulting in decreased signal swing and increased jitter through intersymbol interference (ISI). Ground Current Return In some applications, it may be necessary to invert the output pin order of the AD8193. This requires routing the TMDS traces on multiple layers of the PCB. When routing differential pairs on multiple layers, it is also necessary to reroute the corresponding reference plane to provide one continuous ground current return path for the differential signals. Standard plated through-hole vias are acceptable for both the TMDS traces and the reference plane. An example of this is illustrated in Figure 21. THROUGH-HOLE VIAS SILKSCREEN LAYER 1: SIGNAL (MICROSTRIP) PCB DIELECTRIC LAYER 2: GND (REFERENCE PLANE) PCB DIELECTRIC LAYER 3: PWR (REFERENCE PLANE) PCB DIELECTRIC LAYER 4: SIGNAL (MICROSTRIP) SILKSCREEN Controlling the Characteristic Impedance of a TMDS Differential Pair KEEP REFERENCE PLANE ADJACENT TO SIGNAL ON ALL LAYERS TO PROVIDE CONTINUOUS GROUND CURRENT RETURN PATH. The characteristic impedance of a differential pair depends on a number of variables, including the trace width, the distance between the two traces, the height of the dielectric material between the trace and the reference plane below it, and the dielectric constant of the PCB binder material. To a lesser extent, the characteristic impedance also depends upon the trace thickness and the presence of solder mask. There are many combinations that can produce the correct characteristic impedance. It is generally required to work with the PC board fabricator to obtain a set of parameters to produce the desired results. To guarantee a differential pair with a differential impedance of 100 Ω over the entire length of the trace, change the width of the traces in a differential pair based on how closely one trace is coupled to the other. When the two traces of a differential pair are close and strongly coupled, they should have a width that produces a 100 Ω differential impedance. When the traces split apart to go into a connector, for example, and are no longer so strongly coupled, the width of the traces should be increased to yield a differential impedance of 100 Ω in the new configuration. 07003-022 Both traces of a given differential pair must be equal in length to minimize intrapair skew. Maintaining the physical symmetry of a differential pair is integral to ensuring its signal integrity; excessive intrapair skew can introduce jitter through duty cycle distortion (DCD). The p and n of a given differential pair should always be routed together to establish the required 100 Ω differential impedance. Enough space should be left between the differential pairs of a given group so that the n of one pair does not couple to the p of another pair. For example, one technique is to make the interpair distance 4 to 10 times wider than the intrapair spacing. Figure 21. Example Routing of Reference Plane TMDS Terminations The AD8193 provides internal 50 Ω single-ended terminations for all of its high speed inputs and outputs. The termination resistors back-terminate the output TMDS transmission lines. These back-terminations act to absorb reflections from impedance discontinuities on the output traces, improving the signal integrity of the output traces and adding flexibility to how the output traces can be routed. For example, interlayer vias can be used to route the AD8193 TMDS outputs on multiple layers of the PCB without severely degrading the quality of the output signal. In a typical application, the AD8193 output is connected to an HDMI/DVI receiver or to another device with a 50 Ω single-ended input termination. It is recommended that the outputs be terminated with external 50 Ω on-board resistors when the AD8193 is not connected to another device. Rev. 0 | Page 12 of 16 AD8193 Auxiliary Control Signals There are four single-ended control signals associated with each source or sink in an HDMI/DVI application. These are hot plug detect (HPD), consumer electronics control (CEC), and two display data channel (DDC) lines. The two signals on the DDC bus are SDA and SCL (serial data and serial clock, respectively). The AD8193, which is a low cost part, does not have any additional capability to switch these signals; other means are required to switch these signals if required. In general, it is sufficient to route each auxiliary signal as a single-ended trace. These signals are not sensitive to impedance discontinuities, do not require a reference plane, and can be routed on multiple layers of the PCB. However, it is best to follow strict layout practices whenever possible to prevent the PCB design from affecting the overall application. The specific routing of the HPD, CEC, and DDC lines depends upon the application in which the AD8193 is being used. For example, the maximum speed of signals present on the auxiliary lines is 100 kHz I2C data on the DDC lines; therefore, any layout that enables 100 kHz I2C to be passed over the DDC bus should suffice. The HDMI 1.3 specification, however, places a strict 50 pF limit on the amount of capacitance that can be measured on either SDA or SCL at the HDMI input connector. This 50 pF limit includes the HDMI connector, the PCB, the capacitance of the CMOS switch, and whatever capacitance is seen at the input of the HDMI receiver. There is a similar limit of 100 pF of input capacitance for the CEC line. The parasitic capacitance of traces on a PCB increases with trace length. To help ensure that a design satisfies the HDMI specification, the length of the CEC and DDC lines on the PCB should be made as short as possible. Additionally, if there is a reference plane in the layer adjacent to the auxiliary traces in the PCB stackup, relieving or clearing out this reference plane immediately under the auxiliary traces significantly decreases the amount of parasitic trace capacitance. An example of the board stackup is shown in Figure 22. W Power Supplies The AD8193 has three separate power supplies referenced to a single ground. The supply/ground pairs are • • • AVCC/AVEE VTTI/AVEE VTTO/AVEE The AVCC/AVEE (3.3 V) supply powers the core of the AD8193. The VTTI/AVEE supply (3.3 V) powers the input termination (see Figure 19). Similarly, the VTTO/AVEE supply (3.3 V) powers the output termination (see Figure 20). In a typical application, all pins labeled AVEE should be connected directly to ground. All pins labeled AVCC, VTTI, or VTTO should be connected to 3.3 V. The supplies can also be powered individually, but care must be taken to ensure that each stage of the AD8193 is powered correctly. Power Supply Bypassing The AD8193 requires minimal supply bypassing. When powering the supplies individually, place a 0.01 μF capacitor between each 3.3 V supply pin (AVCC, VTTI, and VTTO) and ground to filter out supply noise. Generally, bypass capacitors should be placed near the power pins and should connect directly to the relevant supplies (without long intervening traces). For example, to minimize the parasitic inductance of the power supply decoupling capacitors, minimize the trace length between capacitor landing pads and the vias as shown in Figure 23. RECOMMENDED EXTRA ADDED INDUCTANCE 3W NOT RECOMMENDED SILKSCREEN 07003-024 3W HPD is a dc signal presented by a sink to a source to indicate that the source EDID is available for reading. The placement of this signal is not critical, but it should be routed as directly as possible. Figure 23. Recommended Pad Outline for Bypass Capacitors LAYER 1: SIGNAL (MICROSTRIP) In applications where the AD8193 is powered by a single 3.3 V supply, it is recommended to use two reference supply planes and bypass the 3.3 V reference plane to the ground reference plane with one 220 pF, one 1000 pF, two 0.01 μF, and one 4.7 μF capacitors. The capacitors should via down directly to the supply planes and be placed within a few centimeters of the AD8193. PCB DIELECTRIC LAYER 2: GND (REFERENCE PLANE) PCB DIELECTRIC LAYER 3: PWR (REFERENCE PLANE) PCB DIELECTRIC LAYER 4: SIGNAL (MICROSTRIP) REFERENCE LAYER RELIEVED UNDERNEATH MICROSTRIP 07003-023 SILKSCREEN Figure 22. Example Board Stackup Rev. 0 | Page 13 of 16 AD8193 Evaluation Board However, this arrangement requires crossing over the TMDS signals on the output side (see Figure 24). The AD8193 evaluation board illustrates one way to implement a 2:1 HDMI link switch with an AD8193 and a CMOS switch. The AD8193 evaluation board deviates from a typical application in that it uses an HDMI connector for the output as well as for the inputs. This setup makes it easy to connect equipment to the AD8193 evaluation board with standard HDMI cables. In a typical application, the output of the AD8193 is routed directly into an HDMI receiver. Because a receiver is generally designed to interface directly to an HDMI input connector, it is not necessary to cross over the TMDS signals in a typical application (see Figure 25). 19 CROSSOVER REQUIRED HDMI CONNECTOR 1 1 HDMI CONNECTOR AD8193 19 19 07003-025 HDMI CONNECTOR 1 Figure 24. Block Diagram of AD8193 Evaluation Board Showing Output Crossover 19 HDMI CONNECTOR HDMI RECEIVER 07003-026 AD8193 1 Figure 25. HDMI Signals to HDMI Receiver, No Crossover Required Rev. 0 | Page 14 of 16 AD8193 The low speed switching is performed by an MC74LVX4053. This part contributes a maximum on resistance of 108 Ω and a maximum capacitive load of 10 pF. The same select signal (S_SEL) controls both the AD8193 and the MC74LVX4053. 07003-027 Figure 26 shows the layout of the TMDS traces. These are 100 Ω differential, controlled-impedance traces. Serpentine traces are used for some of the paths to match the lengths within a group of four. The gray traces are routed on the top layer and the black traces on the bottom layer. Figure 26. Layout of TMDS Traces Rev. 0 | Page 15 of 16 AD8193 OUTLINE DIMENSIONS 5.00 BSC SQ PIN 1 INDICATOR TOP VIEW 0.60 MAX 0.60 MAX 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 12° MAX SEATING PLANE 25 24 32 1 2.85 2.70 SQ 2.55 *EXPOSED PAD (BOT TOM VIEW) 17 16 PIN 1 INDICATOR 9 8 0.20 MIN 3.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.25 0.18 0.20 REF COPLANARITY 0.08 102407-A COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 *THE AD8193 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL HDMI/DVI TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO AVEE. IT IS RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG. ATTACHING THE SLUG TO AN AVEE PLANE REDUCES THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. Figure 27. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-8) Dimensions shown in millimeters ORDERING GUIDE Model AD8193ACPZ 1 AD8193ACPZ-R71 AD8193-EVALZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Reel Evaluation Board Z = RoHS Compliant Part. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07003-0-11/07(0) Rev. 0 | Page 16 of 16 Package Option CP-32-8 CP-32-8 Ordering Quantity 1,500