FAIRCHILD DM74LS393M

Revised March 2000
DM74LS393
Dual 4-Bit Binary Counter
General Description
Features
Each of these monolithic circuits contains eight masterslave flip-flops and additional gating to implement two individual four-bit counters in a single package. The
DM74LS393 comprises two independent four-bit binary
counters each having a clear and a clock input. N-bit binary
counters can be implemented with each package providing
the capability of divide-by-256. The DM74LS393 has parallel outputs from each counter stage so that any submultiple
of the input count frequency is available for system-timing
signals.
■ Dual version of the popular DM74LS93
■ DM74LS393 dual 4-bit binary counter with individual
clocks
■ Direct clear for each 4-bit counter
■ Dual 4-bit versions can significantly improve system
densities by reducing counter package count by 50%
■ Typical maximum count frequency 35 MHz
■ Buffered outputs reduce possibility of collector commutation
Ordering Code:
Order Number
Package Number
Package Description
DM74LS393M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS373N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Counter Sequence (Each Counter)
Count
Outputs
QD
QC
QB
0
L
L
L
QA
L
1
L
L
L
H
2
L
L
H
L
3
L
L
H
H
4
L
H
L
L
5
L
H
L
H
6
L
H
H
L
7
L
H
H
H
8
H
L
L
L
9
H
L
L
H
10
H
L
H
L
11
H
L
H
H
12
H
H
L
L
13
H
H
L
H
14
H
H
H
L
15
H
H
H
H
H = HIGH Logic Level
L = LOW Logic Level
© 2000 Fairchild Semiconductor Corporation
DS006434
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DM74LS393 Dual 4-Bit Binary Counter
August 1986
DM74LS393
Logic Diagram
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2
Supply Voltage
7V
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Input Voltage
Clear
7V
A
5.5V
0°C to +70°C
Operating Free Air Temperature Range
−65°C to +150°C
Storage Temperature Range
Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
4.75
5
5.25
Units
VCC
Supply Voltage
VIH
HIGH Level Input Voltage
V
VIL
LOW Level Input Voltage
0.8
V
IOH
HIGH Level Output Current
−0.4
mA
IOL
LOW Level Output Current
fCLK
Clock Frequency (Note 2)
fCLK
Clock Frequency (Note 3)
tW
Pulse Width (Note 5)
2
8
mA
0
25
MHz
0
20
MHz
A
20
Clear HIGH
20
tREL
Clear Release Time (Note 4)(Note 5)
TA
Free Air Operating Temperature
V
ns
25↓
ns
0
°C
70
Note 2: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.
Note 3: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.
Note 4: The symbol (↓) indicates that the falling edge of the clear pulse is used for reference.
Note 5: TA = 25°C, and VCC = 5V.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
VCC = Min, II = −18 mA
VOH
HIGH Level
VCC = Min, IOH = Max
Output Voltage
VIL = Max, VIH = Min
VOL
LOW Level
VCC = Min, IOL = Max
Output Voltage
VIL = Max, VIH = Min
Min
2.7
IOL = 4 mA, VCC = Min
II
IIH
Max
Units
−1.5
V
3.4
V
0.35
0.5
0.25
0.4
Input Current @ Max
VCC = Max, VI = 7V
Clear
0.1
Input Voltage
VCC = Max, VI = 5.5V
A
0.2
HIGH Level
VCC = Max, VI = 2.7V
Clear
20
A
40
Input Current
IIL
Typ
(Note 6)
LOW Level
VCC = Max, VI = 0.4V
Input Current
IOS
Short Circuit Output Current
VCC = Max (Note 7)
ICC
Supply Current
VCC = Max (Note 8)
Clear
−0.4
A
−1.6
−20
15
V
mA
µA
mA
−100
mA
26
mA
Note 6: All typicals are at VCC = 5V, TA = 25°C.
Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 8: ICC is measured with all outputs open, both CLEAR inputs grounded following momentary connection to 4.5V, and all other inputs grounded.
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DM74LS393
Absolute Maximum Ratings(Note 1)
DM74LS393
Switching Characteristics
at VCC = 5V and TA = 25°C
RL = 2 kΩ
Symbol
Parameter
fMAX
Maximum Clock Frequency
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
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CL = 15 pF
From (Input)
To (Output)
Min
A to QA
25
Max
CL = 50 pF
Min
Units
Max
20
MHz
A to QA
20
24
ns
A to QA
20
30
ns
A to QD
60
87
ns
A to QD
60
87
ns
Clear to Any Q
39
45
ns
4
DM74LS393
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
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DM74LS393 Dual 4-Bit Binary Counter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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