19-1844; Rev 1; 4/01 +3V/+5V, Low-Power, 8-Bit Octal DACs with Rail-to-Rail Output Buffers Features ♦ +2.7V to +5.5V Single-Supply Operation ♦ Low Supply Current: 1.3mA ♦ Low-Power Shutdown Mode 0.54mA (MAX5259) 0.80mA (MAX5258) ♦ ±1LSB DNL (max) ♦ ±1LSB INL (max) ♦ Ground to VDD Reference Input Range ♦ Output Buffer Amplifiers Swing Rail-to-Rail ♦ 10MHz Serial Interface, SPI, QSPI (CPOL = CPHA = 0 or CPOL = CPHA = 1), and MICROWIRECompatible ♦ Double-Buffered Registers for Synchronous Updating ♦ Serial Data Output for Daisy-Chaining ♦ Ultra-Small 16-Pin QSOP Package Ordering Information ________________________Applications Digital Gain and Offset Adjustment Programmable Attenuators PART Programmable Current Sources Portable Instruments SUPPLY TEMP. RANGE PIN-PACKAGE VOLTAGE (V) MAX5258EEE -40oC to +85oC 16 QSOP +5.0 MAX5259EEE -40oC to +85oC 16 QSOP +3.0 Pin Configuration TOP VIEW OUTB 1 16 OUTC OUTA 2 15 OUTD GND 3 VDD 4 REF 5 Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. 14 DOUT MAX5258 MAX5259 13 DIN 12 SCLK LDAC 6 11 CS OUTE 7 10 OUTH OUTF 8 9 OUTG QSOP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5258/MAX5259 General Description The MAX5258/MAX5259 are +3V/+5V single-supply, digital serial-input, voltage-output, 8-bit octal digital-toanalog converters (DACs). Internal precision buffers swing Rail-to-Rail ® , and the reference input range extends from ground to the positive supply. The +5V (MAX5258) and the +3V (MAX5259) feature a 10µA (max) shutdown mode. The serial interface is double-buffered. A 16-bit input shift register is followed by eight 8-bit input registers and eight 8-bit DAC registers. The 16-bit serial word consists of two “don’t care” bits, three address bits, three control bits, and eight data bits. The input and DAC registers can both be updated independently or simultaneously with a single software command. The asynchronous control input (LDAC) provides simultaneous updating of all eight DAC registers. The interface is compatible with SPI™, QSPI™ (CPOL = CPHA = 0 or CPOL = CPHA = 1), and MICROWIRE™. A buffered digital data output allows daisy-chaining of serial devices. The MAX5258/MAX5259 are available in a 16-pin QSOP package. MAX5258/MAX5259 +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V DIN, DOUT, CS, SCLK, LDAC to GND.....................-0.3V to +6V REF to GND ................................................-0.3V to (VDD + 0.3V) OUT_ to GND ...........................................................-0.3V to VDD Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70°C) 16-Pin Plastic QSOP (derate 8.3mW/°C about +70°C)...667mW Operating Temperature Range ..........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (MAX5258) (VDD = +4.5V to +5.5V, VREF = +4.096V, GND = 0, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V and TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±0.1 ±1 LSB STATIC ACCURACY Resolution 8 Bits Integral Nonlinearity (Note 1) INL Differential Nonlinearity (Note 1) DNL Guaranteed monotonic (all codes) ±0.05 ±1 LSB Zero-Code Error ZCE Code = 0A hex ±2.5 ±20 mV Zero-Code Error Supply Rejection Code = 0A hex 0.02 1 LSB Zero-Code Temperature Coefficient Code = 0A hex ±10 µV/oC Full-Scale Error Code = FF hex ±1 ±30 mV Full-Scale Error Supply Rejection Code = FF hex 0.25 1 LSB Full-Scale Temperature Coefficient Code = FF hex ±10 µV/oC REFERENCE INPUTS Input Voltage Range 0 Input Resistance 161 Input Capacitance 230 VDD V 300 kΩ 20 pF DAC OUTPUTS Output Voltage Swing RL = 10kΩ to GND 0 VDD 0.3 V Output Voltage Range RL = 10kΩ to GND 0 VREF V DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL 2 0.7 ✕ VDD _______________________________________________________________________________________ V 0.3 ✕ VDD V +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers (VDD = +4.5V to +5.5V, VREF = +4.096V, GND = 0, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V and TA = +25°C.) PARAMETER SYMBOL CONDITIONS Input Current IIN VIN = 0 to VDD Input Capacitance CIN (Note 3) Output High Voltage VOH ISOURCE = 0.2mA Output Low Voltage VOL ISINK = 1.6mA MIN TYP MAX UNITS ±1.0 µA 10 pF DIGITAL OUTPUTS VDD 0.5 V 0.4 V DYNAMIC PERFORMANCE Voltage-Output Slew Rate Code = FF hex Output Settling Time To 1/2 LSB, from code 0A to code FF hex (Note 2) 0.55 V/µs 10 µs Digital Feedthrough Code = 00 hex 0.15 nV-s Digital-to-Analog Glitch Impulse Code = 80 to code = 7F hex 30 nV-s VREF = 4Vp-p at 1kHz centered at 2.5V code = FF hex 68 VREF = 4Vp-p at 10kHz centered at 2.5V code = FF hex 55 VREF = 0.1Vp-p centered at VDD/2, -3dB bandwidth 700 kHz 16 µV Signal-to-Noise Plus Distortion Ratio SINAD Multiplying Bandwidth dB Wideband Amplifier Noise POWER REQUIREMENTS Power-Supply Voltage VDD 5.5 V Supply Current IDD 1.4 2.6 mA ISHDN 0.45 10 µA Shutdown Supply Current 4.5 _______________________________________________________________________________________ 3 MAX5258/MAX5259 ELECTRICAL CHARACTERISTICS (MAX5258) (continued) MAX5258/MAX5259 +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers ELECTRICAL CHARACTERISTICS (MAX5259) (VDD = +2.7V to +3.3V, VREF = +2.5V, GND = 0, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V, and TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±0.1 ±1 LSB STATIC ACCURACY Resolution 8 Bits Integral Non Linearity (Note 1) INL Differential Non Linearity (Note 1) DNL Guaranteed monotonic (all codes) ±0.1 ±1 LSB Zero-Code Error ZCE Code = 0A hex ±2.5 ±20 mV Zero-Code Error Supply Rejection Code = 0A hex. 0.15 1 LSB Zero-Code Temperature Coefficient Code = 0A hex ±10 Full-Scale Error Code = FF hex ±0.7 ±30 mV Full-Scale Error Supply Rejection Code = FF hex 0.2 1 LSB Full-Scale Temperature Coefficient Code = FF hex ±10 µV/oC µV/oC REFERENCE INPUTS Input Voltage Range 0 Input Resistance 161 Input Capacitance 218 VDD V 300 kΩ 20 pF DAC OUTPUTS Output Voltage Swing RL = 10kΩto GND 0 VDD – 0.3 V Output Voltage Range RL = 10kΩ to GND 0 VREF V DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL 0.7 x VDD Input Current IIN VIN = 0 to VDD Input Capacitance CIN (Note 3) Output High Voltage VOH ISOURCE = 0.2mA Output Low Voltage VOL ISINK = 1.6mA V 0.3 x VDD V ±1.0 µA 10 pF DIGITAL OUTPUTS VDD – 0.5 V 0.4 V DYNAMIC PERFORMANCE Voltage-Output Slew Rate Code = FF hex Output Settling Time To 1/2 LSB, from code 0A to code FF hex (Note 2) 4 0.55 V/µs 7 µs _______________________________________________________________________________________ +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers (VDD = +2.7V to +3.3V, VREF = +2.5V, GND = 0, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V, and TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Digital Feedthrough Code = 00 hex 0.1 nV-s Digital-to-Analog Glitch Impulse Code = 80 to code = 7F hex 20 nV-S VREF = 2.5Vp-p at 1kHz centered at 1.5V code = FF hex 65 VREF = 2.5Vp-pat 10kHz centered at 1.5V code = FF hex 54 VREF = 0.1Vp-p centered at VDD/2, -3dB bandwidth 700 kHz 60 µV Signal-to-Noise Plus Distortion Ratio dB SINAD Multiplying Bandwidth Wideband Amplifier Noise POWER REQUIREMENTS Power-Supply Voltage Supply Current Shutdown Supply Current VDD 2.7 3.6 V IDD 1.3 2.6 mA ISHDN 0.24 10 µA TIMING CHARACTERISTICS (MAX5258) (VREF = +4.096V, GND = 0, CDOUT = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V and TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5 µs 20 ns VDD Rise-to-CS Fall-Setup Time tVDCS LDAC Pulse Width Low tLDAC 40 CS Rise-to-LDAC Fall-Setup Time (Note 4) tCLL 40 CS Pulse Width High tCSW 90 SCLK Clock Frequency (Note 5) fCLK SCLK Pulse Width High tCH 40 ns ns SCLK Pulse Width Low ns ns 10 MHz tCL 40 CS Fall-to-SCLK Rise-Setup Time tCSS 40 ns SCLK Rise-to-CS Rise-Hold Time tCSH 0 ns DIN to SCLK Rise-to-Setup Time tDS 40 ns DIN to SCLK Rise-to-Hold Time tDH 0 ns SCLK Rise-to-DOUT Valid Propagation Delay (Note 6) tDO1 200 ns SCLK Fall-to-DOUT Valid Propagation Delay (Note 7) tDO2 210 ns CS Rise-to-SCLK Rise-Setup Time tCS1 40 ns _______________________________________________________________________________________ 5 MAX5258/MAX5259 ELECTRICAL CHARACTERISTICS (MAX5259) (continued) MAX5258/MAX5259 +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers TIMING CHARACTERISTICS (MAX5259) (VREF = +2.5V, GND = 0, CDOUT = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5 µs 20 ns VDD Rise-to-CS Fall-Setup Time tVDCS LDAC Pulse Width Low tLDAC 40 CS Rise-to-LDAC Fall-Setup Time (Note 4) tCLL 40 CS Pulse Width High tCSW 90 SCLK Clock Frequency (Note 5) fCLK SCLK Pulse Width High tCH 40 ns SCLK Pulse Width Low tCL 40 ns CS Fall-to-SCLK Rise-Setup Time tCSS 40 ns SCLK Rise-to-CS Rise-Hold Time tCSH 0 ns DIN to SCLK Rise-to-Setup Time tDS 40 ns DIN to SCLK Rise-to-Hold Time tDH 0 ns SCLK Rise-to-DOUT Valid Propagation Delay (Note 6) tDO1 200 ns SCLK Fall-to-DOUT Valid Propagation Delay (Note 7) tDO2 210 ns CS Rise-to-SCLK Rise-Setup Time tCS1 ns ns 10 40 MHz ns Note 1: INL and DNL are measured with RL referenced to ground. Nonlinearity is measured from the first code that is greater than or equal to the maximum offset specification to code FF hex (full scale). (See DAC Linearity and Voltage Offset section.) Note 2: Output settling time is measured from the 50% point of the rising edge of CS to 1/2LSB of the final value of VOUT. Note 3: Guaranteed by design, not production tested. Note 4: If LDAC is activated prior to the rising edge of CS, it must remain low for tLDAC or longer after CS goes high. Note 5: When DOUT is not used. If DOUT is used, fCLK (max) is 4MHz due to SCLK to DOUT propagation delay. Note 6: Serial data is clocked-out at SCLK’s rising edge (measured from 50% of the clock edge to 20% or 80% of VDD). Note 7: Serial data is clocked-out at SCLK’s falling edge (measured from 50% of the clock edge to 20% or 80% of VDD). 6 _______________________________________________________________________________________ +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers 500 400 300 200 100 0 1.25 1.00 0.75 0.50 0.25 0 2 3 4 5 1 DAC OUTPUT SINK CURRENT (mA) 2 3 4 5 6 7 1.6 MAX5258/9 toc04 4.5 4.0 3.5 3.0 ALL DAC CODES = FF HEX 1.4 SUPPLY CURRENT (mA) 5.0 2.0 5 6 7 0.8 8 2 3 4 5 6 7 1.6 ALL DAC CODES = OO HEX VDD = +3.0V VREF = +2.5V ALL DAC CODES = FF HEX 1.4 1.2 1.0 ALL DAC CODES = OO HEX 0.8 VDD = +5.0V VREF = +4.5V 0.6 0.4 -40 -15 10 35 60 85 -40 -15 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. REFERENCE VOLTAGE (VDD = +3V) 0.35 0.30 0.25 0.20 0.5 0.4 0.3 0.2 VDD = +5V VREF = +4.5V 10 35 TEMPERATURE (°C) 60 85 MAX5258/9 toc09 85 1.2 1.0 0.8 ALL DAC CODES = OO HEX 0.4 0.1 0.10 -15 ALL DAC CODES = FF HEX 1.4 0.6 VDD = +3V VREF = +2.5V 0.15 1.6 SUPPLY CURRENT (mA) 0.6 SUPPLY CURRENT (µA) 0.40 1.8 MAX5258/9 toc08 0.7 MAX5258/9 toc07 0.45 8 SUPPLY CURRENT vs. TEMPERATURE 1.8 DAC OUTPUT SOURCE CURRENT (mA) 0.50 -40 1 DAC OUTPUT SOURCE CURRENT (mA) 0.4 4 1.5 0 1.0 VDD = +5V 3 2.0 8 1.2 0.6 2.5 2 2.5 SUPPLY CURRENT vs. TEMPERATURE 5.5 1 3.0 DAC OUTPUT SINK CURRENT (mA) DAC FULL-SCALE OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT 0 VDD = +3V 1.0 0 SUPPLY CURRENT (mA) 1 MAX5258/9 toc05 0 DAC FULL-SCALE OUTPUT VOLTAGE (V) 3.5 MAX5258/9 toc06 600 VDD = +5V DAC FULL-SCALE OUTPUT VOLTAGE (mV) 700 1.50 MAX5258/9 toc02 VDD = +3V DAC ZERO-CODE OUTPUT VOLTAGE (mV) MAX5258/9 toc01 DAC ZERO-CODE OUTPUT VOLTAGE (mV) 800 SUPPLY CURRENT (µA) DAC FULL-SCALE OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT DAC ZERO-CODE OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT MAX5258/9 toc03 DAC ZERO-CODE OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT 0.2 -40 -15 10 35 TEMPERATURE (°C) 60 85 0 0.5 1.0 1.5 2.0 2.5 3.0 REFERENCE VOLTAGE (V) _______________________________________________________________________________________ 7 MAX5258/MAX5259 Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) THD + NOISE AT DAC OUTPUT vs. REFERENCE AMPLITUDE -10 -20 THD + NOISE (dB) ALL DAC CODES = FF HEX 1.2 1.0 0.8 ALL DAC CODES = OO HEX 0.6 -30 -40 VREF = 20kHz -50 VREF = 1kHz -70 0.2 -80 0 1 2 3 4 5 -40 -45 VREF = 0.5Vp-p -50 0 0.5 1.0 1.5 2.0 -60 VREF = 1Vp-p -65 VREF = 2Vp-p -70 10 100 1k 100k REFERENCE INPUT FREQUENCY RESPONSE REFERENCE FEEDTHROUGH vs. FREQUENCY WORST-CASE 1LSB DIGITAL STEP CHANGE (POSITIVE) -20 -25 VREF = 0.1Vp-p SINE-WAVE CENTERED AT 2.5V DAC CODE = FF HEX VDD = +3V MAX5258/9 toc14 VREF = 3Vp-p SINE-WAVE DAC CODE = OO HEX VDD = +3V -55 RELATIVE OUTPUT (dB) -15 MAX5258/9 toc15 -50 MAX5258/9 toc13 -10 -60 3V CS 0 -65 -70 -75 50mV/div OUTA -80 -85 -45 -90 1 10 100 1k 10k 100k 1M 10M 100 1k FREQUENCY (Hz) 10k 100k 1M 10M FREQUENCY (Hz) VDD = +3V VREF = +2.5V WORST-CASE 1LSB DIGITAL STEP CHANGE (NEGATIVE) 1µs/div DAC CODE = 7F TO 80 HEX NO-LOAD WORST-CASE 1LSB DIGITAL STEP CHANGE (POSITIVE) MAX5258/9 toc16 MAX5258/9 toc17 3V CS 0 3V CS 0 50mV/div OUTA 50mV/div OUTA VDD = +3V VREF = +2.5V 8 10k FREQUENCY (Hz) -5 -40 -35 REFERENCE AMPLITUDE (Vp-p) 0 -35 -30 REFERENCE VOLTAGE (V) 5 -30 VREF = SINE-WAVE VDD = +3V CENTERED AT +1.5V DAC CODE = FF HEX 500kHz LOWPASS FILTER -25 -55 -60 0.4 -20 MAX5258/9 toc12 1.4 VREF = SINE-WAVE VDD = +3V CENTERED AT +1.5V DAC CODE = FF HEX 80kHz LOWPASS FILTER THD + NOISE (dB) 1.6 SUPPLY CURRENT (mA) 0 MAX5258/9 toc10 1.8 THD + NOISE AT DAC OUTPUT vs. REFERENCE FREQUENCY MAX5258/9 toc11 SUPPLY CURRENT vs. REFERENCE VOLTAGE (VDD = +5V) RELATIVE OUTPUT (dB) MAX5258/MAX5259 +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers 1µs/div DAC CODE = 80 TO 7F HEX NO-LOAD VDD = +5V VREF = +4.5V 1µs/div DAC CODE = 7F TO 80 HEX NO-LOAD _______________________________________________________________________________________ +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers WORST-CASE 1LSB DIGITAL STEP CHANGE (NEGATIVE) CLOCK FEEDTHROUGH MAX5258/9 toc19 MAX5258/9 toc18 3V 3V SCLK CS 0 0 OUTA 50mV/div VDD = +5V VREF = +4.5V 1mV/div OUTA 1µs/div DAC CODE = 00 HEX VDD = +3V VREF = +2.5V NO-LOAD SCLK = 333 kHz 1µs/div DAC CODE = 80 TO 7F HEX NO-LOAD POSITIVE SETTLING TIME POSITIVE SETTLING TIME MAX5258/9 toc21 MAX5258/9 toc20 3V 3V CS CS 0 0 2.0V/div 1.0V/div OUTA OUTA VDD = +3V VREF = +2.5V 2µs/div DAC CODE = 00 TO FF HEX NO-LOAD VDD = +5V VREF = +4.5V 4µs/div DAC CODE = 00 TO FF HEX NO-LOAD NEGATIVE SETTLING TIME NEGATIVE SETTLING TIME MAX5258/9 toc23 MAX5258/9 toc22 3V 3V CS CS 0 0 OUTA 1.0V/div VDD = +3V VREF = +2.5V 4µs/div DAC CODE = FF TO 00 HEX NO-LOAD OUTA 2.0V/div VDD = +5V VREF = +4.5V 4µs/div DAC CODE = FF TO 00 HEX NO-LOAD _______________________________________________________________________________________ 9 MAX5258/MAX5259 Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259 Pin Description PIN 1 NAME OUTB FUNCTION 2 OUTA DAC A Voltage Output 3 GND Ground 4 VDD Power Supply 5 REF Reference Voltage Input 6 LDAC 7 OUTE DAC E Voltage Output 8 OUTF DAC F Voltage Output DAC B Voltage Output Load DAC Input. Driving this asynchronous input low transfers the contents of each input register to its respective DAC registers. 9 OUTG DAC G Voltage Output 10 OUTH DAC H Voltage Output 11 CS 12 SCLK 13 DIN 14 DOUT Serial Data Output. Sinks and sources current. Data at DOUT can be clocked out on the falling edge (mode 0) or rising edge (mode 1) of SCLK (Table 1). 15 OUTD DAC D Voltage Output 16 OUTC DAC C Voltage Output Chip Select Input. Data is shifted in and out when CS is low. Programming commands are executed when CS returns high. Serial Clock Input. Data is clocked in on the rising edge and clocked out on the falling edge (default) or rising edge (A2 = 1; see Table 1). Serial Data Input. Data is clocked in on the rising edge of SCLK. Detailed Description clocked out 16 clock cycles later, either at SCLK’s falling edge (default or mode 0) or rising edge (mode 1). Serial Interface CS must be low to enable the device. If CS is high, the interface is disabled and DOUT remains unchanged. CS must go low at least 40ns before the first rising edge of the clock pulse to properly clock in the first bit. With CS low, data is clocked into the MAX5258/MAX5259’s internal shift register on the rising edge of the external serial clock. Always clock in the full 16 bits. At power-on, the serial interface and all DACs are cleared and set to code zero. The serial data output (DOUT) is set to transition on SCLK’s falling edge. The MAX5258/MAX5259 communicate with microprocessors (µPs) through a synchronous, 3-wire interface (Figure 1). Data is sent MSB first and can be transmitted in two 4-bit and one 8-bit (byte) packets, or one 16-bit word. The first two bits are ignored. A 4-wire interface adds a line for LDAC, allowing asynchronous updating. Data is transmitted and received simultaneously. Figure 2 shows the detailed serial-interface timing. Note that the clock should be low if it is stopped between updates. DOUT does not go into a high-impedance state if the clock idles or CS is high. Serial data is clocked into the data registers in MSB-first format, with the address and configuration information preceding the actual DAC data. Data is clocked in on SCLK’s rising edge while CS is low. Data at DOUT is 10 Serial Input Data Format and Control Codes The 16-bit serial input format, shown in Figure 3, comprises two “don’t care” bits, three DAC address bits (A2, A1, A0), three control bits (C2, C1, C0), and eight data bits (D7…D0). The 6-bit address/control code configures the DAC as shown in Table 1. ______________________________________________________________________________________ +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259 INSTRUCTION EXECUTED CS SCLK DIN X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 DACA DACA X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 DOUT MODE 1 DATA FROM PREVIOUS DATA INPUT DATA FROM PREVIOUS DATA INPUT X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 DOUT MODE 0 (DEFAULT) Figure 1. 3-Wire Interface Timing CS tCSW tCH tCSS tCP tCSH tCS1 tCL SCLK tDS tDH DIN tD02 tD01 DOUT tCLL tLDAC LDAC Figure 2. Detailed Serial-Interface Timing Diagram ______________________________________________________________________________________ 11 MAX5258/MAX5259 +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers Table 1. Serial-Interface Programming Commands LDAC 16-BIT SERIAL WORD* A2 A1 A0 C2 C1 C0 D7……D0 X X X 0 0 0 XXXXXXXX FUNCTION X No operation (NOP); shift data in shift registers. X X X 0 0 1 XXXXXXXX X Clears all input and DAC registers and sets all DAC outputs to zero. X X X 0 1 0 XXXXXXXX X Software shutdown. Output buffers can be individually shut down with zeros in the corresponding data bits. 0 X X 0 1 1 XXXXXXXX X DOUT Phase Mode 0. DOUT transitions on the falling edge of SCLK. 1 X X 0 1 1 XXXXXXXX X DOUT Phase Mode 1. DOUT transitions on the rising edge of SCLK. X X X 1 0 0 8-bit DAC data X Loads all DACs with the same data 0 0 0 1 0 1 8-bit DAC data H Load input register A. All DAC outputs unchanged. 0 0 1 1 0 1 8-bit DAC data H Load input register B. All DAC outputs unchanged. 0 1 0 1 0 1 8-bit DAC data H Load input register C. All DAC outputs unchanged. 0 1 1 1 0 1 8-bit DAC data H Load input register D. All DAC outputs unchanged. 1 0 0 1 0 1 8-bit DAC data H Load input register E. All DAC outputs unchanged. 1 0 1 1 0 1 8-bit DAC data H Load input register F. All DAC outputs unchanged. 1 1 0 1 0 1 8-bit DAC data H Load input register G. All DAC outputs unchanged. 1 1 1 1 0 1 8-bit DAC data H Load input register H. All DAC outputs unchanged. 0 0 0 1 1 0 8-bit DAC data H Load input register A. Update OUTA. All other DAC outputs unchanged. 0 0 1 1 1 0 8-bit DAC data H Load input register B. Update OUTB. All other DAC outputs unchanged. 0 1 0 1 1 0 8-bit DAC data H Load input register C. Update OUTC. All other DAC outputs unchanged. 0 1 1 1 1 0 8-bit DAC data H Load input register D. Update OUTD. All other DAC outputs unchanged. 1 0 0 1 1 0 8-bit DAC data H Load input register E. Update OUTE. All other DAC outputs unchanged. 1 0 1 1 1 0 8-bit DAC data H Load input register F. Update OUTF. All other DAC outputs unchanged. 1 1 0 1 1 0 8-bit DAC data H Load input register G. Update OUTG. All other DAC outputs unchanged. 1 1 1 1 1 0 8-bit DAC data H Load input register H. Update OUTH. All other DAC outputs unchanged. X X X 1 1 1 XXXXXXXX H Software LDAC command. Updates all DACs from their respective input registers. * The first two bits are “don’t care.” 12 ______________________________________________________________________________________ +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers A2 A1 Don’t Care A0 C2 0 C1 0 C0 0 D7 D6 D5 D4 D3 Don’t Care D2 D1 D0 (LDAC = X) The no-operation (NOP) command allows data to be shifted through the MAX5258/MAX5259 shift register without affecting the input or DAC registers. This is useful in daisy-chaining (see the Daisy-Chaining Devices section). For this command, the data bits are "Don’t Cares." As an example, three MAX5258s are daisy-chained (A, B, and C), and devices A and C need to be updated. The 48-bit-wide command would consist of one 16-bit word for device C, followed by an NOP instruction for device B and a third 16-bit word with data for device A. At the rising edge of CS, device B will not change state. Clear A2 A1 A0 Don’t Care C2 C1 C0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 Don’t Care (LDAC = X) The clear command clears all input and DAC registers and sets all DAC outputs to zero. This command brings the DAC out of shutdown. Software Shutdown A2 A1 A0 Don’t Care C2 C1 C0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 8-Bit Data (LDAC = X) Shuts down all output buffer amplifiers and voltage references. Output buffers can be individually disabled with the corresponding zeros in the data bits (D7-D0). If all data bits are zero, only the power-on reset circuit is active, and the device draws 10µA (max). There are four ways to bring the device out of shutdown: POR, CLEAR, LOAD SAME DATA, LOAD INPUT, AND DAC REGISTERS. Set DOUT Phase—SCLK Falling (Mode 0, Default) A2 0 A1 X A0 X C2 0 C1 1 C0 1 D7 D6 D5 D4 D3 8-Bit Data D2 D1 D0 (LDAC = X) This command sets DOUT to transition at the falling edge of SCLK. The same command also updates all DAC registers with the contents of their respective input registers, identical to the LDAC command. This is the default mode on power-up. Set DOUT Phase—SCLK Rising (Mode 1) A2 1 A1 X A0 X C2 0 C1 1 C0 1 D7 D6 D5 D4 D3 8-Bit Data D2 D1 D0 (LDAC = X) Mode 1 sets the serial output DOUT to transition at the rising edge of SCLK. Once this command is issued, DOUT’s phase is latched and will not change except on power-up or if the specific command to set the phase to falling edge is issued. This command also loads all DAC registers with the contents of their respective input registers, and is identical to the LDAC command. ______________________________________________________________________________________ 13 MAX5258/MAX5259 No Operation (NOP) MAX5258/MAX5259 +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers Load All DACs with Shift-Register Data A2 A1 Don’t Care A0 C2 1 C1 0 C0 0 D7 D6 D5 D4 D3 8-Bit Data D2 D1 D0 (LDAC = X) All eight DAC registers are updated with shift-register data. This command allows all DACs to be set to any analog value within the reference range. This command can be used to substitute CLEAR if code 00 (hex) is programmed, which clears all DACs. This command brings the device out of shutdown. Load Input Register, DAC Registers Unchanged (Single Update Operation) A2 A1 Address A0 C2 1 C1 0 C0 1 D7 D6 D5 D4 D3 8-Bit Data D2 D1 D0 (LDAC = X) When performing a single update operation, A2-A0 selects the respective input register. At the rising edge of CS, the selected input register is loaded with the current shift-register data. All DAC outputs remain unchanged. This preloads individual data in the input register without changing the DAC outputs. Load Input and DAC Registers A2 A1 Address A0 C2 1 C1 1 C0 0 D7 D6 D5 D4 D3 8-Bit Data D2 D1 D0 (LDAC = X) This command directly loads current shift-register data in the selected input and DAC registers at the rising edge of CS. A2-A0 set the DAC address. For example, to load all eight DAC registers simultaneously with individual settings, eight commands are required. First perform seven single input register update operations (C2 = 1, C1 = 0, C0 = 1) for DACs A, B, C, D, E, F, and G (C2 = 1, C1 = 0, C0 = 1). The final command loads input register H and updates all eight DAC registers from their respective input registers. This command brings the device out of shutdown. Software “LDAC” Command A2 A1 Address A0 C2 1 C1 1 C0 1 D7 D6 D5 D4 D3 8-Bit Data D2 D1 D0 (LDAC = X) All DAC registers are updated with the contents of their respective input registers at the rising edge of CS. This is a synchronous software command that performs the same function as the asynchronous LDAC. 14 ______________________________________________________________________________________ +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers Serial Data Output DOUT is the internal shift-register’s output. DOUT can be programmed to clock out data on the falling edge of SCLK (mode 0) or the rising edge (mode 1). In mode 0, output data lags input data by 16.5 clock cycles, maintaining compatibility with MICROWIRE and SPI. In mode 1, output data lags input data by 16 clock cycles. On power-up, DOUT defaults to mode 0 timing. DOUT never three-states; it always actively drives either high or low and remains unchanged when CS is high. Interfacing to the Microprocessor The MAX5258/MAX5259 are MICROWIRE (Figure 5) and SPI/QSPI (Figure 6) compatible. For SPI and QSPI, clear the CPOL and CPHA configuration bits (CPOL = CPHA = 0). The SPI/QSPI CPOL = CPHA = 1 configuration can also be used if the DOUT output is ignored. The MAX5258/MAX5259 can interface with Intel’s 80C5X/80C3X family in mode 0 if the SCLK clock polarity is inverted. Universally, if a serial port is not available, three lines from one of the parallel ports can be used for bit manipulation. Digital feedthrough at the voltage outputs is greatly minimized by operating the serial clock only to update the registers. See the Clock Feedthrough photo in the Typical Operating Characteristics section. The clock idle state is low. Daisy-Chaining Devices Any number of MAX5258/MAX5259s can be daisychained by connecting DOUT of one device to DIN of the following device in the chain with all devices in mode zero. The NOP instruction (Table 1) allows data to be passed from DIN to DOUT without changing the input or DAC registers of the passing device. A 3-wire interface updates daisy-chained or individual MAX5258/MAX5259s simultaneously by bringing CS high (Figure 7). Analog Section DAC Operation The MAX5258/MAX5259 use a matrix decoding architecture for the DACs, which saves power in the overall system. The external reference voltage is divided down by a resistor string placed in a matrix fashion. Row and THIS IS THE FIRST BIT SHIFTED IN MSB DOUT LSB X X A2 A1 A0 C2 C1 C0 D7 D6 . . . D1 D0 CONTROL AND ADDRESS BITS DIN 8-BIT DAC DATA Figure 3. Serial Input Format column decoders select the appropriate tab from the resistor string to provide the needed analog voltages. The resistor string presents a code-independent input impedance to the reference and guarantees a monotonic output. Figure 8 shows a simplified diagram of one of the eight DACs. Reference Input The voltage at REF sets the full-scale output voltage for all eight DACs. The 230kΩ typical input impedance at REF is code independent. The output voltage for any DAC can be represented by a digitally programmable voltage source as follows: VOUT = (NB ✕ VREF) / 256, where NB is the numerical value of the DAC’s binary input code. Output Buffer Amplifiers All MAX5258/MAX5259 voltage outputs are internally buffered by precision unity-gain followers that slew at about 0.55V/µs. The outputs can swing from GND to VDD. With a 0 to VREF (or VREF to 0) output transition, the amplifier outputs will typically settle to 1/2LSB in 10µs when loaded with 10kΩ in parallel with 100pF. The buffer amplifiers are stable with any combination of resistive (≥10kΩ) or capacitive (≤100pF) loads. Applications Information DAC Linearity and Voltage Offset The output buffer can have a negative input offset voltage that would normally drive the output negative, but since there is no negative supply, the output remains at GND (Figure 9). When linearity is determined using the endpoint method, it is measured between code 10 (0A hex) and full-scale code (FF hex) after offset and gain error are calibrated out. With a single-supply, negative offset causes the output not to change with an input code transition near zero (Figure 9). Thus, the lowest code that produces a positive output is the lower endpoint. ______________________________________________________________________________________ 15 MAX5258/MAX5259 LDAC Operation (Hardware) LDAC is typically used in 4-wire interfaces (Figure 4). This command is level sensitive, and it allows asynchronous hardware control of the DAC outputs. With LDAC low, all eight DAC registers are transparent, and any time an input register is updated, the DAC output immediately follows. MAX5258/MAX5259 +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers DIN SCLK LDAC CS1 TO OTHER SERIAL DEVICES CS2 CS3 CS CS CS MAX5258/ LDAC MAX5259 MAX5258/ LDAC MAX5259 LDAC MAX5259 SCLK SCLK SCLK DIN DIN DIN MAX5258/ Figure 4. Multiple MAX5258’s Sharing One DIN Line. (Simultaneously Update by Strobing LDAC, or Specifically Update by Enabling an Individual CS) SCLK SK MAX5258/ DIN MAX5259 SO MICROWIRE PORT MAX5258/ MAX5259 MOSI SPI/QSPI DIN PORT SCLK CS I/O CS SCK I/O CPOL = 0, CPHA = 0 Figure 5. Connections for MICROWIRE SCLK Figure 6. Connections for SPI/QSPI MAX5258/ MAX5258/ MAX5258/ SCLK MAX5259 SCLK MAX5259 SCLK MAX5259 DIN DIN CS CS DOUT DOUT DIN CS DEVICE A DOUT DIN CS DEVICE B TO OTHER SERIAL DEVICES DEVICE C MAX5258/ SCLK SCLK MAX5259 DIN DIN CS CS Figure 7. Daisy-Chained or Individual MAX5258s Simultaneously Updated by Bringing CS High (Only Three Wires Are Required) 16 ______________________________________________________________________________________ +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers MAX5258/MAX5259 REF R0 R1 R15 D7 D5 R16 MSB DECODER D6 OUTPUT VOLTAGE D4 R255 O NEGATIVE OFFSET DAC CODE LSB DECODER D3 D2 D1 D0 DAC A Figure 8. DAC Simplified Circuit Diagram Figure 9. Effect of Negative Offset (Single Supply) ratings. Do not apply signals to the digital inputs before the device is fully powered-up. SYSTEM GND OUTB OUTC OUTA OUTD GND DOUT VDD DIN REF Power-Supply Bypassing and Ground Management Bypass VDD with a 0.1µF capacitor, located as close to VDD and GND as possible. Careful PC board layout minimizes crosstalk among DAC outputs and digital inputs. Figure 10 shows suggested circuit board layout to minimize crosstalk. Unipolar-Output, Two-Quadrant Multiplication In unipolar operation, the output voltages and the reference input are the same polarity. Figure 11 shows the MAX5258/MAX5259 unipolar configuration, and Table 2 shows the unipolar code. LDAC Figure 10. Suggested PC Board Layout for Minimizing Crosstalk (Bottom View) Power Sequencing The voltage applied to REF should not exceed VDD at any time. If proper power sequencing is not possible, connect an external Schottky diode between REF and VDD to ensure compliance with the absolute maximum ______________________________________________________________________________________ 17 MAX5258/MAX5259 +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers REFERENCE INPUT REF Table 2. Unipolar Code Table +3V DAC CONTENTS VDD OUT A DAC A OUT B DAC B ANALOG OUTPUT MSB LSB 1111 1111 1000 0001 +VREF(129/256) 1000 0000 +VREF(128/256) = +VREF/2 0111 1111 +VREF(127/256) 0000 0001 +VREF(1/256) 0000 0000 0 +VREF(255/256) Note: 1LSB = (VREF) ✕ (28) = +VREF (1 / 256) OUT C ____________________Chip Information TRANSISTOR COUNT: 13625 PROCESS: BiCMOS DAC C OUT D DAC D OUT E DAC E OUT F DAC F OUT G DAC G OUT H DAC H MAX5258/ MAX5259 Figure 11. Unipolar Output Circuit 18 ______________________________________________________________________________________ +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers DOUT VDD LDAC REF DECODE CONTROL OUT A INPUT REGISTER A DAC REGISTER A INPUT REGISTER B DAC REGISTER B INPUT REGISTER C DAC REGISTER C INPUT REGISTER D DAC REGISTER D INPUT REGISTER E DAC REGISTER E INPUT REGISTER F DAC REGISTER F INPUT REGISTER G DAC REGISTER G INPUT REGISTER H DAC REGISTER H DAC A OUT B DAC B OUT C DAC C OUT D 16-BIT SHIFT REGISTER DAC D OUT E DAC E OUT F DAC F OUT G DAC G OUT H SR CONTROL DAC H MAX5258/ MAX5259 CS DIN SCLK GND ______________________________________________________________________________________ 19 MAX5258/MAX5259 Functional Diagram MAX5258/MAX5259 +3V/+5V, Low-Power, 8-Bit Octal DAC with Rail-to-Rail Output Buffers QSOP.EPS Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.