MICROCHIP MCP616_05

MCP616/7/8/9
2.3V to 5.5V Micropower Bi-CMOS Op Amps
Features
Description
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The MCP616/7/8/9 family of operational amplifiers (op
amps) from Microchip Technology Inc. are capable of
precision, low-power, single-supply operation. These
op amps are unity-gain stable, have low input offset
voltage (±150 µV, max.), rail-to-rail output swing and
low input offset current (0.3 nA, typ.). These features
make this family of op amps well suited for batterypowered applications.
Low Input Offset Voltage: ±150 µV (max.)
Low Noise: 2.2 µVP-P (typ., 0.1 Hz to 10 Hz)
Rail-to-Rail Output
Low Input Offset Current: 0.3 nA (typ.)
Low Quiescent Current: 25 µA (max.)
Power Supply Voltage: 2.3V to 5.5V
Unity Gain Stable
Chip Select (CS) Capability: MCP618
Industrial Temperature Range: -40°C to +85°C
No Phase Reversal
Available in Single, Dual and Quad Packages
Typical Applications
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Battery Power Instruments
Weight Scales
Strain Gauges
Medical Instruments
Test Equipment
Package Types
MCP616
PDIP, SOIC, MSOP
Available Tools
• SPICE Macro Models (at www.microchip.com)
• FilterLab® Software (at www.microchip.com)
NC
VIN–
VIN+
VSS
598 Samples
VDD = 5.5V
10%
8%
6%
4%
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
MCP617
PDIP, SOIC, MSOP
VOUTA 1
NC
VDD
VINA– 2
VOUT VINA+ 3
NC
VSS 4
8
7
6
5
VDD
VOUTB
VINB–
VINB+
MCP619
PDIP, SOIC, TSSOP
CS VOUTA
VDD VINA–
VOUT VINA+
VDD
NC
VINB+
VINB–
VOUTB
1
2
3
4
5
6
7
14 VOUTD
13 VIND–
12 VIND+
11 VSS
10 VINC+
9 VINC–
8 VOUTC
2%
100
80
60
40
0
20
-20
-40
-60
-80
0%
-100
Percentage of Occurrences
12%
NC
VIN–
VIN+
VSS
MCP618
PDIP, SOIC, MSOP
Input Offset Voltage
14%
The single MCP616, the single MCP618 with Chip
Select (CS) and the dual MCP617 are all available in
standard 8-lead PDIP, SOIC and MSOP packages. The
quad MCP619 is offered in standard 14-lead PDIP,
SOIC and TSSOP packages. All devices are fully
specified from -40°C to +85°C, with power supplies
from 2.3V to 5.5V.
Input Offset Voltage (µV)
© 2005 Microchip Technology Inc.
DS21613B-page 1
MCP616/7/8/9
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS .......................................................................7.0V
All Inputs and Outputs ................... VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short Circuit Current ................................. Continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ....................................-65°C to +150°C
Maximum Junction Temperature (TJ) ......................... +150°C
ESD protection on all pins (HBM;MM) ...................4 kV; 200V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT ≈ VDD/2
and RL = 100 kΩ to VDD/2.
Parameters
Sym
Min
Typ
Max
Units
VOS
ΔVOS/ΔTA
PSRR
–150
—
86
—
±2.5
105
+150
—
—
µV
µV/°C
dB
IB
IB
IB
IOS
ZCM
ZDIFF
-35
-70
—
—
—
—
-15
-21
-12
±0.15
600||4
3||2
-5
—
—
—
—
—
VCMR
CMRR
VSS
80
100
VDD – 0.9
—
V
dB
Open-Loop Gain
DC Open-Loop Gain (large signal)
AOL
100
120
—
dB
DC Open-Loop Gain (large signal)
AOL
95
115
—
dB
VOL, VOH
VSS + 15
—
VDD – 20
mV
VOL, VOH
VSS + 45
—
VDD – 60
mV
VOUT
VSS + 50
—
VDD – 50
mV
VOUT
VSS + 100
—
VDD – 100
mV
ISC
ISC
—
—
±7
±17
—
—
mA
mA
RL = 25 kΩ to VDD/2,
0.5V output overdrive
RL = 5 kΩ to VDD/2,
0.5V output overdrive
RL = 25 kΩ to VDD/2,
AOL ≥ 100 dB
RL = 5 kΩ to VDD/2,
AOL ≥ 95 dB
VDD = 2.3V
VDD = 5.5V
VDD
IQ
2.3
12
—
19
5.5
25
V
µA
IO = 0
Input Offset
Input Offset Voltage
Input Offset Drift with Temperature
Power Supply Rejection
Input Bias Current and Impedance
Input Bias Current
At Temperature
At Temperature
Input Offset Current
Common Mode Input Impedance
Differential Input Impedance
Common Mode
Common Mode Input Voltage Range
Common Mode Rejection Ratio
Output
Maximum Output Voltage Swing
Linear Output Voltage Range
Output Short Circuit Current
Power Supply
Supply Voltage
Quiescent Current per Amplifier
DS21613B-page 2
Conditions
TA = -40°C to +85°C
nA
nA
TA = -40°C
nA
TA = +85°C
nA
MΩ||pF
MΩ||pF
VDD = 5.0V,
VCM = 0.0V to 4.1V
RL = 25 kΩ to VDD/2,
VOUT = 0.05V to VDD – 0.05V
RL = 5 kΩ to VDD/2,
VOUT = 0.1V to VDD – 0.1V
© 2005 Microchip Technology Inc.
MCP616/7/8/9
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
Parameters
Sym
Min
Typ
Max
Units
kHz
Conditions
AC Response
Gain Bandwidth Product
GBWP
—
190
—
Phase Margin
PM
—
57
—
°
Slew Rate
SR
—
0.08
—
V/µs
G = +1
Noise
Input Noise Voltage
Eni
—
2.2
—
µVP-P
Input Noise Voltage Density
eni
—
32
—
nV/√Hz
f = 0.1 Hz to 10 Hz
f = 1 kHz
Input Noise Current Density
ini
—
70
—
fA/√Hz
f = 1 kHz
MCP618 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
Parameters
Sym
Min
Typ
Max
Units
Conditions
CS Logic Threshold, Low
VIL
VSS
—
0.2 VDD
V
CS Input Current, Low
ICSL
–1.0
0.01
—
µA
CS Logic Threshold, High
VIH
0.8 VDD
—
VDD
V
CS Input Current, High
ICSH
—
0.01
2
µA
CS = VDD
ISS
-2
-0.05
—
µA
CS = VDD
IO(LEAK)
—
10
—
nA
CS = VDD
CS Low to Amplifier Output Turn-on Time
tON
—
9
100
µs
CS = 0.2VDD to VOUT = 0.9(VDD/2),
G = +1 V/V, RL = 1 kΩ to VSS
CS High to Amplifier Output High-Z
tOFF
—
0.1
—
µs
CS = 0.8VDD to VOUT = 0.1(VDD/2),
G = +1 V/V, RL = 1 kΩ to VSS
VHYST
—
0.6
—
V
VDD = 5.0V
CS Low Specifications
CS = VSS
CS High Specifications
GND Current
Amplifier Output Leakage
CS Dynamic Specifications
CS Hysteresis
VIH
VIL
CS
tOFF
tON
VOUT
High-Z
ISS -50 nA (typ.)
High-Z
-19 µA (typ.)
ICS 10 nA (typ.)
-50 nA (typ.)
10 nA (typ.)
FIGURE 1-1:
Timing Diagram for the CS
Pin on the MCP618.
© 2005 Microchip Technology Inc.
DS21613B-page 3
MCP616/7/8/9
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.3V to +5.5V and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+85
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 8L-PDIP
θJA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Thermal Resistance, 8L-MSOP
θJA
—
206
—
°C/W
Thermal Resistance, 14L-PDIP
θJA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
120
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Conditions
Temperature Ranges
Note 1
Thermal Package Resistances
Note 1:
The MCP616/7/8/9 operate over this extended temperature range, but with reduced performance. In any case, the
Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
DS21613B-page 4
© 2005 Microchip Technology Inc.
MCP616/7/8/9
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Input Offset Voltage (µV)
FIGURE 2-4:
VDD = 5.5V.
18%
Offset Voltage (µV)
FIGURE 2-5:
VDD = 2.3V.
Input Bias Current (nA)
FIGURE 2-3:
VDD = 5.5V.
Input Bias Current at
© 2005 Microchip Technology Inc.
10
8
8
10
0.7
0.6
0.5
0.4
0.3
0.2
-10
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
-21
0%
0.1
2%
0.0
4%
-0.1
6%
-0.2
8%
-0.3
10%
600 Samples
VDD = 5.5V
-0.4
12%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
Input Offset Voltage Drift at
-0.5
600 Samples
VDD = 5.5V
-0.6
Input Offset Voltage at
-0.7
14%
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
16%
-22
Percentage of Occurrences
FIGURE 2-2:
VDD = 2.3V.
6
2%
0%
100
80
60
40
20
0
-20
-40
-60
-80
0%
4%
6
2%
6%
4
4%
8%
2
6%
10%
0
8%
12%
-2
10%
14%
598 Samples
VDD = 2.3V
TA = -40°C to +85°C
-4
12%
16%
-6
598 Samples
VDD = 2.3V
Input Offset Voltage Drift at
-8
Input Offset Voltage at
-10
14%
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
16%
-100
Percentage of Occurrences
FIGURE 2-1:
VDD = 5.5V.
4
100
80
60
40
0
20
-20
-40
-60
-80
0%
2
2%
0
4%
-2
6%
-4
8%
598 Samples
VDD = 5.5V
TA = -40°C to +85°C
-6
10%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
-8
598 Samples
VDD = 5.5V
-10
12%
Percentage of Occurrences
14%
-100
Percentage of Occurrences
Note: Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
Input Offset Current (nA)
FIGURE 2-6:
VDD = 5.5V.
Input Offset Current at
DS21613B-page 5
MCP616/7/8/9
Note: Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
Input Bias Current (nA)
Input Offset Voltage (µV)
VDD = 5.5V
Representative Part
100
VDD = 5.5V
50
0
VDD = 2.3V
-50
-100
-150
-5
0.8
IOS
-10
-15
0.4
IB
-20
-25
0
25
50
75
100
-50
Ambient Temperature (°C)
0.2
115
VDD = 5.5V
VDD = 2.3V
110
100
90
0
25
50
75
Ambient Temperature (°C)
-50
100
-25
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-11:
Temperature.
100
CMRR, PSRR vs. Ambient
9
40
VDD – VOH
Output Voltage Headroom
(mV)
RL = 5 kΩ
VDD = 5.5V
20
15
10
5
CMRR
95
80
-25
FIGURE 2-8:
Quiescent Current vs.
Ambient Temperature.
25
PSRR
105
85
-50
30
0.0
100
120
24
22
20
18
16
14
12
10
8
6
4
2
0
35
-25
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-10:
Input Bias, Offset Currents
vs. Ambient Temperature.
CMRR, PSRR (dB)
Quiescent Current
(µA/Amplifier)
FIGURE 2-7:
Input Offset Voltage vs.
Ambient Temperature.
Output Voltage Headroom
(mV)
0.6
-25
-50
1.0
Input Offset Current (nA)
0
150
VOL – VSS
VDD = 2.3V
8
RL = 25 kΩ
VDD – VOH
7
VDD = 5.5V
6
5
4
3
2
VOL – VSS
1
VDD = 2.3V
0
0
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
FIGURE 2-9:
Maximum Output Voltage
Swing vs. Ambient Temperature at RL = 5 kΩ.
DS21613B-page 6
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
FIGURE 2-12:
Maximum Output Voltage
Swing vs. Ambient Temperature at RL = 25 kΩ.
© 2005 Microchip Technology Inc.
MCP616/7/8/9
100
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
IOS
IB
FIGURE 2-17:
Input Offset Voltage vs.
Common Mode Input Voltage.
50
40
30
20
10
0
-10
-20
-30
-40
-50
RL = 25 kΩ
VDD = 5.5V
VDD = 2.3V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-15:
Input Bias, Offset Currents
vs. Common Mode Input Voltage.
© 2005 Microchip Technology Inc.
5.5
Common Mode Input Voltage (V)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
1.5
VDD = 5.5V
1.0
100
Slew Rate vs. Ambient
TA = +85°C
TA = +25°C
TA = -40°C
0.5
30
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
0.0
Input Bias Current (nA)
FIGURE 2-14:
Temperature.
0
25
50
75
Ambient Temperature (°C)
5.0
-25
Input Offset Current (nA)
-50
TA = +85°C
TA = +25°C
TA = -40°C
4.5
VDD = 5.0V
VDD = 5.5V
4.0
High-to-Low Transition
100
80
60
40
20
0
-20
-40
-60
-80
-100
3.5
Low-to-High Transition
-25
0
25
50
75
Ambient Temperature (°C)
100
90
80
70
60
50
40
30
20
10
0
100
FIGURE 2-16:
Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
Input Offset Voltage (µV)
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
2.0
Slew Rate (V/µs)
FIGURE 2-13:
Output Short Circuit Current
vs. Ambient Temperature.
-50
3.0
0
25
50
75
Ambient Temperature (°C)
-0.5
-25
Input Offset Voltage (µV)
-50
2.5
VDD = 2.3V
0
2.0
| ISC– |
5
PM
1.5
10
1.0
15
GBWP
0.5
VDD = 5.5V
20
200
180
160
140
120
100
80
60
40
20
0
0.0
ISC+
Phase Margin (°)
25
Gain Bandwidth Product
(kHz)
Output Short Circuit Current
(mA)
Note: Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
FIGURE 2-18:
Output Voltage.
Input Offset Voltage vs.
DS21613B-page 7
MCP616/7/8/9
Note: Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
Output Voltage Headroom (mV)
Quiescent Current
(µA/Amplifier)
25
20
15
10
TA = +85°C
TA = +25°C
TA = -40°C
5
0
1,000
VDD = 2.3V
100
VDD – VOH
10
VOL – VSS
1
10µ
0.01
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-19:
Quiescent Current vs.
Power Supply Voltage.
125
DC Open-Loop Gain (dB)
120
VDD = 5.5V
110
VDD = 2.3V
100
95
RL = 25 kΩ
115
110
105
90
FIGURE 2-20:
Load Resistance.
200
180
160
140
1k
10k
1
10
Load Resistance (Ω)
120
100
80
PM
60
40
20
100
90
80
70
60
50
40
30
20
10
0
1k
1
10k
100k
10
100
Load Resistance (Ω)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
FIGURE 2-23:
DC Open-Loop Gain vs.
Power Supply Voltage.
140
Referred to Input
130
0
1M
1,000
FIGURE 2-21:
Gain-Bandwidth Product,
Phase Margin vs. Load Resistance.
DS21613B-page 8
2.0
Power Supply Voltage (V)
DC Open-Loop Gain vs.
GBWP
1.5
100k
100
Phase Margin (°)
100
0.1
Gain Bandwidth Product
(kHz)
10m
10
120
Channel-to-Channel
Seperation (dB)
DC Open-Loop Gain (dB)
125
105
100µ
1m
0.1
1
Output Current Magnitude (A)
FIGURE 2-22:
Output Voltage Headroom
vs. Output Current Magnitude.
130
115
VDD = 5.5V
120
110
100
90
80
70
100
1.E+02
1k
10k
1.E+03
1.E+04
Frequency (Hz)
100k
1.E+05
FIGURE 2-24:
Channel-to-Channel
Separation vs. Frequency (MCP617 and
MCP619 only).
© 2005 Microchip Technology Inc.
MCP616/7/8/9
0
120
-30
100
-60
Phase
80
-90
60
-120
40
-150
Gain
20
-180
0
-210
120
110
CMRR, PSRR (dB)
140
Open-Loop Phase (°)
Open-Loop Gain (dB)
Note: Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
Open-Loop Gain, Phase vs.
1,000
ini
100
100
eni
70
60
50
40
1
1.E+00
10
10
0.1
1
10 100 1k
10k
1.E- 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0
01
0
1
2
3
4
Frequency (Hz)
FIGURE 2-26:
Input Noise Voltage, Current
Densities vs. Frequency.
1k
1.E+03
10k
1.E+04
CMRR, PSRR vs.
VDD = 5.5V
VDD = 2.3V
1
0.1
100
1.E+02
1k
10k
1.E+03
1.E+04
Frequency (Hz)
100k
1.E+05
FIGURE 2-29:
Maximum Output Voltage
Swing vs. Frequency.
Gain = -1
Output Voltage (20 mV/div)
Output Voltage (20 mV/div)
Gain = +1
Time (50 µs/div)
FIGURE 2-27:
Pulse Response.
10
100
1.E+01
1.E+02
Frequency (Hz)
10
Maximum Output Voltage
Swing (V P-P)
1,000
PSRR-
FIGURE 2-28:
Frequency.
10,000
Input Noise Current
Density (fA/—Hz)
Input Noise Voltage
Density (nV/—Hz)
10,000
CMRR
30
20
0.1
1.E-01
-20
-240
0.01 1.E0.1 1.E+
1 1.E+
10 1.E+
100 1.E+
1k 1.E+
10k 100k
1M
1.E1.E+ 1.E+
02 01 00 Frequency
01 02 03
(Hz) 04 05 06
FIGURE 2-25:
Frequency.
PSRR+
100
90
80
Small-Signal, Non-Inverting
© 2005 Microchip Technology Inc.
Time (50 µs/div)
FIGURE 2-30:
Pulse Response.
Small-Signal, Inverting
DS21613B-page 9
MCP616/7/8/9
Note: Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
5.0
Gain = +1
VDD = 5.0V
4
3
2
1
Gain = -1
VDD = 5.0V
4.5
Output Voltage (V)
Output Voltage (V)
5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.0
Time (50 µs/div)
Time (50 µs/div)
5.0
10
4.5
5
4.0
3.5
3.0
CS
VDD = 5.0V
Gain = +1 V/V
RL = 1 kΩ to VSS
0
-5
-10
VOUT
2.5
-15
2.0
-20
1.5
-25
1.0
Output
High-Z
Output
On
Output
High-Z
0.5
-30
-35
0.0
-40
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Large-Signal, Inverting
VDD = 5.0V
Hysteresis
Output
On
CS swept
High-to-Low
CS swept
Low-to-High
Output
High-Z
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Chip Select Voltage (V)
Time (5 µs/div)
FIGURE 2-32:
Chip Select (CS) to
Amplifier Output Response Time (MCP618 only).
6
Input, Output Voltages (V)
FIGURE 2-34:
Pulse Response.
Internal CS Switch Output (V)
Large-Signal, Non-Inverting
Chip Select Voltage (V)
Output Voltage (V)
FIGURE 2-31:
Pulse Response.
FIGURE 2-35:
Chip Select (CS) Internal
Hysteresis (MCP618 only).
Gain = +2 V/V
VDD = 5.0V
5
4
3
2
VIN
1
0
VOUT
-1
Time (100 µs/div)
FIGURE 2-33:
The MCP616/7/8/9 Show
No Phase Reversal.
DS21613B-page 10
© 2005 Microchip Technology Inc.
MCP616/7/8/9
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP616
MCP617
MCP618
MCP619
Symbol
6
1
6
1
VOUT, VOUTA
Output (op amp A)
2
2
2
2
VIN–, VINA–
Inverting Input (op amp A)
3
3
3
3
VIN+, VINA+
Non-inverting Input (op amp A)
7
8
7
4
VDD
—
5
—
5
VINB+
Non-inverting Input (op amp B)
—
6
—
6
VINB–
Inverting Input (op amp B)
—
7
—
7
VOUTB
Output (op amp B)
—
—
—
8
VOUTC
Output (op amp B)
—
—
—
9
VINC–
Inverting Input (op amp C)
—
—
—
10
VINC+
Non-inverting Input (op amp C)
4
4
4
11
VSS
—
—
—
12
VIND+
Non-inverting Input (op amp D)
—
—
—
13
VIND–
Inverting Input (op amp D)
—
—
—
14
VOUTD
Output (op amp D)
—
—
8
—
CS
Chip Select
1, 5, 8
—
1, 5
—
NC
No Internal Connection
3.1
Analog Outputs
The output pins are low-impedance voltage sources.
3.2
Analog Inputs
The non-inverting and inverting inputs are highimpedance PNP inputs with low bias currents.
3.3
Chip Select Digital Input (CS)
This is a CMOS, Schmitt-triggered input that places the
MCP618 op amp into a low-power mode of operation.
© 2005 Microchip Technology Inc.
3.4
Description
Positive Power Supply
Negative Power Supply
Power Supply (VSS and VDD)
The positive power supply (VDD) is 2.5V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single-supply
(positive) configuration. In this case, VSS is connected
to ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These parts should
use a bulk capacitor (typically 1 µF or larger) within
100 mm of the VDD pin; it can be shared with nearby
analog parts.
DS21613B-page 11
MCP616/7/8/9
4.0
APPLICATIONS INFORMATION
The MCP616/7/8/9 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process,
which includes PNP transistors. These op amps are
unity-gain stable and suitable for a wide range of
general purpose applications.
4.1
Inputs
The MCP616/7/8/9 op amps are designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 2-33 shows the input voltage
exceeding the supply voltage without any phase reversal.
4.2
The MCP616/7/8/9 family of op amps have a PNP input
differential pair that gives good DC performance. They
have very low input offset voltage (±150 µV, max.) at
TA = +25°C, with a typical bias current of -15 nA
(sourced out of the inputs).
There must be a DC path to ground (or power supply)
from both inputs, or the op amp will not bias properly.
The DC resistances seen by the op amp inputs (R1||R2
and R4||R5 in Figure 4-2) need to be equal and less
than 100 kΩ, to minimize the total DC offset.
R1
RIN
MCP61X
VOUT
VIN
( Maximum expected VIN ) – V DD
RIN ≥ -----------------------------------------------------------------------------2 mA
V SS – ( Minimum expected V IN )
R IN ≥ --------------------------------------------------------------------------2 mA
R2
V1
The inputs of the MCP616/7/8/9 op amps connect to a
differential PNP input stage. The Common Mode Input
Voltage Range (VCMR) includes ground in singlesupply systems (VSS), but does not include VDD. This
means that the amplifier input behaves linearly as long
as the Common Mode Input Voltage (VCM) is kept
within the specified limits (VSS to VDD – 0.9V at +25°C).
Input voltages that exceed the Absolute Maximum
Voltage Range (VSS – 0.3V to VDD + 0.3V) can cause
excessive current to flow into or out of the input pins.
Current beyond ±2 mA can cause reliability problems.
Applications that exceed this rating must be externally
limited with a resistor, as shown in Figure 4-1.
DC Offsets
C3
R3
MCP61X
V2
R4
Input Current-Limiting
R5
FIGURE 4-2:
Example Circuit for
Calculating DC Offset.
To calculate the DC bias point and DC offset, convert
the circuit to its DC equivalent:
•
•
•
•
•
Replace capacitors with open circuits
Replace inductors with short circuits
Replace AC voltage sources with short circuits
Replace AC current sources with open circuits
Convert DC sources and resistances into their
Thevenin equivalent form
The DC equivalent circuit for Figure 4-2 is shown in
Figure 4-3.
R1
FIGURE 4-1:
Resistor (RIN).
VOUT
R2
V1
REQ
MCP61X
VOUT
VEQ
R5
V EQ = V2 ⋅ -----------------R 4 + R5
R EQ = R 4 || R 5
FIGURE 4-3:
DS21613B-page 12
Equivalent DC Circuit.
© 2005 Microchip Technology Inc.
MCP616/7/8/9
Now calculate the nominal DC bias point with offset:
EQUATION 4-1:
GN = 1 + R2 ⁄ R1
VOOS = GN [VOS + IB ((R1 ||R2 ) – REQ )
– IOS ((R1 ||R2 ) + REQ ) / 2]
VCM = VEQ – (IB + IOS /2) REQ
VOUT = VEQ (GN ) – V1 (GN – 1) + VOOS
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-4) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
Where:
= op amp’s noise gain (from the
non-inverting input to the output)
VOOS = circuit’s output offset voltage
VOS = op amp’s input offset voltage
IB
= op amp’s input bias current
= op amp’s input offset current
IOS
VCM = op amp’s common mode input
voltage
GN
Use the worst-case specs and source values to
determine the worst-case output voltage range and
offset for your design. Make sure the common mode
input voltage range and output voltage range are not
exceeded.
VOUT
CL
FIGURE 4-4:
Output Resistor, RISO
stabilizes large capacitive loads.
Figure 4-5 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
Rail-to-Rail Output
There are two specifications that describe the output
swing capability of the MCP616/7/8/9 family of op
amps. The first specification (Maximum Output Voltage
Swing) defines the absolute maximum swing that can
be achieved under the specified load conditions. For
instance, the output voltage swings to within 15 mV of
the negative rail with a 25 kΩ load tied to VDD/2.
Figure 2-33 shows how the output voltage is limited
when the input goes beyond the linear region of
operation.
The second specification that describes the output
swing capability of these amplifiers is the Linear Output
Voltage Range. This specification defines the
maximum output swing that can be achieved while the
amplifier still operates in its linear region. To verify
linear operation in this range, the large-signal DC
Open-Loop Gain (AOL) is measured at points inside the
supply rails. The measurement must meet the specified
AOL conditions in the specification table.
4.4
VIN
Capacitive Loads
10,000
10k
Recommended RISO (:)
4.3
RISO
MCP61X
1k
1,000
GN = +1
GN t +2
100
100
10n
10p
100p
1n
1.E-11
1.E-10
1.E-09
1.E-08
Normalized Load Capacitance; C L/GN (F)
FIGURE 4-5:
Recommended RISO Values
for Capacitive Loads.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP616/7/8/9 SPICE macro
model are helpful.
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
© 2005 Microchip Technology Inc.
DS21613B-page 13
MCP616/7/8/9
4.5
MCP618 Chip Select (CS)
4.8
PCB Surface Leakage
The MCP618 is a single op amp with Chip Select (CS).
When CS is pulled high, the supply current drops to
50 nA (typ.) and flows through the CS pin to VSS. When
this happens, the amplifier output is put into a highimpedance state. By pulling CS low, the amplifier is
enabled. If the CS pin is left floating, the amplifier may
not operate properly. Figure 1-1 shows the output
voltage and supply current response to a CS pulse.
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP616/7/8/9 family’s bias current at 25°C (1 pA,
typ.).
4.6
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example is shown below in Figure 4-7.
Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It may use a bulk
capacitor (i.e., 1 µF or larger) within 100 mm to provide
large, slow currents. This bulk capacitor is not required
and can be shared with other analog parts.
4.7
Guard Ring
VIN– VIN+
VSS
Unused Op Amps
An unused op amp in a quad package (MCP619)
should be configured as shown in Figure 4-6. Both
circuits prevent the output from toggling and causing
crosstalk. Circuit A can use any reference voltage
between the supplies, provides a buffered DC voltage
and minimizes the supply current draw of the unused
op amp. Circuit B minimizes the number of
components, but may draw a little more supply current
for the unused op amp.
¼ MCP619 (A)
VDD
¼ MCP619 (B)
VDD
VDD
FIGURE 4-6:
DS21613B-page 14
FIGURE 4-7:
for Inverting Gain.
1.
2.
Example Guard Ring Layout
Non-inverting Gain and Unity Gain Buffer:
a) Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b) Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
Inverting Gain and Transimpedance gain (convert current to voltage, such as photo detectors)
amplifiers:
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
Unused Op Amps.
© 2005 Microchip Technology Inc.
MCP616/7/8/9
4.9
4.9.1
4.9.3
Application Circuits
HIGH GAIN PRE-AMPLIFIER
The MCP616/7/8/9 op amps are well suited to
amplifying small signals produced by low-impedance
sources/sensors. The low offset voltage, low offset
current and low noise fit well in this role. Figure 4-8
shows a typical pre-amplifier connected to a lowimpedance source (VS and RS).
RS
VS
10 kΩ
A classic, three-op amp instrumentation amplifier is
illustrated in Figure 4-10. The two-input op amps
provide differential signal gain and a common mode
gain of +1. The output op amp is a difference amplifier,
which converts its input signal from differential to a
single-ended output; it rejects common mode signals at
its input. The gain of this circuit is simply adjusted with
one resistor (RG). The reference voltage (VREF) is
typically referenced to mid-supply (VDD/2) in singlesupply applications.
VOUT
MCP616
RG
RF
11.0 kΩ
100 kΩ
2R ⎞ ⎛ R 4⎞
⎛
V
( V – V ) ⎜1 + ---------2 ⎟ ⎜ ------⎟ + V
OUT =
1
2 ⎝
REF
R ⎠ ⎝ R 3⎠
G
VDD/2
FIGURE 4-8:
High Gain Pre-amplifier.
R3
VOUT
RG
MCP616
R2
VREF
RG
R1
R2
R2
R1
VOUT
½
MCP617
R3
V1
½
MCP617
FIGURE 4-10:
Three-Op Amp
Instrumentation Amplifier.
4.9.4
PRECISION GAIN WITH GOOD
LOAD ISOLATION
The MCP606 is configured as a unity-gain buffer. It
isolates the MCP616’s output from the load, increasing
the high gain stage’s precision. Since the MCP606 has
a higher output current, and the two amplifiers are
housed in separate packages, there is minimal change
in the MCP616’s offset voltage due to loading effect.
½
MCP617
VOUT = V IN (1 + R 2 ⁄ R 1 )
V1
FIGURE 4-9:
Two-Op Amp
Instrumentation Amplifier.
The key specifications that make the MCP616/7/8/9
family appropriate for this application circuit are low
input bias current, low offset voltage and high commonmode rejection.
© 2005 Microchip Technology Inc.
R4
In Figure 4-11, the MCP616 op amp, R1 and R2 provide
a high gain to the input signal (VIN). The MCP616’s low
offset voltage makes this an accurate circuit.
R
2R ⎞
⎛
VOUT = ( V 1 – V 2 ) ⎜1 + ------1 + ---------1- ⎟ + V
REF
R
⎝
2 RG ⎠
VREF
R4
R2
TWO OP AMP INSTRUMENTATION
AMPLIFIER
The two-op amp instrumentation amplifier shown in
Figure 4-9 serves the function of taking the difference
of two input voltages, level-shifting it and gaining it to
the output. This configuration is best suited for higher
gains (i.e., gain > 3 V/V). The reference voltage (VREF)
is typically at mid-supply (VDD/2) in a single-supply
environment.
V2
½
MCP617
V2
For the best noise and offset performance, the source
resistance RS needs to be less than 15 kΩ. The DC
resistances at the inputs are equal to minimize the
offset voltage caused by the input bias currents
(Section 4.2 “DC Offsets”). In this circuit, the DC gain
is 10 V/V, which will give a typical bandwidth of 19 kHz.
4.9.2
THREE OP AMP
INSTRUMENTATION AMPLIFIER
MCP616
VIN
MCP606
VOUT
R1
FIGURE 4-11:
Load Isolation.
R2
Precision Gain with Good
DS21613B-page 15
MCP616/7/8/9
5.0
DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP616/7/8/9 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP616/7/8/9
op amps is available on Microchip’s web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation at room temperature. See the
model file for information on its capabilities.
5.2
FilterLab® Software
Microchip’s FilterLab® software is an innovative tool
that simplifies analog active-filter (using op amps)
design. It is available free of charge from our web site
at www.microchip.com. The FilterLab software tool
provides full schematic diagrams of the filter circuit with
component values. It also outpouts the filter circuit in
SPICE format, which can be used with the macro
model to simulate actual filter performance.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
DS21613B-page 16
© 2005 Microchip Technology Inc.
MCP616/7/8/9
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
MCP616
I/P256
0515
8-Lead SOIC (150 mil)
XXXXXXXX
XXXXYYWW
NNN
8-Lead MSOP
MCP616
I/SN0515
256
YWWNNN
515256
e3
OR
MCP616I
e3 0515
SN^^
256
Example:
616I
*
OR
MCP616
e3 256
I/P ^^
0515
Examples:
XXXXXX
Legend: XX...X
Y
YY
WW
NNN
Note:
Examples:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2005 Microchip Technology Inc.
DS21613B-page 17
MCP616/7/8/9
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP619)
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
14-Lead SOIC (150 mil) (MCP619)
Examples:
MCP619-I/P
XXXXXXXXXXXXXX
0515256
Examples:
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
14-Lead TSSOP (MCP619)
XXXXXXXX
YYWW
NNN
DS21613B-page 18
OR
MCP619
e3
I/P^^
0515256
MCP619ISL
XXXXXXXXXX
0515256
OR
MCP619
e3
I/SL ^^
0515256
Example:
MCP619IST
0515
256
© 2005 Microchip Technology Inc.
MCP616/7/8/9
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
c
§
B1
B
eB
a
b
MIN
.140
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
5
INCHES*
NOM
MAX
8
.100
.155
.130
.170
.145
.313
.250
.373
.130
.012
.058
.018
.370
10
10
.325
.260
.385
.135
.015
.070
.022
.430
15
15
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
MAX
4.32
3.68
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
© 2005 Microchip Technology Inc.
DS21613B-page 19
MCP616/7/8/9
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.146
.189
.010
.019
0
.008
.013
0
0
A1
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.197
.020
.030
8
.010
.020
15
15
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21613B-page 20
© 2005 Microchip Technology Inc.
MCP616/7/8/9
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
B
n
1
α
A2
A
c
φ
A1
(F)
L
β
Units
Dimension Limits
n
p
MIN
INCHES
NOM
MAX
MILLIMETERS*
NOM
8
0.65 BSC
0.75
0.85
0.00
4.90 BSC
3.00 BSC
3.00 BSC
0.40
0.60
0.95 REF
0°
0.08
0.22
5°
5°
-
MIN
8
Number of Pins
.026 BSC
Pitch
A
.043
Overall Height
A2
.030
.033
.037
Molded Package Thickness
A1
.000
.006
Standoff
E
.193 TYP.
Overall Width
E1
.118 BSC
Molded Package Width
D
.118 BSC
Overall Length
L
.016
.024
.031
Foot Length
Footprint (Reference)
F
.037 REF
φ
Foot Angle
0°
8°
c
Lead Thickness
.003
.006
.009
B
.009
.012
.016
Lead Width
α
5°
15°
Mold Draft Angle Top
β
5°
15°
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
MAX
1.10
0.95
0.15
0.80
8°
0.23
0.40
15°
15°
JEDEC Equivalent: MO-187
Drawing No. C04-111
© 2005 Microchip Technology Inc.
DS21613B-page 21
MCP616/7/8/9
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
eB
p
B
Units
Dimension Limits
n
p
MIN
INCHES*
NOM
14
.100
.155
.130
MAX
MILLIMETERS
NOM
14
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
18.80
19.05
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
Molded Package Thickness
A2
.115
.145
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
Molded Package Width
E1
.240
.250
.260
Overall Length
D
.740
.750
.760
Tip to Seating Plane
L
.125
.130
.135
c
Lead Thickness
.008
.012
.015
Upper Lead Width
B1
.045
.058
.070
Lower Lead Width
B
.014
.018
.022
eB
Overall Row Spacing
§
.310
.370
.430
α
Mold Draft Angle Top
5
10
15
β
Mold Draft Angle Bottom
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
DS21613B-page 22
MAX
4.32
3.68
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
15
© 2005 Microchip Technology Inc.
MCP616/7/8/9
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
α
h
45×
c
A2
A
φ
A1
L
β
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.150
.337
.010
.016
0
.008
.014
0
0
INCHES*
NOM
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.347
.020
.050
8
.010
.020
15
15
MILLIMETERS
NOM
14
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
5.99
3.81
3.90
8.56
8.69
0.25
0.38
0.41
0.84
0
4
0.20
0.23
0.36
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
© 2005 Microchip Technology Inc.
DS21613B-page 23
MCP616/7/8/9
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
β
A1
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Molded Package Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
φ
c
B1
α
β
MIN
.033
.002
.246
.169
.193
.020
0
.004
.007
0
0
INCHES
NOM
14
.026
.035
.004
.251
.173
.197
.024
4
.006
.010
5
5
A2
MAX
.043
.037
.006
.256
.177
.201
.028
8
.008
.012
10
10
MILLIMETERS*
NOM
MAX
14
0.65
1.10
0.85
0.90
0.95
0.05
0.10
0.15
6.25
6.38
6.50
4.30
4.40
4.50
4.90
5.00
5.10
0.50
0.60
0.70
0
4
8
0.09
0.15
0.20
0.19
0.25
0.30
0
5
10
0
5
10
MIN
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
DS21613B-page 24
© 2005 Microchip Technology Inc.
MCP616/7/8/9
APPENDIX A:
REVISION HISTORY
Revision B (April 2005)
The following is the list of modifications:
1.
2.
3.
4.
5.
6.
7.
Clarified specifications found in Section 1.0
“Electrical Characteristics”.
Updated Section 2.0 “Typical Performance
Curves” and added input noise current density
plot.
Added Section 3.0 “Pin Descriptions”.
Updated Section 4.0 “Applications Information”.
Updated the SPICE macro model and added
information on the FilterLab software, in
Section 5.0 “Design Tools”.
Corrected package marking information
(Section 6.0 “Packaging Information”).
Added Appendix A: “Revision History”.
Revision A (April 2001)
• Original Release of this Document.
© 2005 Microchip Technology Inc.
DS21613B-page 25
MCP616/7/8/9
NOTES:
DS21613B-page 26
© 2005 Microchip Technology Inc.
MCP616/7/8/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
–X
/XX
Device
Temperature
Range
Package
Device:
MCP616:
MCP616T:
MCP617:
MCP617T:
MCP618:
MCP618T:
MCP619:
MCP619T:
Single Operational Amplifier
Single Operational Amplifier
(Tape and Reel for SOIC, MSOP)
Dual Operational Amplifier
Dual Operational Amplifier
(Tape and Reel for SOIC and MSOP)
Single Operational Amplifier w/Chip Select
(CS)
Single Operational Amplifier w/Chip Select
(CS) (Tape and Reel for SOIC and MSOP)
Quad Operational Amplifier
Quad Operational Amplifier
(Tape and Reel for SOIC and TSSOP)
Temperature Range:
I
= -40°C to +85°C
Package:
MS
P
SN
SL
ST
=
=
=
=
=
Plastic MSOP, 8-lead
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic SOIC (150 mil Body), 8-lead
Plastic SOIC (150 mil Body), 14-lead (MCP619)
Plastic TSSOP (4.4mm Body), 14-lead (MCP619)
© 2005 Microchip Technology Inc.
Examples:
a)
MCP616-I/P:
b)
MCP616-I/SN:
c)
MCP616T-I/SN:
a)
MCP617-I/MS:
b)
MCP617T-I/MS:
c)
MCP617-I/P:
a)
MCP618-I/SN:
b)
MCP618T-I/SN:
c)
MCP618-I/P:
a)
MCP619T-I/SL:
b)
MCP619T-I/ST:
c)
MCP619-I/P:
Industrial Temperature,
8LD PDIP.
Industrial Temperature,
8LD SOIC.
Tape and Reel,
Industrial Temperature,
8LD SOIC.
Industrial Temperature,
8LD MSOP.
Tape and Reel,
Industrial Temperature,
8LD MSOP.
Industrial Temperature,
8LD PDIP.
Industrial Temperature,
8LD SOIC.
Tape and Reel,
Industrial Temperature,
8LD SOIC.
Industrial Temperature,
8LD PDIP.
Tape and Reel,
Industrial Temperature,
14LD SOIC.
Tape and Reel,
Industrial Temperature,
14LD TSSOP.
Industrial Temperature,
14LD PDIP.
DS21613B-page 27
MCP616/7/8/9
NOTES:
DS21613B-page 28
© 2005 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode,
Smart Serial, SmartTel, Total Endurance and WiperLock are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2005 Microchip Technology Inc.
DS21613B-page 29
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
India - Bangalore
Tel: 91-80-2229-0061
Fax: 91-80-2229-0062
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
India - New Delhi
Tel: 91-11-5160-8631
Fax: 91-11-5160-8632
Austria - Weis
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark - Ballerup
Tel: 45-4450-2828
Fax: 45-4485-2829
China - Chengdu
Tel: 86-28-8676-6200
Fax: 86-28-8676-6599
Japan - Kanagawa
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
France - Massy
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Germany - Ismaning
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Alpharetta, GA
Tel: 770-640-0034
Fax: 770-640-0307
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
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Tel: 630-285-0071
Fax: 630-285-0075
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Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
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Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
China - Qingdao
Tel: 86-532-502-7355
Fax: 86-532-502-7205
Malaysia - Penang
Tel:011-604-646-8870
Fax:011-604-646-5086
Philippines - Manila
Tel: 011-632-634-9065
Fax: 011-632-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
England - Berkshire
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Taiwan - Hsinchu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
San Jose
Mountain View, CA
Tel: 650-215-1444
Fax: 650-961-0286
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
04/20/05
DS21613B-page 30
© 2005 Microchip Technology Inc.