Advanced Micro Devices FDDI on Copper with AMD PHY Components by Eugen Gershon Publication # 15923 Rev. Amendment A /0 Issue Date 6/91 1991 Advanced Micro Devices, Inc. FDDI on Copper with AMD PHY Components by Eugen Gershon and pin-out compatible with the MIC device found on one of our demonstration platforms. INTRODUCTION This application note outlines an implementation using AMD PHY components found in either the SUPERNET 1 or SUPERNET 2 families to drive and receive signals over shielded twisted pair media. The circuit described meets the electrical specification of the interoperable solution (PID 16011A) endorsed by AMD, Chipcom, DEC, Motorola, and SynOptics. This interoperable solution (IOS) is designed to minimize the cost of FDDI connections confined within 100 meter range by replacing the optical transceiver and fiber with a shielded twisted pair (STP) transceiver and STP cabling. If a design utilizes AMD’s SUPERNET 1 or SUPERNET 2 chipsets, no major changes are required; only a simple interface circuit from the PHY transmitter to the cable and another interface from the cable to the PHY receiver are necessary. The interface can be implemented at minimal cost and with no more board space requirements than available optical Media Interface Connectors (MICs). We built the circuit described herein using surface mount devices on a small daughter board that was form factor When optical PMD devices are removed from the board, the signals at their interface to the system should be kept intact, both in logical content and as voltage/current levels – see Figure 1. The optical transmitter accepts both “Serial Data Out” from the PHY transmitter and “Output Disable” control (not used in IOS), at P-ECL levels. Similarly, the optical receiver supplies “Serial Data In” to the PHY receiver and “Carrier Detect” status (here called “Link Detect”) at the same P-ECL levels. One new signal handled by the copper interface circuit is a status signal, incorporated into Link Detect, that shows that the cable is connected at both ends. It is detected by both transmitter and receiver because each one uses a separate twisted pair. This solution is designed to work on STP cable, 150 ohm, Type 1 or 2. It specifies a maximum FDDI signal attenuation of 12 dB (a factor of 4) at 100 meters. STP Z0 = 150 Ω Serial D A T A Data PHY Transmitter “T” Copper Interface Out I N Connection Detected AND Link Detect Connection Detected Sufficient Power Level (”Signal Detect”) Serial D A T A Data PHY Receiver O U T “R” Copper Interface In STP Z0 = 150 Ω 15923A-001A Figure 1. Block Diagram Publication # 15923 Rev. Amendment A /0 Issue Date 6/91 1991 Advanced Micro Devices, Inc. 1 FDDI on Copper with AMD PHY Components The transmit waveform going to the cable is required to meet a template based on a differential P-ECL output waveform, such as at the PDT (ENDEC) outputs. This means that AMD parts can be used to drive the STP cable directly (source terminations should be added as required by the IOS specifications). Also, the attenuated signal coming out of the cable at the receiver end is sufficient to allow clock and data recovery by the PDR (EDS) without any need for amplification. Transmitter Interface The main coupling component to the cable is a transformer, which should be designed for the speed (rise and fall time) and the frequency spectrum of the FDDI signal. Figure 2 shows the data path. The transformer shown is a 1:1 transformer with center taps made by Pulse Engineering, Inc. R1 and R2 are biasing resistors for the output driver stage inside the PDT (ENDEC). The output voltages are roughly 3 volts for “LOW” and 4 volts for “HIGH”, therefore the resistor values can be calculated from the average DC current: 3.5 V/R1 = 10 to 20 mA. R3 and R4 combined with the output impedance of the driver and with the transformer series impedance form the cable termination (150 ohms) at the transmitter end. R3 and R4 will reduce the output signal to the cable by a factor of two. The PDT output driver sees a differential impedance of about 300 ohms in parallel with the 540 ohm biasing resistors. This requires less than its full driving capability of 100 ohms differential. IOS specifies no precompensation at the transmitter end in order to minimize high frequency power levels in the transmitted signal spectrum, which improves the FCC-related performance. Receiver Interface The main coupling component at the receiver end is also the transformer. Figure 3 shows the data path. R4, R5 and R6 are bias resistors to bring the input stage of the PDR (EDS) to its DC operating point of about 3.5 volts. R5 provides a small offset voltage between RX and RY to keep the inputs (and outputs) stable in the absence of a carrier. The bias voltage level is isolated from the transformer secondary by C3 and C4. It is also possible to include the transformer in the DC path in order to avoid the need for capacitors C3 and C4. In this case a two-transformer option is a better choice. The R1, R2 and R3//R5 combination, and the parallel loading of Link Detect (not shown) give the proper cable termination at the receiver end (150 ohms). R1 and R2 with their parallel capacitors C1 and C2 form a high-pass filter that compensates for the high-frequency attenuation and phase shift in the cable. There are many possible correct schemes for compensation. AMD’s parts can run a 100 meter link without compensation in most cases, provided the signal is not deteriorated by low performance transformers or external noise. However, in the interest of providing a robust implementation over the IOS specification, compensation has been included. R3 68 Ω TY Am79865 Physical Data Transmitter (PDT) TX T1 FTP 4.0 R1 270 Ω STP 150 Ω R4 68 Ω R2 270 Ω Either one 1:1 transformer with center taps (as shown), or two simple 1:1 transformers 15923A-002A Figure 2. Transmitter Interface for Data Out 2 FDDI on Copper with AMD PHY Components Cable Continuity Detection As mentioned before IOS requires a DC path to check cable connection between two (“master” and “slave”) stations. The cable continuity signal is one part of “Link Detect” status, which is comprised of both cable continuity and minimum signal level. C1 150 p T1 FTP 4.0 R1 75 Ω C3 1µ R3 10 KΩ STP 150 Ω R4 30 KΩ R2 75 Ω C2 150 p RY R5 150 Ω RX C4 1µ R6 6 KΩ Either one 1:1 transformer with center taps (as shown), or two simple 1:1 transformers Am79866 Physical Data Receiver (PDR) +5 V 15923A-003A Figure 3. Receive Interface for Data In Figure 4 shows the required DC path for which there are two interoperable options. The simpler of the two solutions (shown) reports continuity if at least one of the wires in the twisted pair is connected. The second option requires both wires to be connected in order to report continuity, but its implementation uses more components. For example, the second option requires two transformers at each twisted pair end and cannot be implemented with one center-tapped transformer. Both implementation options are shown in the IOS document, Appendix 1. The S-port cable continuity test will signal a “high” at the emitter output or a “low” at the collector output when the cable is connected. An M-port needs to check that the voltage across the resistor is within a “window”. A low voltage indicates no connection; a high voltage indicates a loop-back condition. In both cases cable continuity signal is “false.” Signal Level Detection The circuit for input signal level detection is based on a fast comparator. In Figures 5 and 6 the comparator is built from a 4 transistor amplifier and a peak detector. In Figure 7, a fast IC comparator is used. Other implementations are shown in the IOS document. If the input signal level is 50 mV or more peak-to-peak, and the cable is connected, the output level of Link Detect goes to “high” (4 volts). 3 FDDI on Copper with AMD PHY Components M-PORT R3 68 Ω S-PORT +5 V C1 150 p T1 FTP 4.0 T1 FTP 4.0 R1 75 Ω R1 270 Ω TRANSMIT RECEIVE R2 75 Ω R4 68 Ω R2 270 Ω Optocoupler C1 150 p T1 FTP 4.0 T1 FTP 4.0 R1 75 Ω R3 68 Ω R1 270 Ω RECEIVE TRANSMIT R4 68 Ω R2 75 Ω C2 150 p C2 150 p R2 270 Ω Vmax Vmin 15923A-004A Window Comparator Figure 4. The Simple Option for Cable Continuity Detection Lay-Out During the time we have been experimenting with the copper interface, it has become apparent that one major source of problems is the computer noise coupled into the transmitted and received signals. Little serial inductors were added to the serial lines that come from the PDT or ENDEC (TX, TY), and go to the PDR or EDS (RX, RY), to filter high frequency components that do not belong to the FDDI signal. The protoypes we have built for preliminary testing were based on FASTcards (ENDEC and EDS). The whole in- 4 terface circuit, including data path, bias resistors and Link Detect, was plugged into the ODL footprint. The newer generation of FASTcards based on PDT/Rs will use exactly the same interface. Detailed schematics of an S-port and an M-port are shown in Figures 5 and 6 respectively. Since FCC compliance is dependent on both the circuit characteristics and the system lay-out and configuration, test results will vary from implementation to implementation. However, the circuit includes noise suppressing elements to minimize EMI. FDDI on Copper with AMD PHY Components S-PORT C1 150 p R3 C2 10 KΩ 150 p RECEIVE L1 0.15 µH C3 1µ R1 75 Ω T1 FTP 4.0 L3 1.5 µH R5 30 KΩ R4 10 KΩ Am79866 Physical Data Receiver (PDR) RY R6 150 Ω RX C4 1µ R2 75 Ω L5 0.15 µH L2 0.15 µH R7 6 KΩ L4 1.5 µH +5 V L6 0.15 µH +5 V R8 300 Ω L7 2.5 µH R9 3 KΩ R17 150 Ω R15 2 KΩ R13 3 KΩ R12 150 Ω R30 500 Ω Q3 Q1 Q2 Q4 C6 1µ C5 1µ R16 3 KΩ R10 2 KΩ Signal Level Detected C8 1µ R18 300 Ω R31 4 KΩ R19 1 KΩ D1 1N6263 C9 1µ R20 10 KΩ R14 2 KΩ R11 75 Ω L8 1.5 µH +5 V 1 4N32 2 R21 250 Ω Q1, Q2, Q4: 2N2369 or PN2369 or equivalent Q3: 2N3639, PN3639, 2N3546 or equivalent 5 4 R22 400 Ω Cable Continuity Detected LINK DETECT R24 600 Ω R23 1 KΩ T2 FTP 4.0 R26 68 Ω L10 0.15 µH TY TX TRANSMIT R27 68 Ω L11 0.15 µH R29 270 Ω Am79865 Physical Data Transmitter (PDT) R28 270 Ω 15923A-005A Figure 5. Schematic For the S-Port 5 FDDI on Copper with AMD PHY Components M-PORT T1 C3 1µ R1 75 Ω FTP 4.0 C1 150 p R3 C2 10 KΩ 150 p RECEIVE L3 1.5 µH R5 30 KΩ L1 0.15 µH R4 10 KΩ Am79866 Physical Data Receiver (PDR) RY R6 150 Ω RX R2 75 Ω C4 1µ R7 6 KΩ +5 V L4 1.5 µH L2 0.15 µH L6 0.15 µH L5 0.15 µH +5 V R8 300 Ω L7 2.5 µH R17 150 Ω R15 2 KΩ R13 3 KΩ R12 150 Ω R9 3 KΩ R30 500 Ω Q3 Q2 Q1 L8 1.5 µH C7 1µ C5 1µ R31 4 KΩ R19 1 KΩ D1 1N6263 U1 LM393 or LM2311 + Q1, Q2, Q4: 2N2369 or PN2369 or equivalent Q3: 2N3639, PN3639, 2N3546 or equivalent LINK DETECT +5 V R24 600 Ω – R23 4 KΩ R22 400 Ω Cable Continuity Detected L9 1.5 µH R25 100 Ω T2 FTP 4.0 R26 68 Ω L10 0.15 µH TY TX TRANSMIT R27 68 Ω L11 0.15 µH R28 270 Ω R29 270 Ω Am79865 Physical Data Transmitter (PDT) 15923A-006A Figure 6. Schematic For the M-Port 6 C9 1µ R36 1 KΩ + R33 3.5 KΩ – R35 1.5 KΩ R18 300 Ω +5 V R32 1.5 KΩ R21 650 Ω R16 3 KΩ R11 75Ω +5 V R34 3.5 KΩ Signal Level Detected C8 1µ R14 2 KΩ R10 2 KΩ +5 V Q4 C6 1µ R20 10 KΩ FDDI on Copper with AMD PHY Components S-PORT T1 FTP 4.0 L1 0.15 µH C3 1 µ R1 75 Ω C1 150 p R3 C2 10 KΩ 150 p RECEIVE R4 10 KΩ R2 75 Ω C4 1µ L5 0.15 µH L3 1.5 µH R5 30 KΩ Am79866 Physical Data Receiver (PDR) RY R6 150 Ω RX R7 6 KΩ L4 1.5 µH L2 0.15 µH +5V L6 0.15 µH +5 V R8 300 Ω L7 2.5 µH R10 20 KΩ +5 V U1 L8 1.5 µH R9 10 KΩ C5 1µ R13 500 Ω – R11 500 Ω +5 V LM361 + Signal Level Detected STROBE C6 1µ 1 R14 250 Ω 4 –5 V R12 30 KΩ 5 4N32 2 +5 V U2 D1 1N6263 Cable Continuity Detected LINK DETECT R15 1 KΩ C7 10 n T2 FTP 4.0 R16 50 KΩ R17 68 Ω L9 0.15 µH TRANSMIT TY TX R18 68 Ω L10 0.15 µH R19 270 Ω R20 270 Ω Am79865 Physical Data Transmitter (PDT) 15923A-007A Figure 7. Alternative Schematic For the S-Port Using a Fast Comparator For Signal Detect 7