19-0524; Rev 1; 8/06 Multiple-Output Clock Generators with Dual PLLs and OTP The MAX9471/MAX9472 multipurpose clock generators are ideal for consumer and communication applications. The MAX9471/MAX9472 feature two buffered phase-locked loop (PLL) outputs that can be independently set from 4MHz to 200MHz. These devices also provide one (MAX9472) or two (MAX9471) buffered outputs of the reference clock. The MAX9471 outputs a set of MPEG/AC3 audio and video frequencies most commonly used in consumer applications. The MAX9472 outputs a set of common audio frequencies. These frequencies are selected through an I2C† interface (MAX9471) or by setting the three-level FS pins. The MAX9471/MAX9472 feature a one-time-programmable (OTP) ROM, allowing one-time programming of the two PLL outputs. The MAX9471/MAX9472 include two basic configurations. In one configuration, the OTP ROM sets PLL1 output to any frequency between 4MHz to 200MHz, and the I2C interface (MAX9471) or programmable pins set the PLL2 output frequency to a set of audio and video frequencies. In the other configuration, the OTP ROM sets both PLL1 and PLL2 frequencies to fixed values between 4MHz to 200MHz. In both cases, the reference output is available, but the OTP ROM can disable it. The OTP ROM on the MAX9471/MAX9472 is factory set based on the customer requirements. Contact the factory for samples with preferred frequencies. The devices operate from a 3.3V supply and are specified over the -40°C to +85°C extended temperature range. The MAX9471 is available in a 20-pin TQFN package. The MAX9472 is available in a 14-pin TSSOP package. Features ♦ 5MHz to 50MHz Input Clock Reference ♦ Crystal or Input-Clock-Based Reference ♦ Two Fractional-N Feedback PLLs (4MHz to 200MHz) with Buffered Outputs ♦ Two Buffered Outputs of Reference Clock ♦ OTP for Factory-Preset PLL Frequencies Available (Contact Factory) ♦ Programmable Through I2C Interface or ThreeLevel Logic Pins for Video or Audio Clocks ♦ Low-RMS Jitter PLL (14ps for 45MHz) ♦ Integrated VCXO with ±200ppm Tuning Range ♦ Available in 20-Pin TQFN and 14-Pin TSSOP Packages ♦ +3.3V Supply ♦ -40°C to +85°C Temperature Range Ordering Information PINPACKAGE PKG CODE PART TEMP RANGE MAX9471ETP+** -40°C to +85°C 20 TQFN-EP* T2055-5 MAX9472EUD+** -40°C to +85°C 14 TSSOP U14-2 *EP = Exposed pad. **Marking is for samples only. Contact factory for ordering information. +Denotes lead-free package. Pin Configurations Data Networking Systems FS2 VDD VDD GND 14 13 12 11 Communication Systems PD TOP VIEW Digital TVs 15 Applications VDD 16 10 GND Set-Top Boxes X2 17 9 I.C. Home Entertainment Centers X1 18 8 CLK4 FSO/SCL 19 7 CLK3 20 6 CLK2 2 3 4 5 AGND GND CLK1 + VDDA †Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 1 FS1/SDA TUNE Multimedia PCs MAX9471 TQFN (5mm x 5mm) Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9471/MAX9472 General Description MAX9471/MAX9472 Multiple-Output Clock Generators with Dual PLLs and OTP ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................-0.3V to +4.0V VDDA to AGND ......................................................-0.3V to +4.0V AGND to GND ......................................................-0.3V to +0.3V All Other Pins to GND ..................................-0.3V to VDD + 0.3V Short-Circuit Duration (all LVCMOS outputs)..............................................Continuous ESD Protection (Human Body Model)..................................±2kV Continuous Power Dissipation (TA = +70°C) 20-Pin TQFN (derate 21.3mW/°C above +70°C) .......2758mW 14-Pin TSSOP (derate 9.1mW/°C above +70°C) ......796.8mW Storage Temperature Range .............................-65°C to +150°C Maximum Junction Temperature .....................................+150°C Operating Temperature Range ...........................-40°C to +85°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VDD = VDDA = +3.0V to +3.6V and TA = -40°C to +85°C. Typical values at VDD = VDDA = 3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2.0 VDD V 0 0.8 V 20 µA LVCMOS INPUTS (PD, X1 as a reference INPUT CLK) Input High Level VIH1 Input Low Level VIL1 Input Current High Level IIH1 VIN = VDD Input Current Low Level IIL1 VIN = 0 -20 µA THREE-LEVEL INPUTS (FS0, FS1, FS2, as FS2 = open) Input High Level VIH2 Input Low Level VIL2 Input Open Level Input Current 2.5 VIO2 IIL2, IIH2 V 0.8 VIL2 = 0 or VIH2 = VDD V 1.27 2.10 V -10 +10 µA SERIAL INTERFACE (SCL, SDA) (Note 2) (MAX9471) Input High Level VIH Input Low Level VIL Input-Leakage Current 0.7 x VDD IIH, IIL Low-Level Output VOL Input Capacitance CI V -1 ISINK = 4mA 0.3 x VDD V +1 µA 0.4 (Note 3) 8.4 V pF CLOCK OUTPUTS (CLK_) Output High Level VOH IOH = -4mA Output Low Level VOL IOL = 4mA VDD 0.6 V 0.4 V POWER SUPPLIES Digital Power-Supply Voltage VDD 3.0 3.6 V Analog Power-Supply Voltage VDDA 3.0 3.6 V Total Current for Digital and Analog Supplies IDC CLK1 at 125MHz and CLK2 at 74.1758MHz; all outputs not loaded 12 mA Total Power-Down Current IPD PD = low 60 µA 2 _______________________________________________________________________________________ Multiple-Output Clock Generators with Dual PLLs and OTP (VDD = VDDA = +3.0V to +3.6V, TA = -40°C to +25°C. Typical values are at VDD = VDDA = 3.3V, TA = +25°C with fXTL = 27MHz, unless otherwise noted.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS OUTPUT CLOCKS (CLK1, CLK2) Minimum Frequency Range fOUT fIN = 5MHz to 50MHz Maximum Frequency Range fOUT fIN = 5MHz to 50MHz, CL < 5pF Clock Rise Time tR Clock Fall Time tF Duty Cycle 4 MHz 200 MHz 20% to 80% of VDD, CL = 10pF, fOUT = 74.1758MHz (Figure 5) 1.4 ns 80% to 20% of VDD, CL = 10pF, fOUT = 74.1758MHz (Figure 5) 1.2 ns fOUT = 74.1758MHz, CL = 10pF 133 42 50 125MHz, CL = 5pF, fIN = 27MHz 26.3 74.1758MHz, CL = 10pF, fIN = 27MHz 33.6 58 % Output Period Jitter JP RMSps Soft Power-On Time tFST SDA from low to high, fOUT = 71.1758MHz, fIN = 13MHz (Figure 6) 1 ms Hard Power-On Time tPO1 (Figure 6) 15 ms 27 MHz VCXO CLOCKS (CLK3, CLK4) Crystal Frequency fXTL Crystal Accuracy ±30 Tuning Voltage Range VTUNE VCXO Tuning Range TUNE Input Impedance 0.0 VTUNE = 0 to 3V, C1 = C2 = 4.0pF ±150 ZTUNE Output CLK Accuracy VTUNE = 1.5V, C1 = C2 = 4.0pF Output Duty Cycle CL = 10pF load, CLK3 40 ppm 3.0 ±200 V ppm 95 kΩ ±50 ppm 50 60 % Output Period Jitter CL = 10pF 36 RMSps Output Rise Time tR 20% to 80% of VDD (Figure 5), CL = 10pF 1.4 ns Output Fall Time tF 80% to 20% of VDD (Figure 5), CL = 10pF 1.4 ns _______________________________________________________________________________________ 3 MAX9471/MAX9472 AC ELECTRICAL CHARACTERISTICS MAX9471/MAX9472 Multiple-Output Clock Generators with Dual PLLs and OTP SERIAL-INTERFACE TIMING CHARACTERISTICS (MAX9471) (VDD = VDDA = +3.3V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1, Figure 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz Serial Clock fSCL Bus Free Time Between STOP and START Conditions tBUF 1.3 µs Hold Time, Repeated START Condition tHD,STA 0.6 µs Repeated START Condition Setup Time tSU,STA 0.6 µs STOP Condition Setup Time tSU,STO Data Hold Time tHD,DAT Data Setup Time 0.6 (Note 4) 15 µs 900 ns tSU,DAT 100 ns SCL Clock Low Period tLOW 1.3 µs SCL Clock High Period tHIGH 0.7 µs Rise Time of SDA and SCL, Receiving tR (Notes 3, 5) 20 + 0.1Cb 300 ns Fall Time of SDA and SCL, Receiving tF (Notes 3, 5) 20 + 0.1Cb 300 ns tF,TX (Notes 3, 6) 20 + 0.1Cb 250 ns Pulse Width of Spike Suppressed tSP (Notes 3, 7) 0 50 ns Capacitive Load for Each Bus Line Cb (Note 3) 400 pF Fall Time of SDA, Transmitting Note 1: All parameters are tested at TA = +25°C. Specifications over temperature are guaranteed by design. Note 2: No high-output level is specified, only the output resistance to the bus. Pullup resistors on the bus provide the high-level voltage. Note 3: Guaranteed by design. Note 4: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCL’s falling edge. Note 5: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 x VDD and 0.7 x VDD. Note 6: Bus sink current is less than 6mA. Cb is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 x VDD and 0.7 x VDD. Note 7: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. 4 _______________________________________________________________________________________ Multiple-Output Clock Generators with Dual PLLs and OTP (VDD = VDDA = +3.3V, TA = +25°C, fXTL = 27MHz, unless otherwise noted.) RISE TIME (ns) 12 8 0 1.0 -15 10 35 60 85 1.4 1.0 0.6 0.2 0.2 -40 -15 10 35 60 85 -40 -15 10 35 TEMPERATURE (°C) JITTER vs. TEMPERATURE 33MHz OUTPUT 66MHz OUTPUT CL = 10pF fXTAL = 27MHz 60 85 2.5 3.0 MAX9471/2 toc06 TEMPERATURE (°C) MAX9471/2 toc05 TEMPERATURE (°C) MAX9471/2 toc04 -40 35 1.4 CL = 10pF fXTAL = 27MHz fCLK1 = 66MHz 1.8 0.6 4 40 CL = 10pF fXTAL = 27MHz fCLK1 = 66MHz MAX9471/2 toc03 1.8 FALL TIME vs. TEMPERATURE 2.2 FALL TIME (ns) MAX9471/2 toc01 fCLK1 = 125MHz fCLK2 = 74.1758MHz 16 SUPPLY CURRENT (mA) RISE TIME vs. TEMPERATURE 2.2 MAX9471/2 toc02 SUPPLY CURRENT vs. TEMPERATURE 20 JITTER (ps) 30 25 CLK1 1V/div fCLK1 = 33MHz 20 CLK1 1V/div 15 10 5 fCLK1 = 66MHz 0 -40 -15 10 35 60 10ns/div 10ns/div DUTY CYCLE vs. TEMPERATURE VCXO TUNING RANGE vs. VCXO ACCURACY 85 53 DUTY CYCLE (%) CLK1 1V/div CL = 10pF fXTAL = 27MHz 51 fCLK1 = 33MHz 49 47 fCLK1 = 66MHz fIN = 27MHz fOUT = 45MHz 200 4pF 5pF 100 6pF 0 -100 -200 -300 45 4ns/div 300 MAX9741/2 toc09 MAX9471/2 toc07 55 VCXO ACCURACY (PPM) 125MHz CLK OUTPUT MAX9471/2 toc08 TEMPERATURE (°C) -40 -15 10 35 TEMPERATURE (°C) 60 85 0 0.5 1.0 1.5 2.0 VCXO TUNING RANGE (V) _______________________________________________________________________________________ 5 MAX9471/MAX9472 Typical Operating Characteristics Multiple-Output Clock Generators with Dual PLLs and OTP MAX9471/MAX9472 Typical Operating Circuit/Block Diagram +3.3V +3.3V 0.1µF x 3 0.1µF VDD VDDA* MAX9471 MAX9472 X1 C1 27MHz VDD VDD* VCXO C2 X2 PLL1 CLK1 TUNE FS0/SCL SERIAL INTERFACE FS1/SDA PLL2 CLK2 FS2* CLK3 AGND* CLK4* GND OTP *MAX9471 ONLY. Pin Description PIN MAX9471 6 MAX9472 NAME FUNCTION 1 5 TUNE VCXO Tune Voltage Input. If using a reference clock input, connect TUNE to VDD. 2 — VDDA Analog Power Supply. Bypass to GND with a 0.1µF capacitor. 3 — AGND 4, 10, 11 6, 10, 11 GND Ground Analog Ground 5 7 CLK1 Output Clock 1. PLL1 buffered output. 6 8 CLK2 Output Clock 2. PLL2 buffered output. 7 9 CLK3 Output Clock 3. VCXO buffered output. 8 — CLK4 Output Clock 4. VCXO buffered output. 9 — I.C. Internally Connected. Leave unconnected. 12, 13, 16 4, 12 VDD Power Supply. Bypass to GND with a 0.1µF capacitor. 14 — FS2 Function Select 2 15 13 PD Active-Low, Power-Down Input. Pull high for normal operation, drive PD low to place MAX9471/MAX9472 in power-down mode. 17 14 X2 Crystal Connection 2. Leave open if using a reference clock. 18 1 X1 19 — FS0/SCL Function Select 0/Serial Clock. Set FS2 high to place the device in I2C mode (see Table 1). Crystal Connection 1 or Reference Clock Input 20 — FS1/SDA Function Select 1/Serial Data. Set FS2 high to place the device in I2C mode (see Table 1). — 2 FS1 — 3 FS0 Function Select 0 EP — EP Exposed Pad (MAX9471 only). Connect EP to GND. Function Select 1 _______________________________________________________________________________________ Multiple-Output Clock Generators with Dual PLLs and OTP The MAX9471/MAX9472 have two programmable fractional-N feedback PLLs so that almost any frequencies between 4MHz to 200MHz can be generated. The MAX9471 provides four outputs: two for the PLLs and two for the reference clock. The MAX9472 provides three outputs: two for the PLLs and one for the reference clock. The crystal frequency can be between 5MHz and 30MHz. The internal VCXO has a fine-tuning range of ±200ppm. Power-Down Driving PD low places the MAX9471/MAX9472 in power-down mode. PD overrides all other functions, setting all outputs to high impedance and shutting down the two PLLs. Every output has an 80kΩ (typ) internal pulldown resistor. Voltage-Controlled Crystal Oscillator (VCXO) The MAX9471/MAX9472s’ internal VCXO produces a reference clock for the PLLs used to generate the output clocks. The oscillator uses a crystal clock as the base frequency reference and has a voltage-controlled tuning input for micro adjustment in a range of ±200ppm. The tuning voltage VTUNE can vary from 0V to 3V as shown in Figure 1. The crystal should be AT cut and oscillate on its fundamental mode with ±30ppm accuracy. The crystal shunt capacitor should be less than 10pF, including board parasitic capacitance. To achieve up to ±200ppm pullability, the crystal-loading capacitance should be less than 14pF. The VCXO is a free-running oscillator. It starts oscillating with an internal POR signal and can be disabled by PD. VCXO settles at approximately 5ms at power-on and 10µs at a change of the VTUNE voltage. Choosing different C1 and C2 capacitors allows flexibility for centering the various crystals. See theTypical Operating Characteristics for an example. To use the MAX9471/MAX9472 as a synthesizer with an input reference clock, connect the input clock to X1 and TUNE to VDD, and leave X2 unconnected. This configuration is for applications where the micro tuning is not needed, and there is a system reference clock available. One-Time Programmable Memory The MAX9471/MAX9472 feature a factory-configurable, OTP memory for nonvolatile applications allowing for simple and permanent clock generation. Contact the factory for presetting the MAX9471/MAX9472 to requested frequencies. Using OTP, the MAX9471/MAX9472 can be configured to two different configurations. One configuration is to have PLL1 set to any frequency between 4MHz to 200MHz and select the PLL2’s frequency by I 2 C (MAX9471) or programmable pins. The second configuration is to preset the frequencies in PLL1 and PLL2 to fixed values between 4MHz to 200MHz. In both cases, the reference output is available, but it can be disabled by OTP. At power-up, all the outputs are enabled. Frequency Selection of CLK2 Output The OTP ROM can set PLL2’s output to be selectable from a group of frequencies that are common for MPEG video and audio applications. The frequency selection can be done by the FS_ inputs or through the I2C interface (MAX9471). For the MAX9471, pull FS2 high (Table 1) to select the PLL2 frequency through the I2C interface. Otherwise, the frequencies are selected according to Table 2. For the MAX9471, Table 3 shows the mappings for I2C programming. Serial Interface (MAX9471) The MAX9471 can be programmed through a 2-wire, I2C-compatible serial interface. The device is activated after power-up and FS2 = high. The device operates as a slave that sends and receives data through clock line SCL and data line SDA for bidirectional communication with the master. A master (typically a microcontroller) initiates all data transfers to and from the MAX9471 and 27.0054 VCXO OUTPUT FREQUENCY (MHz) +200ppm 27.00 Table 1. Mode Selection by FS2 (MAX9471 Only) -200ppm 26.9946 0 3V VTUNE FS2 MODE Low or open Pin programmable High I2C enabled Figure 1. VCXO Tuning Range for a 27MHz Crystal _______________________________________________________________________________________ 7 MAX9471/MAX9472 Detailed Description MAX9471/MAX9472 Multiple-Output Clock Generators with Dual PLLs and OTP Table 3. MAX9471 I2C Frequency Selection at CLK2 (FS2 = High) Table 2. MAX9471/MAX9472 Frequency Selection at CLK2 FS2 FS1 FS0 A4 FREQUENCY (MHz) A3 A2 A1 FREQUENCY (MHz) AUDIO FREQUENCIES AUDIO FREQUENCIES Open Open Open 4.096 0 0 0 0 4.096 Open Open Low 6.144 0 0 0 1 6.144 Open Open High 8.1920 0 0 1 0 8.1920 Open Low High 11.2896 0 0 1 1 11.2896 Open Low Open 12.2880 0 1 0 0 12.2880 Open Low Low 16.3840 0 1 0 1 16.3840 Open High High 22.5792 0 1 1 0 22.5792 Open High Open 24.5760 0 1 1 1 24.5760 Open High Low 9.216 1 0 0 0 9.216 Low Open High 16.9344 1 0 0 1 16.9344 Low Open Open 18.4320 1 0 1 0 18.4320 Low Open Low 33.8688 1 0 1 1 33.8688 Low High High 36.864 1 1 74.1758241 1 1 VIDEO FREQUENCIES Low Low Low 0 0 VIDEO FREQUENCIES 0 1 36.864 74.1758241 Low Low High 74.25 1 1 1 0 74.25 Low Low Open 54.054 1 1 1 1 54.054 High X X Disable three-level pins and enable I2C *MAX9472 can be programmed to FS2 = open settings only. SDA tSU, DAT tBUF tSU, STA tLOW tHD, STA tHD, DAT tSU, STO SCL tHIGH tHD, STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION Figure 2. I 2C Timing Diagram generates the SCL clock that synchronizes the data transfer. The SDA line operates as both an input and an open-drain output. A pullup resistor, typically 4.7kΩ, is required on SDA. The SCL line operates only as an 8 input. A pullup resistor, typically 4.7kΩ, is required on SCL if there are multiple masters on the 2-wire bus, or if the master in a single-master system has an open-drain SCL output. Figure 2 is the I2C timing diagram. _______________________________________________________________________________________ Multiple-Output Clock Generators with Dual PLLs and OTP START and STOP Conditions Both SCL and SDA remain high when the interface is not busy. The active master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission (Figure 3). SDA SCL S P START CONDITION STOP CONDITION Figure 3. START and STOP Diagram MASTER-WRITE DATA STRUCTURE S SLAVE ADDRESS W A A DATA AA P DATA AA P MASTER-READ DATA STRUCTURE S SLAVE ADDRESS MASTER TRANSFERS TO SLAVE R A A A = ACK; A = 0: SUCCESSFUL, A = 1: UNSUCCESSFUL S = START CONDITION P = STOP CONDITION SLAVE TRANSFERS TO MASTER Figure 4. Serial-Interface Data Structure _______________________________________________________________________________________ 9 MAX9471/MAX9472 Data Transfer and ACK Following the START condition, each SCL clock pulse transfers 1 bit. Between a START and a STOP, multiple bits are transferred on the 2-wire bus. The first 7 bits are for the device address. Bit 8 indicates the writing (low) or reading (high) operation (R/W). Bit 9 is the ACK for the address and operation type. The next 8 bits (bit 10 to bit 17) form the content byte. The next bit, bit 18, is the ACK for the content byte. The master always transfers the first 8 bits (address + R/W). The slave (MAX9471) may receive a content byte from the bus or transfer a content byte to the bus. The ACK bits are transmitted by the address or content recipient. A lowACK bit indicates a successful transfer; otherwise, a high-ACK bit indicates an unsuccessful transfer. More content bytes can be continuously transferred until the master sends a STOP. For the MAX9471 data writing, after the 9 bits with the slave ID, R/W, and ACK, 1 data byte is sent to the MAX9471 from the master. Figure 4 shows the structure of the data transfer. Figure 5 shows CLK_ rise and fall times. Device Address The default I2C address for the MAX9471 is factory set to 1100111. Contact factory for different addresses. MAX9471/MAX9472 Multiple-Output Clock Generators with Dual PLLs and OTP tF tR 80% CLK_ 20% 80% 20% RISE AND FALL TIME MEASURES BETWEEN 20% AND 80%. Figure 5. CLK_ Rise and Fall Times VDD 2.2V t STOP PULSE AFTER WRITING STOP EDGE SDA (MAX9471) CLK1 OR CLK2 tPO1 tFST CLK3 OR CLK4 tPO2 Figure 6. VCXO and PLL Timing Diagram 10 ______________________________________________________________________________________ Multiple-Output Clock Generators with Dual PLLs and OTP Pin Configurations (continued) Crystal Selection When using a crystal with the MAX9471/MAX9472s’ internal oscillator, connect the crystal to X1 and X2. Choose an AT-cut crystal that oscillates on its fundamental mode with ±30ppm and loading capacitance less than 14pF. To achieve a wide VCXO tuning range, select a crystal with motional capacitance greater than 7fF and connect 6pF or less shunt capacitors at X1 and X2 to ground. When the VCXO is used as an oscillator, select both shunt capacitors to be approximately 13pF. The optimal shunt capacitors for achieving minimum frequency offset can be determined experimentally. TOP VIEW X1 1 14 X2 FS1 2 13 PD FS0 3 12 VDD VDD 4 MAX9472 TUNE 5 11 GND 10 GND GND 6 9 CLK3 CLK1 7 8 CLK2 TSSOP Board Layout Considerations and Bypassing The MAX9471/MAX9472s’ oscillator frequencies make proper layout important to ensure stability. For best performance, place components as close as possible to the device. + Chip Information PROCESS: CMOS Digital or AC transient signals on GND can create noise at the clock output. Return GND to the highest quality ground available. Bypass each VDD and VDDA with a 0.1µF capacitor, placed as close as possible to the device. Careful PC board ground layout minimizes crosstalk between the outputs and digital inputs. ______________________________________________________________________________________ 11 MAX9471/MAX9472 Applications Information Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QFN THIN.EPS MAX9471/MAX9472 Multiple-Output Clock Generators with Dual PLLs and OTP 12 ______________________________________________________________________________________ Multiple-Output Clock Generators with Dual PLLs and OTP TSSOP4.40mm.EPS PACKAGE OUTLINE, TSSOP 4.40mm BODY 21-0066 G 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2006 Maxim Integrated Products Springer is a registered trademark of Maxim Integrated Products, Inc. MAX9471/MAX9472 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)