19-3683; Rev 0; 5/05 Multiple-Output Clock Generator with Spread Spectrum The MAX9492 frequency synthesizer is designed to generate multiple clocks for clock distribution in network routers or switches. The device provides a total of six buffered clock outputs (CLK1 to CLK6). CLK1 is the buffered output of the reference clock. CLK2 through CLK6 are independently programmable to generate eight different frequencies based on a 25MHz input crystal: 133, 125, 83, 66, 62.5, 50, 33, and 25MHz. All the outputs are LVCMOS single-ended signals. Either a 25MHz crystal or an external clock can serve as the input reference clock. The MAX9492 incorporates two phase-locked loops (PLLs) with two internal loop filters. Select the MAX9492’s output clock frequency by programming on-chip registers through the MAX9492’s I2C* interface. The device also features spread-spectrum capability to reduce electromagnetic interference (EMI). This technique allows spreading the fundamental energy over a wider frequency range, hence reducing the respective energy amplitude. The output frequency spectrum is downspread by -1.25% or -2.5%. The MAX9492 operates from a 3.3V supply and is guaranteed over the extended temperature range (-40°C to +85°C). The device is available in a space-saving, 20-pin, TQFN, 5mm x 5mm package. Features ♦ Five LVCMOS Outputs with Independent Frequency Selections ♦ One Buffered Reference Clock Output ♦ Eight Selectable Frequencies: 133, 125, 83, 66, 62.5, 50, 33, and 25MHz ♦ Crystal or an Input-Clock-Based Clock Reference ♦ Output Frequency Programmed Through I2C Interface ♦ 0, -1.25%, or -2.5% Selectable Downspreading Rate ♦ Low Output Period Jitter (Without Spread Spectrum) < 10psRMS ♦ <220ps Output-to-Output Skew ♦ Available in 20-Lead, 5mm x 5mm, TQFN Package ♦ +3.3V Supply ♦ -40°C to +85°C Extended Temperature Range Applications Network Routers Ordering Information Telecom/Networking Equipment Storage Area Networks/Network Attached Storage PART TEMP RANGE PINPACKAGE 20 Thin QFN-EP** MAX9492ETP -40°C to +85°C 5mm x 5mm x 0.8mm PKG CODE T2055-3 **EP = Exposed pad. Typical Operating Circuit and Pin Configuration appear at end of data sheet. *Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9492 General Description MAX9492 Multiple-Output Clock Generator with Spread Spectrum ABSOLUTE MAXIMUM RATINGS VDD_ to GND .........................................................-0.3V to +4.0V All Other Pins to GND.................................-0.3V to (VDD + 1.0V) Short-Circuit Duration (all LVCMOS outputs) .............Continuous ESD Protection (Human Body Model)................................. ±2kV Continuous Power Dissipation (TA = +70°C) 20-Pin TQFN (derate 20.8mW/°C above +70°C) ......1667mW Storage Temperature Range .............................-65°C to +165°C Maximum Junction Temperature .....................................+150°C Operating Temperature Range ...........................-40°C to +85°C Lead Temperature (soldering, 10s) ................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VDD = VDDA = +3.0V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values at VDD = VDDA = +3.3V, TA = +25°C, with CLK1 at 25MHz, and all other CLK_ outputs at 133MHz.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.8 V +20 µA CLOCK INPUT (X1) Input High Level VIH1 Input Low Level VIL1 Input Current IIL1, IIH1 2.0 VX_ = 0 to VDD V -20 CLOCK OUTPUTS (CLK_) Output High Level VOH IOH = -100µA IOH = -4mA VDD 0.2 V 2.4 IOL = 100µA 0.2 IOL = 4mA 0.4 Output Low Level VOL Output Short-Circuit Current IOS CLK_ = VDD or GND Output Capacitance CO (Note 2) -60 V +69 mA 5 pF 0.8 V THREE-LEVEL INPUTS (SSC, SA0, SA1) Input High Level VIH2 Input Low Level VIL2 Input Open Level Input Current 2.5 VIO2 IIL2, IIH2 VIL2 = 0 or VIH2 = VDD V 1.35 1.90 V -15 +15 µA SERIAL INTERFACE (SCL, SDA) (Note 3) Input High Level VIH Input Low Level VIL Input Leakage Current 0.7 x VDD IIH, IIL Low-Level Output VOL Input Capacitance Ci V -1 0.3 x VDD V +1 µA ISINK = 4mA 0.4 V (Note 2) 10 pF 3.6 V POWER SUPPLIES Digital Power-Supply Voltage VDD Analog Power-Supply Voltage VDDA 3.0 3.6 V Total Supply Current IDC CL = 10pF 60 76 mA Output Disabled Supply Current IOD All clock registers = 0x0F 18 24 mA 2 3.0 _______________________________________________________________________________________ Multiple-Output Clock Generator with Spread Spectrum (VDD = VDDA = +3.0V to +3.6V, CL = 10pF, unless otherwise noted. Typical values at VDD = VDDA = +3.3V, TA = +25°C, with CLK1 at 25MHz and all other CLK_ outputs at 133MHz.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 10 35 MHz 15 35 MHz -50 +50 ppm OUTPUTS (CLK_) Crystal Frequency Input Frequency Range External clock Crystal Frequency Tolerance ∆fA Output-to-Output Skew tSKO Any two CLK_ outputs Rise Time tR1 20% VDD to 80% VDD Fall Time tF1 80% VDD to 20% VDD Duty Cycle 220 ps 1.9 2.5 ns 1.3 2.5 ns 60 % 15 ps 40 Output Period Jitter JP RMS (SSC = 0), CLK1 is disabled to high impedance Power-Up Time tPO VDD > 2.8V to PLL lock Frequency Spread 10 2 SSC = high -2.5 SSC = floating -1.25 ms % SERIAL INTERFACE TIMING (VDD = VDDA = +3.3V, TA = -40°C to +85°C.) (Note 1, Figure 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz Serial Clock fSCL Bus Free Time Between STOP and START Conditions tBUF 1.3 µs Hold Time, Repeated START Condition tHD,STA 0.6 µs Repeated START Condition Setup Time tSU,STA 0.6 µs STOP Condition Setup Time tSU,STO Data Hold Time tHD,DAT (Note 4) 0.6 15 900 ns µs Data Hold Time Slave tHD,DAT (Note 4) 15 900 ns Data Setup Time tSU,DAT 100 ns SCL Clock Low Period tLOW 1.3 µs SCL Clock High Period tHIGH 0.7 µs Rise Time of SDA and SCL, Receiving tR (Notes 2, 5) 20 + 0.1CB 300 ns Fall Time of SDA and SCL, Receiving tF (Notes 2, 5) 20 + 0.1CB 300 ns _______________________________________________________________________________________ 3 MAX9492 AC ELECTRICAL CHARACTERISTICS SERIAL INTERFACE TIMING (continued) (VDD = VDDA = +3.3V, TA = -40°C to +85°C.) (Note 1, Figure 1) PARAMETER SYMBOL CONDITIONS MIN TYP tF,TX (Notes 2, 6) 20 + 0.1CB Pulse Width of Spike Suppressed tSP (Notes 2, 7) 0 Capacitive Load for Each Bus Line CB (Note 2) Fall Time of SDA, Transmitting MAX UNITS 250 ns 50 ns 400 pF Note 1: All DC parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design. Note 2: Guaranteed by design. Note 3: No high output level is specified but only the output resistance to the bus. For I2C, the high-level voltage is provided by pullup resistors on the bus. Note 4: The device provides a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCL’s falling edge. Note 5: CB = total capacitance of one bus line in pF. tR and tF measured between 0.3 x VDD and 0.7 x VDD. Note 6: Bus sink current is less than 6mA. CB is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 x VDD and 0.7 x VDD. Note 7: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. TEMPERATURE (ALL OUTPUTS SET TO 133MHz) 61.2 2.0 2.3 MAX9492 toc03 2.5 MAX9492 toc02 61.6 FALL TIME vs. TEMPERATURE (ALL OUTPUTS SET TO 133MHz) RISE TIME vs. TEMPERATURE (ALL OUTPUTS SET TO 133MHz) MAX9492 toc01 62.0 1.8 60.4 60.0 59.6 FALL TIME (ns) 60.8 RISE TIME (ns) SUPPLY CURRENT (mA) MAX9492 Multiple-Output Clock Generator with Spread Spectrum 2.1 1.9 1.6 1.4 59.2 58.8 1.2 1.7 58.4 58.0 4 1.0 1.5 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 Multiple-Output Clock Generator with Spread Spectrum 133MHz OUTPUT WAVEFORM PERIOD JITTER vs. TEMPERATURE PERIOD JITTER (psRMS) 16 133MHz 83MHz OUTPUT WAVEFORM MAX9492 toc05 MAX9492 toc04 20 MAX9492 toc06 3.3V 3.3V 33.3MHz 12 125MHz 8 62.5MHz 4 0V 0V 0 -40 -15 10 35 60 2ns/div 2ns/div PERIOD JITTER vs. FREQUENCY 133MHz OUTPUT 0% DOWNSPREADING 85 TEMPERATURE (°C) DUTY CYCLE vs. TEMPERATURE 33.3MHz PERIOD JITTER (psRMS) DUTY CYCLE (%) 16 62.5MHz 50.0 49.5 49.0 133MHz 48.5 125MHz 48.0 MAX9492 toc09 MAX9492 toc08 50.5 20 MAX9492 toc07 51.0 12 10dB/REF 0dBm RBW = 10kHz VBW = 10kHz ATN = 20dB CENTER = 133MHz SPAN = 4MHz 8 4 47.5 0 47.0 -40 -15 10 35 60 25 85 TEMPERATURE (°C) 133MHz OUTPUT WITH 0% AND 1.25% DOWNSPREADING MAX9492 toc10 10dB/REF 0dBm VBW = 1kHz CENTER = 133MHz RBW = 100kHz ATN = 20dB SPAN = 15MHz 50 75 100 FREQUENCY (MHz) 125 150 133MHz OUTPUT WITH 0% AND 2.5% DOWNSPREADING MAX9492 toc11 10dB/REF 0dBm VBW = 1kHz CENTER = 133MHz RBW = 100kHz ATN = 20dB SPAN = 15MHz _______________________________________________________________________________________ 5 MAX9492 Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) MAX9492 Multiple-Output Clock Generator with Spread Spectrum Pin Description PIN NAME 1 GNDA FUNCTION 2 X1 3 X2 4 VDDA Power-Supply Input for Analog Circuits. Bypass to GNDA with a 0.1µF capacitor. 5, 13, 16 VDD Power-Supply Input for Digital Circuits. Bypass to GND with a 0.1µF capacitor. 6 SCL Serial Clock Input. Serial interface clock. 7 SDA Serial Data I/O. Data I/O of serial interface. Analog Ground Crystal Connection or Clock Input. If using a 25MHz crystal, connect it to X1 and X2. If using a reference clock, connect the clock signal to X1 and leave X2 floating. See the Typical Operating Circuit. 8, 20 GND Digital Ground 9 CLK1 Clock 1 Output. Buffered reference clock output. 10 CLK2 Clock 2 Output. Frequency-selectable clock output. 11 CLK3 Clock 3 Output. Frequency-selectable clock output. 12 CLK4 Clock 4 Output. Frequency-selectable clock output. 14 CLK5 Clock 5 Output. Frequency-selectable clock output. 15 CLK6 Clock 6 Output. Frequency-selectable clock output. 17 SSC Spread-Spectrum-Select Input. Selects the spectrum-spread percentage. When SSC is low, spread spectrum is disabled. When SSC is floating, spread spectrum is set to -1.25%. When SSC is high, spread spectrum is set to -2.5%. 18 SA1 19 SA0 Address-Select Inputs for Serial Interface. SA0 and SA1 select the serial interface address, as shown in Table 1. SA0 and SA1 are three-level inputs, making nine possible address combinations. EP GND Exposed pad. Connect to GND. Block Diagram VDDA SCL SDA VDD CLK1 I 2C SA0 SA1 266MHz PLL1 X1 MUX CLK2 MUX CLK5 MUX CLK6 DIVIDE BY 2, 4, 8 25MHz OSC X2 250MHz PLL2 SSC SPREAD SPECTRUM DIVIDE BY 2, 3, 4, 5, 10 MAX9492 AGND 6 GND _______________________________________________________________________________________ Multiple-Output Clock Generator with Spread Spectrum The MAX9492 frequency synthesizer is designed to generate multiple clocks for clock distribution in network routers or switches. The device provides a total of six buffered clock outputs (CLK1 to CLK6). CLK1 is the buffered output of the reference clock. CLK2 through CLK6 are independently programmable to generate eight different frequencies based on a 25MHz input crystal: 133, 125, 83, 66, 62.5, 50, 33, and 25MHz. All the outputs are LVCMOS single-ended signals. Select the MAX9492’s output frequency by programming on-chip registers through the I2C interface. The MAX9492 also features spread-spectrum capability to reduce EMI. Output frequency spectrum can be downspread by -2.5% or -1.25%. The 25MHz reference comes from either a crystal or an external clock. The MAX9492 incorporates two PLLs with two internal loop filters. The MAX9492 operates from a 3.3V supply. Reference Frequency Input The MAX9492 requires a reference frequency. The reference can be a 25MHz crystal or an external clock signal. If using a 25MHz crystal, connect it across X1 and X2, and connect loading capacitors from X1 and X2 to GND (refer to the crystal manufacturer’s specification). If using an external clock, connect the signal to X1 and leave X2 floating. Power-Up State At power-up, the CLK1 output is enabled and free running, the CLK2 to CLK4 outputs are set at 33.3MHz, and the other CLK outputs are disabled at logic-low. The output states can be overridden by writing to the registers through the I2C interface. Serial Interface The MAX9492 is programmed through its I 2C serial interface. This interface has a clock, SCL, and a bidirectional data line, SDA. In an I2C system, a master, typically a microcontroller, initiates all data transfers to and from slave devices, and generates the clock to synchronize the data transfers. The MAX9492 operates as a slave device. The timing of the SDA and SCL signals is detailed in Figure 1. SDA operates as both an input and an open-drain output. A pullup resistor, typically 4.7kΩ, is required on SDA. SCL operates only as an input. A pullup resistor, typically 4.7kΩ, is required on SCL. START and STOP Conditions A master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high (Figure 2). When communication is complete, a master issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. SDA tBUF tSU,STA tSU,DAT tHD,STA tLOW tSU,STO tHD,DAT SCL tHIGH tHD,STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 1. Serial-Interface Timing Diagram _______________________________________________________________________________________ 7 MAX9492 Detailed Description MAX9492 Multiple-Output Clock Generator with Spread Spectrum NOT ACKNOWLEDGE SDA 1 1 A4 A3 A1 A0 R/W ACK ACKNOWLEDGE LSB MSB SCL A2 START Figure 2. I2C Address and Acknowledge Bit Transfer One data bit is transferred during each SCL clock cycle. SDA must remain stable during the high period of SCL, as changes in SDA while SCL is high are START and STOP control signals. Idle the interface by pulling both SDA and SCL high. After 8 bits are transferred, the receiving device generates an acknowledge signal by pulling SDA low for the entire duration of the 9th clock pulse. If the receiving device does not pull SDA low, a not acknowledge is indicated (Figure 2). Table 1. Device I2C Address Selection 8 SA0 SA1 DEVICE ADDRESS Open Open 110 1000 Low Open 110 0100 High Open 110 0010 Open Low 110 1100 Low Low 110 1001 High Low 111 0000 Open High 111 0001 Low High 111 0010 High High 111 0100 Device Address The MAX9492 features a 7-bit device address, configured by the two three-level address inputs, SA1 and SA0. To select the device address, connect SA1 and SA0 to VDD, GND, or leave floating, as indicated in Table 1. The MAX9492 has nine possible addresses, allowing up to nine MAX9492 devices to share the same interface bus. Writing to the MAX9492 Writing to the MAX9492 begins with a START condition (Figure 3). Following the START condition, each pulse on SCL transfers 1 bit of data. The first 7 bits comprise the device address (see the Device Address section). The 8th bit is low to indicate a write operation. An acknowledge bit is then generated by the MAX9492, signaling that it recognizes its address. The next 8 bits form the register address byte (Table 2) and determine which control register receives the following data byte. The MAX9492 then generates another acknowledge bit. The data byte is then written into the addressed register of the MAX9492. An acknowledge bit by the MAX9492 followed by a required STOP condition by the master completes the communication. To write to the device again, the entire write procedure is repeated; I2C burstwrite mode is not supported by the MAX9492. _______________________________________________________________________________________ Multiple-Output Clock Generator with Spread Spectrum MAX9492 MASTER-WRITE DATA STRUCTURE START S R/W DEVICE ADDRESS 1 1 A4 A3 A2 A1 A0 0 REGISTER ADDRESS DATA IN ACK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 ACK D7 D6 D5 D4 D3 STOP D2 D1 D0 ACK P MASTER-READ DATA STRUCTURE START S R/W DEVICE ADDRESS 1 1 A4 A3 A2 A1 A0 0 REGISTER ADDRESS ACK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 ACK DEVICE ADDRESS RS 1 1 A4 A3 A2 R/W A1 A0 1 DATA OUT ACK D7 D6 S = START CONDITION A_ = DEVICE ADDRESS RA_ = REGISTER ADDRESS D_ = DATA DATA DIRECTION = MASTER TO SLAVE ACK = ACKNOWLEDGE P = STOP CONDITION = SLAVE TO MASTER ACK = NOT-ACKNOWLEDGE RS = REPEATED START D5 D4 D3 STOP D2 D1 D0 ACK P Figure 3. I2C Interface Data Structure Reading from the MAX9492 Reading from the MAX9492 registers begins with a START condition and a device address with the write bit set low, then the register address that is to be read, followed by a repeated START condition and a device address with the write bit set high, and finally the data are shifted out (Figure 3). Following a START condition, the first 7 bits comprise the device address. The 8th bit is low to indicate a write operation (to write in the following register address). An acknowledge bit is then generated by the MAX9492, signaling that it recognizes its address. The next 8 bits form the register address, indicating the location of the data to be read, followed by another acknowledge, again generated by the MAX9492. The master then produces a repeated START condition and readdresess the device, with the R/W bit high to indicate a read operation (Figure 3). The MAX9492 generates an acknowledge bit, signaling that it recognizes its address. The data byte is then clocked out of the MAX9492. A final not-acknowledge bit, generated by the master (not required), and a STOP condition, also generated by the master, complete the communication. To read from the device again, the entire read procedure is repeated; I 2 C burst-read mode is not supported by the MAX9492. Device Control Registers The MAX9492 has eight control registers. The register addresses and functions are shown in Table 2. The first seven registers are used to set the six outputs, with register 0x00 controlling all outputs simultaneously, and the rest are mapped to individual outputs. All other addresses are reserved and are not to be used. Table 2. Register Address Mapping REGISTER ADDRESS OUTPUT PORT 00 Broadcast to all CLK registers 01 CLK1 02 CLK2 03 CLK3 04 CLK4 05 CLK5 06 CLK6 All others Reserved _______________________________________________________________________________________ 9 Setting the Clock Frequencies Spread-Spectrum Control Each CLK_ output has an associated control register. The contents of the registers determine the frequencies of their associated outputs. Table 3 provides the frequency mapping for the registers. CLK1 only responds to the 25MHz and high-impedance settings in Table 3. For example, writing 03h to the CLK1 control register does not change CLK1’s output frequency to 133.3MHz. The CLK1 output continues to output a buffered reference clock signal. The MAX9492 features spread-spectrum output structures to spread radiated emissions over the frequency band. A programmable triangle-wave generator injects an offset element into the master oscillator to dither its output by -1.25% or -2.5%. The dither is controlled by the SSC input. When SSC is low, spread spectrum is disabled. When SSC is floating, spread spectrum is set to -1.25%. When SSC is high, spread spectrum is set to -2.5%. Power Supply Table 3. Output Frequency Selection for CLK1–CLK6 BITS IN CLKn REGISTERS OUTPUT FREQUENCY (MHz) 00 Logic-Low 01 133.3 02 125 03 83.3 04 66.6 05 62.5 The MAX9492 uses a 3.0V to 3.6V power supply connected to VDD, and 3.0V to 3.6V connected to VDDA. Bypass V DDA and V DD at the device with a 0.1µF capacitor. Additionally, use bulk bypass capacitors of 10µF where power enters the circuit board. Applications Information Board Layout Considerations As with all high-frequency devices, board layout is critical to proper operation. Place the crystal as close as possible to X1 and X2, and minimize parasitic capacitance around the crystal leads. Ensure that the exposed pad makes good contact with GND. 06 50 07 33.3 08 25 0F High Impedance Chip Information PROCESS: BiCMOS Pin Configuration Typical Operating Circuit +3.3V X1 VDD 25MHz MAX9492 14 13 12 11 16 10 CLK2 SSC 17 9 CLK1 SA1 18 8 GND SA0 19 7 SDA GND 20 6 SCL MAX9492 CLOCK OUTPUTS EXPOSED PADDLE (GND) 3 4 5 VDD GND 2 VDDA 1 X2 CLK6 X1 SDA SCL SA0 SA1 SSC AGND VDD CLK1 X2 SERIAL INTERFACE 15 0.1µF 10pF 10pF CLK3 0.1µF VDD CLK4 VDD VDD VDDA TOP VIEW CLK5 0.1µF 0.1µF CLK6 +3.3V GNDA MAX9492 Multiple-Output Clock Generator with Spread Spectrum THIN QFN 10 ______________________________________________________________________________________ Multiple-Output Clock Generator with Spread Spectrum QFN THIN.EPS D2 D b C L 0.10 M C A B D2/2 D/2 k L MARKING XXXXX E/2 E2/2 C L (NE-1) X e E DETAIL A PIN # 1 I.D. E2 PIN # 1 I.D. 0.35x45¡ e/2 e (ND-1) X e DETAIL B e L1 L C L C L L L e e 0.10 C A C 0.08 C A1 A3 PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm 21-0140 -DRAWING NOT TO SCALE- COMMON DIMENSIONS A1 A3 b D E e k L L1 N ND NE JEDEC 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0 0.02 0.05 0.20 REF. 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.25 - 0.25 - 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0.20 REF. 0.20 REF. 0.20 REF. 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.50 BSC. 0.40 BSC. 0.50 BSC. - 0.25 0.35 0.45 0.25 - 0.25 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 - 0.30 0.40 0.50 16 4 4 20 5 5 WHHB WHHC 1 2 EXPOSED PAD VARIATIONS PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A H 28 7 7 WHHD-1 32 8 8 40 10 10 WHHD-2 ----- NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. D2 L E2 PKG. CODES MIN. NOM. MAX. T1655-1 T1655-2 T1655N-1 3.00 3.00 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.10 3.10 3.20 3.20 3.20 T2055-2 T2055-3 T2055-4 3.00 3.00 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.10 3.10 3.20 3.20 3.20 T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 T4055-1 3.20 3.30 3.40 3.20 3.30 3.40 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 MIN. NOM. MAX. –0.15 ** ** ** ** ** ** 0.40 DOWN BONDS ALLOWED NO YES NO NO YES NO YES ** NO NO YES YES NO ** ** 0.40 ** ** ** ** ** NO YES YES NO NO YES NO NO ** YES ** ** ** ** ** SEE COMMON DIMENSIONS TABLE 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3, AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. 13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", –0.05. PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm 21-0140 -DRAWING NOT TO SCALE- H 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX9492 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)