MAXIM MAX1066CCUP

19-2466; Rev 0; 4/02
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
The 14-bit-wide MAX1065 is available in a 28-pin TSSOP
package, and the byte-wide MAX1066 is available in a
20-pin TSSOP package. Both devices are available in
either the 0°C to +70°C commercial, or the -40°C to
+85°C extended temperature range.
Features
♦ 14-Bit-Wide (MAX1065) and Byte-Wide (MAX1066)
Parallel Interface
♦ High Speed: 165ksps Sample Rate
♦ Accurate: ±1LSB DNL (max), ±1LSB INL (max)
♦ 4.096V, 35ppm/°C Internal Reference
♦ External Reference Range 3.8V to 5.25V
♦ Single 4.75V to 5.25V Analog Supply Voltage
♦ 2.7V to 5.25V Digital Supply Voltage
♦ Low Supply Current
1.8mA (External Reference)
2.7mA (Internal Reference)
0.1mA AutoShutdown Mode (10ksps, External
Reference)
♦ Small Footprint
28-Pin TSSOP Package (14-Bit Wide)
20-Pin TSSOP Package (Byte Wide)
Ordering Information
Applications
Temperature
Sensor/Monitor
Cable/Harness Tester
Accelerometer
Measurements
Digital Signal Processing
Industrial Process
Control
I/O Boards
Data-Acquisition
Systems
Typical Operating Circuit
5V ANALOG
5V DIGITAL
0.1µF
0.1µF
DVDD
AVDD
µP DATA
BUS
D0–D13
ANALOG INPUT
AIN
R/C
MAX1065
CS
PINPACKAGE
INL
MAX1065ACUI
0°C to 70°C
28 TSSOP
±1
MAX1065BCUI
0°C to 70°C
28 TSSOP
±2
MAX1065CCUI
0°C to 70°C
28 TSSOP
±3
MAX1065AEUI
-40°C to +85°C
28 TSSOP
±1
MAX1065BEUI
-40°C to +85°C
28 TSSOP
±2
MAX1065CEUI
-40°C to +85°C
28 TSSOP
±3
MAX1066ACUP
0°C to 70°C
20 TSSOP
±1
MAX1066BCUP
0°C to 70°C
20 TSSOP
±2
MAX1066CCUP
0°C to 70°C
20 TSSOP
±3
MAX1066AEUP
-40°C to +85°C
20 TSSOP
±1
MAX1066BEUP
-40°C to +85°C
20 TSSOP
±2
MAX1066CEUP
-40°C to +85°C
20 TSSOP
±3
EOC
REF
RESET
TEMP RANGE
PART
Pin Configurations appear at end of data sheet.
REFADJ
AGND
DGND
0.1µF
1µF
AutoShutdown is a registered trademark of Maxim Integrated
Products, Inc.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1065/MAX1066
General Description
The MAX1065/MAX1066 14-bit, low-power successive
approximation analog-to-digital converters (ADCs) feature automatic power-down, a factory-trimmed internal
clock, and a high-speed, 14-bit-wide (MAX1065) or
byte-wide (MAX1066) parallel interface. The devices
operate from a single 4.75V to 5.25V analog supply and
a 2.7V to 5.25V digital supply.
The MAX1065/MAX1066 use an internal 4.096V reference or an external reference. The MAX1065/MAX1066
consume only 1.8mA at a sampling rate of 165ksps with
external reference and 2.7mA with internal reference.
AutoShutdown™ reduces supply current to 0.1mA at
10ksps.
The MAX1065/MAX1066 are ideal for high-performance,
battery-powered, data-acquisition applications.
Excellent dynamic performance and low-power consumption in a small package make the MAX1065/
MAX1066 the best choice for circuits with demanding
power consumption and space requirements.
MAX1065/MAX1066
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V
DVDD to DGND.........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AIN, REF, REFADJ to AGND....................-0.3V to (AVDD + 0.3V)
CS, HBEN, R/C, RESET to DGND ............................-0.3V to +6V
Digital Output (D13–D0, EOC)
to DGND ..................................................-0.3V to (DVDD + 0.3V)
Maximum Continuous Current Into Any Pin ........................50mA
Continuous Power Dissipation (TA = +70°C)
20-Pin TSSOP (derate 10.9mW/°C above +70°C) .......879mW
28-Pin TSSOP (derate 12.8mW/°C above +70°C) .....1026mW
Operating Temperature Ranges
MAX106_ _CU_ ...................................................0°C to +70°C
MAX106_ _EU_ ................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = 5V, external reference = 4.096V, CREF = 1µF, CREFADJ = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
Relative Accuracy (Note 1)
Differential Nonlinearity
N
INL
DNL
14
±1
MAX106_B
±2
MAX106_C
±3
No missing codes over temperature
±1
RMS noise, includes quantization
noise
Transition Noise
(Note 2)
LSB
LSB
LSBRMS
0.32
Offset Error
Gain Error
Bits
MAX106_A
0.2
1
mV
±0.002
±0.02
%FSR
Offset Drift
0.6
ppm/°C
Gain Drift
0.2
ppm/°C
84
dB
DYNAMIC PERFORMANCE (fIN(SINE-WAVE) = 1kHz, VIN = 4.096VP-P, 165ksps)
Signal-to-Noise Plus Distortion
SINAD
81
Signal-to-Noise Ratio
SNR
82
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
84
-99
87
dB
-86
dB
102
dB
Full-Power Bandwidth
-3dB point
4
MHz
Full-Linear Bandwidth
SINAD > 81dB
20
kHz
CONVERSION RATE
Sample Rate
fSAMPLE
165
ksps
Aperture Delay
40
ns
Aperture Jitter
100
ps
ANALOG INPUT
Input Range
VAIN
Input Capacitance
CAIN
2
0
VREF
40
_______________________________________________________________________________________
V
pF
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
(AVDD = DVDD = 5V, external reference = 4.096V, CREF = 1µF, CREFADJ = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4.056
4.096
4.136
V
INTERNAL REFERENCE
REF Output Voltage
VREF
REF Output Tempco
TCREF
±35
ppm/°C
REF Short-Circuit Current
IREFSC
±10
mA
Capacitive Bypass at REFADJ
Capacitive Bypass at REF
REFADJ Input Leakage Current
CREFADJ
0.1
CREF
1
IREFADJ
µF
µF
20
µA
EXTERNAL REFERENCE
REFADJ Buffer Disable
Threshold
To power-down the internal reference
REF Input Voltage Range
REF Input Current
Internal reference disabled
IREF
AVDD 0.4
3.8
VREF = 4.096V, fSAMPLE = 165ksps
62
AVDD 0.1
V
AVDD
V
120
±0.1
Shutdown mode
µA
DIGITAL INPUTS/OUTPUTS (CS, R/C, EOC, D0–D13, RESET, HBEN)
Input High Voltage
0.7 x
DVDD
VIH
Input Low Voltage
0.3 x
DVDD
VIL
Input Leakage Current
Input Hysteresis
IIN
VIH = 0 or DVDD
±0.1
VHYST
Input Capacitance
CIN
Output High Voltage
VOH
ISOURCE = 0.5mA,
DVDD = 2.7V to 5.25V,
AVDD = 5.25V
Output Low Voltage
VOL
ISINK = 1.6mA,
DVDD = 2.7V to 5.25V,
AVDD = 5.25V
Three-State Leakage Current
IOZ
D0–D13
Three-State Output
Capacitance
COZ
±1
V
µA
0.1
V
15
pF
DVDD 0.4
V
±0.1
0.4
V
±10
µA
15
pF
POWER REQUIREMENTS
Analog Supply Voltage
AVDD
4.75
5.25
V
Digital Supply Voltage
DVDD
2.7
AVDD
V
Internal reference
Analog Supply Current
IAVDD
External reference
165ksps
2.7
100ksps
2.0
10ksps
1.0
1ksps
1.0
165ksps
1.8
100ksps
1.1
10ksps
0.1
1ksps
0.01
3.2
2.3
mA
_______________________________________________________________________________________
3
MAX1065/MAX1066
ELECTRICAL CHARACTERISTICS (continued)
MAX1065/MAX1066
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 5V, external reference = 4.096V, CREF = 1µF, CREFADJ = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
165ksps
Digital Supply Current
IDVDD
D0–D13 = all zeros
Full power-down
Shutdown Supply Current
(Note 3)
Power-Supply Rejection Ratio
(Note 4)
ISHDN
PSRR
REF and REF
buffer enabled
(standby mode)
TYP
MAX
0.5
0.7
100ksps
0.3
10ksps
0.03
1ksps
0.003
UNITS
mA
IAVDD
0.05
5
mA
IDVDD
0.5
5
µA
IAVDD
1.0
1.2
mA
IDVDD
0.5
5
µA
AVDD = 5V, ±5%, full-scale input
68
dB
TIMING CHARACTERISTICS (Figures 1 and 2)
(AVDD = 4.75V to 5.25V, DVDD = 2.7V to AVDD, external reference = 4.096V, CREF = 1µF, CREFADJ = 0.1µF, CD13–D0, CEOC = 20pF,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
Acquisition Time
tACQ
Conversion Time
tCONV
CS Pulse Width High
tCSH
CS Pulse Width Low
tCSL
R/C to CS Fall Setup Time
tDS
R/C to CS Fall Hold Time
tDH
CS to Output Data Valid
tDO
HBEN Transition To
Output Data Valid
(MAX1066 only)
tDO1
EOC Fall To CS Fall
tDV
CS Rise To EOC Rise
tEOC
Bus Relinquish Time
(Note 5)
tBR
CONDITIONS
MIN
TYP
MAX
1.1
4.7
(Note 5)
(Note 5)
40
VDVDD = 4.75V to 5.25V
40
VDVDD = 2.7V to 4.74V
60
40
VDVDD = 2.7V to 5.25V
60
µs
ns
ns
0
VDVDD = 4.75V to 5.25V
UNITS
ns
ns
VDVDD = 4.75V to 5.25V
40
VDVDD = 2.7V to 4.74V
80
VDVDD = 4.75V to 5.25V
40
VDVDD = 2.7V to 4.74V
80
ns
ns
0
ns
VDVDD = 4.75V to 5.25V
40
VDVDD = 2.7V to 4.74V
80
VDVDD = 4.75V to 5.25V
40
VDVDD = 2.7V to 4.74V
80
ns
ns
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 2: Offset nulled.
Note 3: Maximum specification is limited by automated test equipment.
Note 4: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply.
Note 5: To ensure best performance, finish reading the data and wait tBR before starting a new acquisition.
4
_______________________________________________________________________________________
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
0.4
1.0
INL (LSB)
0.2
1.5
0
-0.2
0.5
0
-0.5
-0.4
-1.0
-0.6
1
0.1
0.01
0.001
-1.5
-0.8
-1.0
-2.0
0
4096
8192
12288
16384
0.0001
0
4096
8192
12288
16384
1
10
IAVDD + IDVDD SUPPLY CURRENT
vs. TEMPERATURE
IAVDD + IDVDD SHUTDOWN CURRENT
vs. TEMPERATURE
INTERNAL REFERENCE
vs. TEMPERATURE
1.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
0
20
40
60
-20
0
20
40
60
200
0
-200
-400
0.015
0.010
0.005
0
-0.005
-800
-0.015
0
-0.020
60
80
0
20
40
60
80
SINAD vs. FREQUENCY
100
90
80
70
60
50
40
30
-0.010
-600
-20
TEMPERATURE (°C)
SINAD (dB)
400
TEMPERATURE (°C)
-40
MAX1065/MAX1066 toc08
600
40
4.076
80
0.020
GAIN ERROR (%FSR)
MAX1065/MAX1066 toc07
800
20
4.086
GAIN ERROR vs. TEMPERATURE
OFFSET ERROR vs. TEMPERATURE
1000
0
4.096
TEMPERATURE (°C)
TEMPERATURE (°C)
-20
4.106
4.056
-40
80
4.116
MAX1065/MAX1066 toc09
-20
4.126
4.066
0.5
SAMPLE RATE = 165ksps
MAX1065/MAX1066 toc06
MAX1065/MAX1066 toc05
4.0
4.136
INTERNAL REFERENCE (V)
1.5
4.5
SHUTDOWN CURRENT (µA)
MAX1065/MAX1066 toc04
2.0
5.0
1000
100
CONVERSION RATE (ksps)
2.5
-40
0.1
OUTPUT CODE
3.0
-40
0.01
OUTPUT CODE
3.5
OFFSET ERROR (µV)
10
MAX1065/MAX1066 toc03
0.6
MAX1065/MAX1066 toc02
0.8
DNL (LSB)
2.0
MAX1065/MAX1066 toc01
1.0
SUPPLY CURRENT (mA)
IAVDD + IDVDD SUPPLY CURRENT
vs. SAMPLE RATE
INL vs. OUTPUT CODE
SUPPLY CURRENT (mA)
DNL vs. OUTPUT CODE
20
10
SAMPLE RATE = 165ksps
0
-40
-20
0
20
40
TEMPERATURE (°C)
60
80
0.1
1
10
100
FREQUENCY (kHz)
_______________________________________________________________________________________
5
MAX1065/MAX1066
Typical Operating Characteristics
(AVDD = DVDD = 5V, external reference = 4.096V, CREF = 1µF, CREFADJ = 0.1µF, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(AVDD = DVDD = 5V, external reference = 4.096V, CREF = 1µF, CREFADJ = 0.1µF, TA = +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. FREQUENCY
-30
90
80
SFDR (dB)
-40
100
-50
-60
70
60
50
-70
40
-80
30
-90
20
-100
10
0.1
1
-40
-60
-80
-120
SAMPLE RATE = 165ksps
0.1
100
10
SAMPLE RATE = 165ksps
-20
-100
0
-110
0
1.0
10
-140
0
100
20
40
60
80
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
MAX1065/MAX1066 toc12
SAMPLE RATE = 165ksps
-20
MAX1065/MAX1066 toc11
-10
FFT AT 1kHz
110
MAX1065/MAX1066 toc10
0
MAGNITUDE (dB)
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
THD (dB)
MAX1065/MAX1066
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
Pin Description
PIN
6
NAME
FUNCTION
MAX1065
MAX1066
MAX1065
MAX1066
1
1
D6
D4/D12
Three-State Digital Data Output
2
2
D7
D5/D13
Three-State Digital Data Output. D13 is the MSB.
3
3
D8
D6/0
Three-State Digital Data Output
4
4
D9
D7/0
Three-State Digital Data Output
5
—
D10
—
Three-State Digital Data Output
6
—
D11
—
Three-State Digital Data Output
7
—
D12
—
Three-State Digital Data Output
8
—
D13
—
Three-State Digital Data Output (MSB)
9
5
R/C
Read/Convert Input. Power up and put the MAX1065/MAX1066 in acquisition
mode by holding R/C low during the first falling edge of CS. During the
second falling edge of CS the level on R/C determines whether the reference
and reference buffer power down or remain on after conversion. Set R/C high
during the second falling edge of CS to power down the reference and buffer,
or set R/C low to leave the reference and buffer powered up. Set R/C high
during the third falling edge of CS to put valid data on the bus.
10
6
EOC
End Of Conversion. EOC drives low when conversion is complete.
Analog Supply Input. Bypass with a 0.1µF capacitor to AGND.
11
7
AVDD
12
8
AGND
13
9
AIN
14
10
AGND
Analog Ground. Primary analog ground (star ground).
Analog Input
Analog Ground. Connect Pin 14 to Pin 12 (MAX1065). Connect Pin 10 to Pin 8
(MAX1066).
_______________________________________________________________________________________
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
PIN
NAME
MAX1066
15
11
REFADJ
Reference Buffer Output. Bypass REFADJ with a 0.1µF capacitor to AGND for
internal reference mode. Connect REFADJ to AVDD to select external
reference mode.
16
12
REF
Reference Input/Output. Bypass REF with a 1µF capacitor to AGND for internal
reference mode. External reference input when in external reference mode.
17
—
RESET
Reset Input. Logic high resets the device.
HBEN
High Byte-Enable Input. Used to multiplex the 14-bit conversion result.
1: Most significant byte available on the data bus.
0: Least significant byte available on the data bus.
—
MAX1065
FUNCTION
MAX1065
13
MAX1066
Convert Start. The first falling edge of CS powers up the device and enables
acquire mode when R/C is low. The second falling edge of CS starts
conversion. The third falling edge of CS loads the result onto the bus when R/C
is high.
18
14
CS
19
15
DGND
Digital Ground
20
16
DVDD
Digital Supply Voltage. Bypass with a 0.1µF capacitor to DGND.
21
17
N.C.
D0/D8
No Connection. Do Not Connect (MAX1065).
Three-State Digital Data Output (MAX1066).
22
18
N.C.
D1/D9
No Connection. Do Not Connect (MAX1065).
Three-State Digital Data Output (MAX1066).
23
19
D0
D2/D10
Three-State Digital Data Output
24
20
D1
D3/D11
Three-State Digital Data Output
25
—
D2
—
Three-State Digital Data Output
26
—
D3
—
Three-State Digital Data Output
27
—
D4
—
Three-State Digital Data Output
28
—
D5
—
Three-State Digital Data Output
Functional Diagram
REFADJ
HBEN*
AVDD
AGND
DVDD
DGND
5kΩ
REFERENCE
OUTPUT
REGISTERS
14 OR 8*
14 OR 8*
D0–D13
OR
D0/D8–D5/D13*
REF
AIN
CAPACITIVE
DAC
AGND
RESET**
CLOCK
CS
SUCCESSIVEAPPROXIMATION
REGISTER AND
CONTROL LOGIC
MAX1065
MAX1066
EOC
R/C
*BYTE WIDE (MAX1066 ONLY)
**16-BIT WIDE (MAX1065 ONLY)
_______________________________________________________________________________________
7
MAX1065/MAX1066
Pin Description (continued)
MAX1065/MAX1066
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
Detailed Description
Converter Operation
The MAX1065/MAX1066 use a successive-approximation
(SAR) conversion technique with an inherent track-andhold (T/H) stage to convert an analog input into a 14-bit
digital output. Parallel outputs provide a high-speed interface to most microprocessors (µPs). The Functional
Diagram shows a simplified internal architecture of the
MAX1065/MAX1066. Figure 3 shows a typical application
circuit for the MAX1066.
DVDD
1mA
D0–D13
D0–D13
CLOAD = 20pF
CLOAD = 20pF
1mA
DGND
DGND
Analog Input
The equivalent input circuit is shown in Figure 4. A
switched capacitor digital-to-analog converter (DAC)
provides an inherent track-and-hold function. The single-ended input is connected between AIN and AGND.
Input Bandwidth
The ADC’s input-tracking circuitry has a 4MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, use antialias filtering.
Internal protection diodes, which clamp the analog
input to AVDD and/or AGND, allow the input to swing
from AGND - 0.3V to AVDD + 0.3V, without damaging
the device.
If the analog input exceeds 300mV beyond the supplies, limit the input current to 10mA.
Track and Hold (T/H)
a) HIGH-Z TO VOH,
VOL TO VOH, AND
VOH TO HIGH-Z
b) HIGH-Z TO VOL,
VOH TO VOL, AND
VOL TO HIGH-Z
Figure 1. Load Circuits for D0–D13 Enable Time, CS to D0–D13
Delay Time and Bus Relinquish Time
tCSL
In track mode, the analog signal is acquired on the
internal hold capacitor. In hold mode, the T/H switches
open and the capacitive DAC samples the analog input.
tCSH
CS
tACQ
REF POWERDOWN BIT
R/C
tDH
tDS
tDV
tEOC
EOC
HI–Z
tCONV
D0–D13
tBR
tDO
HI-Z
DATA VALID
HBEN*
tDO1
D7/D13–D0/D8*
HIGH/LOW
BYTE VALID
tBR
HIGH/LOW
BYTE VALID
*HBEN AND BYTE-WIDE DATA BUS AVAILABLE ON MAX1066 ONLY.
Figure 2. MAX1065/MAX1066 Timing Diagram
8
_______________________________________________________________________________________
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
where R IN = 800Ω, R S = the input signal’s source
impedance, and t ACQ is never less than 1.1µs. A
source impedance less than 1kΩ does not significantly
affect the ADC’s performance.
To improve the input-signal bandwidth under AC conditions, drive AIN with a wideband buffer (>4MHz) that can
drive the ADC’s input capacitance and settle quickly.
Power-Down Modes
Select standby mode or shutdown mode with the R/C
bit during the second falling edge of CS (see Selecting
Standby or Shutdown Mode section). The MAX1065/
MAX1066 automatically enter either standby mode, reference and buffer on, or shutdown, reference and
buffer off, after each conversion depending on the status of R/C during the second falling edge of CS.
5V ANALOG
5V DIGITAL
0.1µF
0.1µF
DVDD
D0–D7 OR
D8–D13
AVDD
ANALOG INPUT
AIN
R/C
MAX1066
CS
EOC
REF
HIGH
BYTE
REFADJ
HBEN
LOW
BYTE
µP DATA
BUS
AGND
DGND
0.1µF
1µF
Internal Clock
The MAX1065/MAX1066 generate an internal conversion clock. This frees the microprocessor from the burden of running the SAR conversion clock. Total
conversion time after entering hold mode (second
falling edge of CS) to end-of-conversion (EOC) falling is
4.7µs (max).
Applications Information
Starting a Conversion
CS and R/C control acquisition and conversion in the
MAX1065/MAX1066 (Figure 2). The first falling edge of
CS powers up the device and puts it into acquisition
mode if R/C is low. The convert start is ignored if R/C is
high. When powering up from shutdown, the MAX1065/
MAX1066 needs at least 10ms (CREFADJ = 0.1µF, CREF
= 1µF) for the internal reference to wake up and settle
before starting the conversion. The ADC may wake up
from shutdown to an unknown state. Put the ADC in a
known state by completing one “dummy” conversion.
The MAX1065/ MAX1066 will be in a known state, ready
for actual data acquisition, after the completion of the
dummy conversion. A dummy conversion consists of one
full conversion cycle.
The MAX1065 provides an alternative reset function to
reset the device (see RESET section).
Selecting Standby or Shutdown Mode
The MAX1065/MAX1066 have a selectable standby or
low-power shutdown mode. In standby mode, the
ADC’s internal reference and reference buffer do not
power down between conversions, eliminating the need
to wait for the reference to power up before performing
the next conversion. Shutdown mode powers down the
reference and reference buffer after completing a conversion. Supply current is greatly reduced when in
shutdown mode. The reference and reference buffer
require a minimum of 10ms (CREFADJ = 0.1µF, CREF =
1µF) to power up and settle from shutdown.
The state of R/C at the second falling edge of CS
selects which power-down mode the MAX1065/
MAX1066 enters upon conversion completion. Holding
R/C low causes the MAX1065/MAX1066 to enter standby mode. The reference and buffer are left on after the
conversion completes. R/C high causes the
MAX1065/MAX1066 to enter shutdown mode and shut
down the reference and buffer after conversion
(Figures 5 and 6).
When using an external reference, set the REF powerdown bit high for lowest current operation.
Figure 3. Typical Application Circuit for MAX1066
_______________________________________________________________________________________
9
MAX1065/MAX1066
During the acquisition, the analog input (AIN) charges
capacitor CDAC. The acquisition ends on the second
falling edge of CS. At this instant, the T/H switches
open. The retained charge on C DAC represents a
sample of the input.
In hold mode, the capacitive DAC adjusts during the
remainder of the conversion time to restore node ZERO
to zero within the limits of 14-bit resolution. At the end of
the conversion, force CS low to put valid data on the bus.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is
high, the acquisition time lengthens and more time
must be allowed between conversions. The acquisition
time (tACQ) is the maximum time the device takes to
acquire the signal. Use the following formula to calculate acquisition time:
tACQ = 11(RS + RIN) x 35pF
MAX1065/MAX1066
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
Internal and External Reference
REF
TRACK
Internal Reference
The internal reference of the MAX1065/MAX1066 is
internally buffered to provide 4.096V (typ) output at
REF. Bypass REF to AGND and REFADJ to AGND with
1µF and 0.1µF respectively. Fine adjustments can be
made to the internal reference voltage by sinking or
sourcing current at REFADJ. The input impedance at
REFADJ is nominally 5kΩ. The internal reference voltage is adjustable to ±1.5% with the circuit of Figure 7.
CAPACITIVE DAC
AIN
ZERO
CSWITCH
3pF
HOLD
CDAC = 32pF
RIN
800Ω
HOLD
TRACK
AGND
AUTO-ZERO
RAIL
Figure 4. Equivalent Input Circuit
Standby Mode
While in standby mode, the supply current is reduced
to less than 1mA (typ). The next falling edge of CS with
R/C low causes the MAX1065/MAX1066 to exit standby
mode and begin acquisition. The reference and reference buffer remain active to allow quick turn-on time.
Standby mode allows significant power savings while
running at the maximum sample rate.
Shutdown Mode
In shutdown mode, the reference and reference buffer
are shut down between conversions. Shutdown mode
reduces supply current to 0.5µA (typ) immediately after
the conversion. The falling edge of CS with R/C low
causes the reference and buffer to wake up and enter
acquisition mode. To achieve 14-bit accuracy, allow
10ms (CREFADJ = 0.1µF, CREF = 1µF) for the internal
reference to wake up. Increase wakeup time proportionally when using larger values of CREFADJ and CREF.
ACQUISITION
CONVERSION
External Reference
An external reference can be placed at either the input
(REFADJ) or the output (REF) of the MAX1065/
MAX1066’s internal buffer amplifier. When connecting
an external reference to REFADJ, the input impedance
is typically 5kΩ. Using the buffered REFADJ input
makes buffering the external reference unnecessary;
however, the internal buffer output must be bypassed
at REF with a 1µF capacitor.
Connect REFADJ to AVDD to disable the internal buffer.
Directly drive REF using an external reference. During
conversion, the external reference must be able to
drive 100µA of DC load current and have an output
impedance of 10Ω or less. REFADJ’s impedance is typically 5kΩ. The DC input impedance of REF is 40kΩ
minimum.
For optimal performance, buffer the reference through
an op amp and bypass REF with a 1µF capacitor.
Consider the MAX1065/MAX1066’s equivalent input
noise (80µVRMS) when choosing a reference.
DATA
OUT
ACQUISITION
CS
REF POWERDOWN BIT
CS
R/C
R/C
EOC
EOC
REF
AND
BUFFER
REF
AND
BUFFER
Figure 5. Selecting Standby Mode
10
CONVERSION
REF POWERDOWN BIT
Figure 6. Selecting Shutdown Mode
______________________________________________________________________________________
DATA
OUT
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
68kΩ
100kΩ
11...110
11...101
REFADJ
150kΩ
FULL-SCALE
TRANSITION
11...111
MAX1065
MAX1066
0.22µF
FS = VREF
VREF
16384
1LSB =
00...011
00...010
00...001
Figure 7. MAX1065/MAX1066 Reference Adjust Circuit
00...000
0
Reading the Conversion Result
EOC is provided to flag the microprocessor when a conversion is complete. The falling edge of EOC signals
that the data is valid and ready to be output to the bus.
D0–D13 are the parallel outputs of the MAX1065/
MAX1066. These three-state outputs allow for direct
connection to a microcontroller I/O bus. The outputs
remain high-impedance during acquisition and conversion. Data is loaded onto the bus with the third falling
edge of CS with R/C high after tDOns. Bringing CS high
forces the output bus back to high-impedance. The
MAX1065/MAX1066 then waits for the next falling edge
of CS to start the next conversion cycle (Figure 2).
The MAX1065 loads the conversion result onto a 14-bitwide data bus while the MAX1066 has a byte-wide output format. HBEN toggles the output between the
most/least significant byte. The least significant byte is
loaded onto the output bus when HBEN is low and the
most significant byte is on the bus when HBEN is high
(Figure 2).
1
2
3
FS
INPUT VOLTAGE (LSB)
FS - 3/2LSB
Figure 8. MAX1065/MAX1066 Transfer Function
the required output voltage change before the beginning
of the acquisition time. At the beginning of acquisition, the
internal sampling capacitor array connects to AIN (the
amplifier output) causing some output disturbance.
Ensure that the sampled voltage has settled to within the
required limits before the end of the acquisition time. If
the frequency of interest is low, AIN can be bypassed
with a large enough capacitor to charge the internal sampling capacitor with very little ripple. However, for AC use,
AIN must be driven by a wideband buffer (at least
10MHz), which must be stable with the ADC’s capacitive
load (in parallel with any AIN bypass capacitor used) and
also settle quickly. An example of this circuit using the
MAX4434 is given in Figure 9.
RESET
Toggle RESET with CS high. The next falling edge of
CS will begin acquisition. This reset is an alternative to
the dummy conversion explained in the Starting a
Conversion section.
MAX1065/
MAX1066
Transfer Function
Figure 8 shows the MAX1065/MAX1066 output transfer
function. The output is coded in standard binary.
Input Buffer
Most applications require an input buffer amplifier to
achieve 14-bit accuracy. If the input signal is multiplexed,
the input channel should be switched immediately after
acquisition, rather than near the end of or after a conversion. This allows more time for the input buffer amplifier to
respond to a large step-change in input signal. The input
amplifier must have a high enough slew rate to complete
ANALOG
INPUT
10Ω
MAX4434
AIN
40pF
Figure 9. MAX1065/MAX1066 Fast Settling Input Buffer
______________________________________________________________________________________
11
MAX1065/MAX1066
OUTPUT CODE
5V
MAX1065/MAX1066
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Do not
run analog and digital lines parallel to each other, and do
not lay out digital signal paths underneath the ADC package. Use separate analog and digital ground planes with
only one point connecting the two ground systems (analog and digital) as close to the device as possible.
Route digital signals far away from sensitive analog and
reference inputs. If digital lines must cross analog lines,
do so at right angles to minimize coupling digital noise
onto the analog lines. If the analog and digital sections
share the same supply, then isolate the digital and analog supply by connecting them with a low-value (10Ω)
resistor or ferrite bead.
The ADC is sensitive to high-frequency noise on the AVDD
supply. Bypass AVDD to AGND with a 0.1µF capacitor in
parallel with a 1µF to 10µF low-ESR capacitor and the
smallest capacitor closest to the device. Keep capacitor
leads short to minimize stray inductance.
Definitions
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals.


SignalRMS
SINAD(dB) = 20 × log

 (Noise + Distortion)RMS 
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number
of bits as follows:
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1065/MAX1066
are measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of 1LSB guarantees no missing
codes and a monotonic transfer function.
Aperture Jitter and Delay
Aperture jitter is the sample-to-sample variation in the
time between samples. Aperture delay is the time
between the rising edge of the sampling clock and the
instant when the actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADC’s resolution (N-bits):
ENOB =
SINAD − 1.76
6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:

2
2
2
2
  V2 + V3 + V4 + V5  


THD = 20 × log


V1




where V1 is the fundamental amplitude and V2 through
V5 are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest frequency component.
Chip Information
TRANSISTOR COUNT: 15,140
PROCESS: BiCMOS
SNR = (6.02 x N + 1.76)dB
where N = 14 bits.
12
______________________________________________________________________________________
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
TOP VIEW
D6 1
28 D5
D4/D12 1
20 D3/D11
D7 2
27 D4
D5/D13 2
19 D2/D10
D8 3
26 D3
D6/0 3
D9 4
25 D2
D7/0 4
D10 5
24 D1
R/C 5
23 D0
EOC 6
22 N.C.
AVDD 7
14 CS
21 N.C.
AGND 8
13 HBEN
D11 6
MAX1065
D12 7
D13 8
R/C 9
20 DVDD
AIN 9
EOC 10
19 DGND
AGND 10
AVDD 11
18 CS
AGND 12
17 RESET
AIN 13
18 D1/D9
17 D0/D8
MAX1066
16 DVDD
15 DGND
12 REF
11 REFADJ
TSSOP
16 REF
15 REFADJ
AGND 14
TSSOP
______________________________________________________________________________________
13
MAX1065/MAX1066
Pin Configurations
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
TSSOP,NO PADS.EPS
MAX1065/MAX1066
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.