19-2755; Rev 0; 1/03 16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range The MAX1177/MAX1178/MAX1188 16-bit, low-power, successive-approximation analog-to-digital converters (ADCs) feature automatic power-down, a factorytrimmed internal clock, and a byte-wide parallel interface. The devices operate from a single +4.75V to +5.25V analog supply and feature a separate digital supply input for direct interface with +2.7V to +5.25V digital logic. The MAX1177 accepts an analog input voltage range from 0 to +10V. The MAX1188 accepts a bipolar analog input voltage range of ±10V, while the MAX1178 accepts a bipolar analog input voltage range of ±5V. All devices consume no more than 26.5mW at a sampling rate of 135ksps when using an external reference and 31mW when using the internal +4.096V reference. AutoShutdown™ reduces supply current to 0.4mA at 10ksps. The MAX1177/MAX1178/MAX1188 are ideal for highperformance, battery-powered, data-acquisition applications. Excellent AC performance (THD = -100dB) and DC accuracy (±2 LSB INL) make the MAX1177/ MAX1178/MAX1188 ideal for industrial process control, instrumentation, and medical applications. The MAX1177/MAX1178/MAX1188 are available in a 20-pin TSSOP package and are fully specified over the -40°C to +85°C extended temperature range and the 0°C to +70°C commercial temperature range. Features ♦ Byte-Wide Parallel Interface ♦ Analog Input Voltage Range: ±10V, ±5V, 0 to 10V ♦ Single +4.75V to +5.25V Analog Supply Voltage ♦ Interfaces with +2.7V to +5.25V Digital Logic ♦ ±2 LSB INL (max) ♦ ±1 LSB DNL (max) ♦ Low Supply Current (max) 2.9mA (External Reference) 3.8mA (Internal Reference) 5µA AutoShutdown Mode ♦ Small Footprint ♦ 20-Pin TSSOP Package Ordering Information PART TEMP RANGE INPUT PINVOLTAGE PACKAGE RANGE (V) MAX1177ACUP* 0°C to +70°C 20 TSSOP 0 to +10 MAX1177BCUP* 0°C to +70°C 20 TSSOP 0 to +10 MAX1177CCUP* 0°C to +70°C 20 TSSOP 0 to +10 MAX1177AEUP* -40°C to +85°C 20 TSSOP 0 to +10 MAX1177BEUP* -40°C to +85°C 20 TSSOP 0 to +10 MAX1177CEUP* -40°C to +85°C 20 TSSOP 0 to +10 *Future product—contact factory for availability. Ordering Information continued at end of data sheet. Applications Typical Operating Circuit Temperature Sensing and Monitoring +5V ANALOG Industrial Process Control I/O Modules +5V DIGITAL 0.1µF 0.1µF Data-Acquisition Systems ANALOG INPUT AIN R/C CS Pin Configuration and Functional Diagram appear at end of data sheet. AutoShutdown is a trademark of Maxim Integrated Products, Inc. µP DATA D0–D7 BUS OR D8–D15 DVDD AVDD Precision Instrumentation MAX1177 MAX1178 MAX1188 EOC REF REFADJ HBEN HIGH BYTE AGND DGND 0.1µF 10µF LOW BYTE ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1177/MAX1178/MAX1188 General Description MAX1177/MAX1178/MAX1188 16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range ABSOLUTE MAXIMUM RATINGS AVDD to AGND .........................................................-0.3V to +6V DVDD to DGND.........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V AIN to AGND .....................................................-16.5V to +16.5V REF, REFADJ to AGND............................-0.3V to (AVDD + 0.3V) CS, R/C, HBEN to DGND .........................................-0.3V to +6V D_, EOC to DGND ...................................-0.3V to (DVDD + 0.3V) Maximum Continuous Current into any Pin.........................50mA Continuous Power Dissipation (TA = +70°C) 20-Pin TSSOP (derate 10.9mW/°C above +70°C) .......879mW Operating Temperature Ranges MAX11_ _ _CUP..................................................0°C to +70°C MAX11_ _ _EUP ...............................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = DVDD = +5V ±5%, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution Differential Nonlinearity Integral Nonlinearity RES DNL INL Transition Noise 16 Bits MAX11_ _A -1 +1 MAX11_ _B -1 +1.5 MAX11_ _C -1 +2 MAX11_ _A -2 +2 MAX11_ _B -2 +2 MAX11_ _C -4 +4 No missing codes overtemperature RMS noise, external reference 0.6 Internal reference 0.75 Offset Error -10 LSB LSB LSBRMS 0 +10 mV Gain Error 0 ±0.2 %FSR Offset Drift 16 µV/°C Gain Drift ±1 ppm/°C AC ACCURACY (fIN = 1kHz, VAIN = full range, 135ksps) Signal-to-Noise Plus Distortion Signal-to-Noise Ratio SINAD 86 90 dB SNR 87 91 dB Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR -100 92 -92 103 dB dB ANALOG INPUT Input Range Input Resistance VAIN RAIN MAX1177 0 10 MAX1188 -10 +10 MAX1178 -5 +5 MAX1177/MAX1178 Normal operation 5.3 MAX1177 Shutdown mode 5.3 MAX1178 Shutdown mode 3.0 Normal operation 7.8 Shutdown mode 6.0 MAX1188 2 6.9 9.2 10 13.0 V kΩ _______________________________________________________________________________________ 16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range (AVDD = DVDD = +5V ±5%, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MAX1177, 0 ≤ VAIN ≤ +10V Input Current IAIN MIN Input Capacitance IPU MAX -0.1 +2.0 MAX1188, -10V ≤ VAIN ≤ +10V Normal operation -1.8 +1.2 Shutdown mode -1.8 +1.8 MAX1178, -5V ≤ VAIN ≤ +5V Normal operation -1.8 +0.4 Shutdown mode -1.8 +1.8 MAX1188, VAIN = +10V, shutdown mode to operating mode Input Current Step at Power-Up TYP 0.5 UNITS mA 0.7 mA MAX1178, VAIN = +5V, shutdown mode to operating mode 1 CIN 1.4 10 pF INTERNAL REFERENCE REF Output Voltage VREF 4.056 REF Output Tempco REF Short-Circuit Current IREF-SC 4.096 4.136 V ±35 ppm/°C ±10 mA EXTERNAL REFERENCE REF and REFADJ Input Voltage Range REFADJ Buffer Disable Threshold REF Input Current IREF REFADJ Input Current IREFADJ 3.8 4.2 V AVDD 0.4 AVDD 0.1 V Normal mode, fSAMPLE = 135ksps Shutdown mode (Note 1) REFADJ = AVDD 60 100 ±0.1 ±10 16 µA µA DIGITAL INPUTS/OUTPUTS Output High Voltage VOH ISOURCE = 0.5mA, DVDD = +2.7V to +5.25V, AVDD = +5.25V Output Low Voltage VOL ISINK = 1.6mA, DVDD = +2.7V to +5.25V, AVDD = +5.25V Input High Voltage VIH Input Low Voltage VIL Input Leakage Current Input Hysteresis DVDD 0.4 V 0.4 0.7 × DVDD Digital input = DVDD or 0V V V -1 0.3 × DVDD V +1 µA VHYST 0.2 V Input Capacitance CIN 15 pF Three-State Output Leakage IOZ Three-State Output Capacitance COZ ±10 15 µA pF _______________________________________________________________________________________ 3 MAX1177/MAX1178/MAX1188 ELECTRICAL CHARACTERISTICS (continued) MAX1177/MAX1178/MAX1188 16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = +5V ±5%, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4.75 5.25 V 2.70 5.25 V POWER SUPPLIES Analog Supply Voltage AVDD Digital Supply Voltage DVDD Analog Supply Current IAVDD Shutdown Supply Current ISHDN Digital Supply Current IDVDD Power-Supply Rejection External reference, 135ksps MAX1177 Internal reference, 135ksps MAX1177 2.9 MAX1178/MAX1188 4 5.3 3.8 MAX1178/MAX1188 mA 5.2 6.2 Shutdown mode (Note 1), digital input = DVDD or 0V 0.5 5 µA Standby mode 3.7 0.75 mA AVDD = DVDD = 4.75V to 5.25V mA 3.5 LSB TIMING CHARACTERISTICS (Figures 1 and 2) (AVDD = +4.75V to +5.25V ±5%, DVDD = +2.7V to AVDD, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, CLOAD = 20pF, TA = TMIN to TMAX.) PARAMETER Maximum Sampling Rate SYMBOL tACQ Conversion Time tCONV tCSH CS Pulse Width Low tCSL R/C to CS Fall Setup Time tDS R/C to CS Fall Hold Time tDH CS to Output Data Valid tDO EOC Fall to CS Fall tDV CS Rise to EOC Rise tEOC Bus Relinquish Time tBR HBEN Transition to Output Data Valid MIN TYP fSAMPLE-MAX Acquisition Time CS Pulse Width High CONDITIONS tDO1 UNITS 135 ksps 4.7 µs 2 (Note 2) (Note 2) µs 40 DVDD = 4.75V to 5.25V 40 DVDD = 2.7V to 5.25V 60 ns ns 0 DVDD = 4.75V to 5.25V 40 DVDD = 2.7V to 5.25V 60 ns ns DVDD = 4.75V to 5.25V 40 DVDD = 2.7V to 5.25V 80 0 40 DVDD = 2.7V to 5.25V 80 DVDD = 4.75V to 5.25V 40 DVDD = 2.7V to 5.25V 80 DVDD = 4.75V to 5.25V 40 DVDD = 2.7V to 5.25V 80 _______________________________________________________________________________________ ns ns DVDD = 4.75V to 5.25V Note 1: Maximum specification is limited by automated test equipment. Note 2: To ensure best performance, finish reading the data and wait tBR before starting a new acquisition. 4 MAX ns ns ns 16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range MAX1177/78/88 toc02 2.5 1.5 1.5 1.0 1.0 0.5 0 -0.5 0 -0.5 -1.0 -1.5 -1.5 -2.0 -2.0 30000 40000 -2.5 50000 60000 0 STANDBY MODE 0.1 SHUTDOWN MODE 0.01 0.001 5.0 SHUTDOWN SUPPLY CURRENT (µA) MAX1177/78/88 toc04 SUPPLY CURRENT (mA) 1 VAIN = 0V 0.0001 10 100 4.5 4.0 3.5 2.5 2.0 1.5 -0.05 -0.10 -0.15 -0.20 TEMPERATURE (°C) 0 -2 60 MAX1188 MAX1178 -4 -8 0 -10 -20 0 20 40 60 80 -40 -20 0 80 20 40 60 80 TEMPERATURE (°C) FFT AT 1kHz 0 MAX1177/78/88 toc08 4.136 4.126 4.116 4.106 4.096 4.086 fSAMPLE = 131ksps -20 -40 -60 -80 -100 -120 4.076 -140 4.066 -160 -180 4.056 40 MAX1177 2 -6 MAGNITUDE (dB) 0 20 4 0.5 -40 INTERNAL REFERENCE (V) MAX1177/78/88 toc07 GAIN ERROR (%FSR) 0.05 80 60 6 INTERNAL REFERENCE vs. TEMPERATURE 0.10 40 8 TEMPERATURE (°C) 0.15 20 10 1.0 1000 0.20 0 0 OFFSET ERROR vs. TEMPERATURE 3.0 GAIN ERROR vs. TEMPERATURE -20 -20 TEMPERATURE (°C) NO CONVERSIONS SAMPLE RATE (ksps) -40 -40 SHUTDOWN CURRENT (AVDD + DVDD) vs. TEMPERATURE 10 1 4.75V fSAMPLE = 135ksps SHUTDOWN MODE BETWEEN CONVERSIONS CODE SUPPLY CURRENT (AVDD + DVDD) vs. SAMPLE RATE 0.1 4.55 4.40 10000 20000 30000 40000 50000 60000 CODE 0.01 4.60 MAX1177/78/88 toc06 20000 5.0V 4.65 4.45 OFFSET ERROR (mV) 10000 4.70 4.50 MAX1177/78/88 toc05 0 5.25V 4.75 0.5 -1.0 -2.5 4.80 MAX1177/78/88 toc09 2.0 SUPPLY CURRENT (mA) 2.0 DNL (LSB) INL (LSB) 2.5 SUPPLY CURRENT (AVDD + DVDD) vs. TEMPERATURE DNL vs. CODE MAX1177/78/88 toc01 MAX1177/78/88 toc03 INL vs. CODE -40 -20 0 20 40 TEMPERATURE (°C) 60 80 0 10 20 30 40 50 60 FREQUENCY (kHz) _______________________________________________________________________________________ 5 MAX1177/MAX1178/MAX1188 Typical Operating Characteristics (Typical Application Circuit, AVDD = DVDD = +5V, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, CLOAD = 20pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) Typical Operating Characteristics (continued) (Typical Application Circuit, AVDD = DVDD = +5V, external reference = +4.096V, CREF = 10µF, CREFADJ = 0.1µF, VREFADJ = AVDD, CLOAD = 20pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) SFDR vs. FREQUENCY 80 70 0 MAX1177/78/88 toc11 MAX1177/78/88 toc10 90 THD vs. FREQUENCY 120 100 -10 -20 -30 80 50 40 -40 THD (dB) SFDR (dB) 60 60 -50 -60 -70 40 30 MAX1177/78/88 toc12 SINAD vs. FREQUENCY 100 SINAD (dB) MAX1177/MAX1178/MAX1188 16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range -80 20 -90 20 10 fSAMPLE = 131ksps fSAMPLE = 131ksps 0 -100 0 1 10 100 fSAMPLE = 131ksps -110 1 FREQUENCY (kHz) 100 10 FREQUENCY (kHz) 1 10 100 FREQUENCY (kHz) Pin Description PIN NAME 1 D4/D12 Three-State Digital Data Output 2 D5/D13 Three-State Digital Data Output 3 D6/D14 Three-State Digital Data Output 4 D7/D15 Three-State Digital Data Output. D15 is the MSB. R/C Read/Convert Input. Power up and put the MAX1177/MAX1178/MAX1188 in acquisition mode by holding R/C low during the first falling edge of CS. During the second falling edge of CS, the level on R/C determines whether the reference and reference buffer power down or remain on after conversion. Set R/C high during the second falling edge of CS to power down the reference and buffer, or set R/C low to leave the reference and buffer powered up. Set R/C high during the third falling edge of CS to put valid data on the bus. 6 EOC End of Conversion. EOC drives low when conversion is complete. 7 AVDD Analog Supply Input. Bypass with a 0.1µF capacitor to AGND. 8 AGND Analog Ground. Primary analog ground (star ground). 5 6 FUNCTION 9 AIN 10 AGND Analog Input 11 REFADJ Reference Buffer Output. Bypass REFADJ with a 0.1µF capacitor to AGND for internal reference mode. Connect REFADJ to AVDD to select external reference mode. 12 REF Reference Input/Output. Bypass REF with a 10µF capacitor to AGND for internal reference mode. External reference input when in external reference mode. Analog Ground. Connect pin 10 to pin 8. _______________________________________________________________________________________ 16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range PIN NAME FUNCTION 13 HBEN 14 CS 15 DGND Digital Ground 16 DVDD Digital Supply Voltage. Bypass with a 0.1µF capacitor to DGND. 17 D0/D8 Three-State Digital Data Output. D0 is the LSB. 18 D1/D9 Three-State Digital Data Output 19 D2/D10 Three-State Digital Data Output 20 D3/D11 Three-State Digital Data Output High-Byte Enable Input. Used to multiplex the 16-bit conversion result. 1: Most significant byte available on the data bus. 0: Least significant byte available on the data bus. Convert Start. The first falling edge of CS powers up the device and enables acquire mode when R/C is low. The second falling edge of CS starts conversion. The third falling edge of CS loads the result onto the bus when R/C is high. Analog Input DVDD 1mA DO–D15 DO–D15 CLOAD = 20pF CLOAD = 20pF 1mA DGND DGND a) HIGH-Z TO VOH, VOL TO VOH, AND VOH TO HIGH-Z b) HIGH-Z TO VOL, VOH TO VOL, AND VOL TO HIGH-Z Figure 1. Load Circuits Detailed Description Converter Operation The MAX1177/MAX1178/MAX1188 use a successiveapproximation (SAR) conversion technique with an inherent track-and-hold (T/H) stage to convert an analog input into a 16-bit digital output. Parallel outputs provide a high-speed interface to microprocessors (µPs). The Functional Diagram shows a simplified internal architecture of the MAX1177/MAX1178/MAX1188. Figure 3 shows a typical application circuit for the MAX1177/MAX1178/MAX1188. Input Scaler The MAX1177/MAX1178/MAX1188 have an input scaler, which allows conversion of true bipolar input voltages and input voltages greater than the power supply, while operating from a single +5V analog supply. The input scaler attenuates and shifts the analog input to match the input range of the internal DAC. The MAX1177 has a unipolar input voltage range of 0 to +10V. The MAX1188 input voltage range is ±10V while the MAX1178 input voltage range is ±5V. Figure 4 shows the equivalent input circuit of the MAX1177/ MAX1178/MAX1188. This circuit limits the current going into or out of AIN to less than 1.8mA. Track and Hold (T/H) In track mode, the internal hold capacitor acquires the analog signal (see Figure 4). In hold mode, the T/H switches open and the capacitive DAC samples the analog input. During the acquisition, the analog input (AIN) charges capacitor CHOLD. The acquisition ends on the second falling edge of CS. At this instant, the T/H switches open. The retained charge on CHOLD represents a sample of the input. In hold mode, the capacitive DAC adjusts during the remainder of the conversion time to restore node T/H OUT to zero within the limits of 16-bit resolution. Force CS low to put valid data on the bus after conversion is complete. _______________________________________________________________________________________ 7 MAX1177/MAX1178/MAX1188 Pin Description (continued) MAX1177/MAX1178/MAX1188 16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range tCSH tCSL CS tACQ REF POWERDOWN CONTROL R/C tDH tDS tEOC tDV EOC tCONV tDO HBEN tBR tDO1 tDO HIGH-Z HIGH-Z D7/D15–D0/D8 HIGH/LOW BYTE VALID HIGH/LOW BYTE VALID Figure 2. MAX1177/MAX1178/MAX1188 Timing Diagram Power-Down Modes Select standby mode or shutdown mode with the R/C bit during the second falling edge of CS (see the Selecting Standby or Shutdown Mode section). The MAX1177/MAX1178/MAX1188 automatically enter either standby mode (reference and buffer on) or shutdown (reference and buffer off) after each conversion, depending on the status of R/C during the second falling edge of CS. Internal Clock +5V ANALOG 0.1µF Starting a Conversion CS and R/C control acquisition and conversion in the MAX1177/MAX1178/MAX1188 (see Figure 2). The first falling edge of CS powers up the device and puts it in acquire mode if R/C is low. The convert start is ignored if R/C is high. The MAX1177/MAX1178/MAX1188 need 8 0.1µF DVDD AVDD ANALOG INPUT The MAX1177/MAX1178/MAX1188 generate an internal conversion clock to free the microprocessor from the burden of running the SAR conversion clock. Total conversion time (tCONV) after entering hold mode (second falling edge of CS) to end of conversion (EOC) falling is 4.7µs (max). Applications Information +5V DIGITAL µP DATA D0–D7 BUS OR D8–D15 AIN R/C CS MAX1177 MAX1178 MAX1188 EOC REF REFADJ HBEN HIGH BYTE AGND DGND 0.1µF 10µF LOW BYTE Figure 3. Typical Application Circuit for the MAX1177/MAX1178/ MAX1188 _______________________________________________________________________________________ 16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range MAX1177 R2 MAX1178/MAX1188 R1 3.4kΩ 161Ω AIN TRACK S1 CHOLD 30pF R2 R1 3.4kΩ 161Ω TRACK S1 AIN CHOLD 30pF T/H OUT R3 T/H OUT R3 HOLD TRACK HOLD S2 HOLD S3 POWERDOWN TRACK HOLD S2 R2 = 7.85kΩ (MAX1188) OR 3.92kΩ (MAX1177/MAX1178) S1, S2 = T/H SWITCH S3 = POWER-DOWN (MAX1178/MAX1188 ONLY) R3 = 5.45kΩ (MAX1188) OR 17.79kΩ (MAX1177/MAX1178) Figure 4. Equivalent Input Circuit at least 12ms (CREFADJ = 0.1µF, CREF = 10µF) for the internal reference to wake up and settle before starting the conversion, if powering up from shutdown. Selecting Standby or Shutdown Mode The MAX1177/MAX1178/MAX1188 have a selectable standby or low-power shutdown mode. In standby mode, the ADC’s internal reference and reference buffer do not power down between conversions, eliminating the need to wait for the reference to power up before performing the next conversion. Shutdown mode powers down the reference and reference buffer after completing a conversion. The reference and reference buffer require a minimum of 12ms (CREFADJ = 0.1µF, CREF = 10µF) to power up and settle from shutdown. The state of R/C at the second falling edge of CS selects which power-down mode the MAX1177/ MAX1178/MAX1188 enter upon conversion completion. Holding R/C low causes the MAX1177/MAX1178/ MAX1188 to enter standby mode. The reference and buffer are left on after the conversion completes. R/C high causes the MAX1177/MAX1178/MAX1188 to enter shutdown mode and power down the reference and buffer after conversion (see Figures 5 and 6). Set the voltage at R/C high during the second falling edge of CS to realize the lowest current operation. Standby Mode While in standby mode, the supply current is less than 3.7mA (typ). The next falling edge of CS with R/C low causes the MAX1177/MAX1178/MAX1188 to exit standby mode and begin acquisition. The reference and reference buffer remain active to allow quick turn-on time. Shutdown Mode In shutdown mode, the reference and reference buffer are shut down between conversions. Shutdown mode reduces supply current to 0.5µA (typ) immediately after the conversion. The next falling edge of CS with R/C low causes the reference and buffer to wake up and enter acquisition mode. To achieve 16-bit accuracy, allow 12ms (CREFADJ = 0.1µF, CREF = 10µF) for the internal reference to wake up. Internal and External Reference Internal Reference The internal reference of the MAX1177/MAX1178/ MAX1188 is internally buffered to provide +4.096V output at REF. Bypass REF to AGND and REFADJ to AGND with 10µF and 0.1µF, respectively. Sink or source current at REFADJ to make fine adjustments to the internal reference. The input impedance of REFADJ is nominally 5kΩ. Use the circuit of Figure 7 to adjust the internal reference to ±1.5%. _______________________________________________________________________________________ 9 MAX1177/MAX1178/MAX1188 REF MAX1177/MAX1178/MAX1188 16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range ACQUISITION CONVERSION DATA OUT ACQUISITION CS CS R/C R/C EOC EOC REF AND BUFFER POWER REF AND BUFFER POWER CONVERSION DATA OUT Figure 5. Selecting Standby Mode Figure 6. Selecting Shutdown Mode External Reference An external reference can be placed at either the input (REFADJ) or the output (REF) of the MAX1177/ MAX1178/MAX1188s’ internal buffer amplifier. Using the buffered REFADJ input makes buffering the external reference unnecessary. The input impedance of REFADJ is typically 5kΩ. The internal buffer output must be bypassed at REF with a 10µF capacitor. HBEN toggles the output between the high/low byte. The low byte is loaded onto the output bus when HBEN is low and the high byte is on the bus when HBEN is high. Connect REFADJ to AVDD to disable the internal buffer. Directly drive REF using an external 3.8V to 4.2V reference. During conversion, the external reference must be able to drive 100µA of DC load current and have an output impedance of 10Ω or less. For optimal performance, buffer the reference through an op amp and bypass REF with a 10µF capacitor. Consider the MAX1177/MAX1178/MAX1188s’ equivalent input noise (0.6 LSB) when choosing a reference. Reading the Conversion Result EOC is provided to flag the microprocessor when a conversion is complete. The falling edge of EOC signals that the data is valid and ready to be output to the bus. D0–D15 are the parallel outputs of the MAX1177/MAX1178/MAX1188. These three-state outputs allow for direct connection to a microcontroller I/O bus. The outputs remain high impedance during acquisition and conversion. Data is loaded onto the output bus with the third falling edge of CS with R/C high (after tDO). Bringing CS high forces the output bus back to high impedance. The MAX1177/MAX1178/MAX1188 then wait for the next falling edge of CS to start the next conversion cycle (see Figure 2). 10 Transfer Function Figures 8, 9, and 10 show the MAX1177/MAX1178/ MAX1188 output transfer functions. The MAX1188 and MAX1178 outputs are coded in offset binary, while the MAX1177 is coded in standard binary. Input Buffer Most applications require an input buffer amplifier to achieve 16-bit accuracy and prevent loading the source. Switch the channels immediately after acquisition, rather than near the end of, or after, a conversion, when the input signal is multiplexed. This allows more time for the input buffer amplifier to respond to a large step change in input signal. The input amplifier must have a high enough slew rate to complete the required output voltage change before the beginning of the acquisition time. Figure 11 shows an example of this circuit using the MAX427. Figures 12a and 12b show how the MAX1188 and MAX1178 analog input current varies depending on whether the chip is operating or powered down. The part is fully powered down between conversions if the voltage at R/C is set high during the second falling edge of CS. The input current abruptly steps to the powered-up value at the start of acquisition. This step in the input current can disrupt the ADC input, depending on the driving circuit’s output impedance at high frequencies. If the driving circuit cannot fully settle by the end of acquisition, the accuracy of the system can ______________________________________________________________________________________ 16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range FULL-SCALE TRANSITION 11 1111 1111 1111 MAX1177 MAX1178 MAX1188 +5V MAX1177/MAX1178/MAX1188 MAX1177 INPUT RANGE = 0V TO +10V OUTPUT CODE 11 1111 1111 1110 11 1111 1111 1101 68kΩ 100kΩ REFADJ FULL-SCALE RANGE (FSR) = +10V 0.1µF 150kΩ 1LSB = 00 0000 0000 0011 FSR x VREF 65536 x 4.096 00 0000 0000 0010 00 0000 0000 0001 00 0000 0000 0000 0 1 2 3 65535 65534 65536 INPUT VOLTAGE (LSB) Figure 7. MAX1177/MAX1178/MAX1188 Reference Adjust Circuit OUTPUT CODE 11 1111 1111 1111 MAX1188 INPUT RANGE = -10V TO +10V FULL-SCALE TRANSITION Figure 8. MAX1177 Transfer Function OUTPUT CODE 11 1111 1111 1111 11 1111 1111 1110 11 1111 1111 1110 11 1111 1111 1101 11 1111 1111 1101 10 0000 0000 0001 10 0000 0000 0000 FULL-SCALE RANGE (FSR) = +20V 01 1111 1111 1111 1LSB = 00 0000 0000 0011 00 0000 0000 0010 FSR x VREF 65536 x 4.096 MAX1178 INPUT RANGE = -5V TO +5V FULL-SCALE TRANSITION 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 00 0000 0000 0011 00 0000 0000 0010 FULL-SCALE RANGE (FSR) = +1V 1LSB = FSR x VREF 65536 x 4.096 00 0000 0000 0001 00 0000 0000 0001 00 0000 0000 0000 0 +32766 +32768 -32768 -32766 +1 -32767 -32765 -1 +32767 INPUT VOLTAGE (LSB) 00 0000 0000 0000 0 +32766 +32768 -32768 -32766 +1 -32767 -32765 -1 +32767 INPUT VOLTAGE (LSB) Figure 9. MAX1188 Transfer Function Figure 10. MAX1178 Transfer Function be compromised. To avoid this situation, increase the acquisition time, use a driving circuit that can settle within tACQ, or leave the MAX1178/MAX1188 powered up by setting the voltage at R/C low during the second falling edge of CS. planes with only one point connecting the two ground systems (analog and digital) as close to the device as possible. Route digital signals far away from sensitive analog and reference inputs. If digital lines must cross analog lines, do so at right angles to minimize coupling digital noise onto the analog lines. If the analog and digital sections share the same supply, isolate the digital and analog supply by connecting them with a low value (10Ω) resistor or ferrite bead. Layout, Grounding, and Bypassing For best performance, use printed circuit boards. Do not run analog and digital lines parallel to each other, and do not lay out digital signal paths underneath the ADC package. Use separate analog and digital ground ______________________________________________________________________________________ 11 MAX1178 ANALOG INPUT CURRENT vs. ANALOG INPUT VOLTAGE REF MAX1177 MAX1178 MAX1188 MAX427 ** * AIN ANALOG INPUT CURRENT (mA) ANALOG INPUT 1.5 1.0 0.5 SHUTDOWN MODE 0 -0.5 STANDBY MODE -1.0 *MAX1177 ONLY. **MAX1178/MAX1188 ONLY. -1.5 -5.0 -2.5 0 2.5 5.0 ANALOG INPUT VOLTAGE (V) Figure 11. MAX1177/MAX1178/MAX1188 Fast-Settling Input Buffer Figure 12a. MAX1178 Analog Input Current The ADC is sensitive to high-frequency noise on the AV DD supply. Bypass AV DD to AGND with a 0.1µF capacitor in parallel with a 1µF to 10µF low-ESR capacitor with the smallest capacitor closest to the device. Keep capacitor leads short to minimize stray inductance. Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1177/MAX1178/ MAX1188 are measured using the end-point method. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of 1 LSB guarantees no missing codes and a monotonic transfer function. 12 MAX1188 ANALOG INPUT CURRENT vs. ANALOG INPUT VOLTAGE 1.5 ANALOG INPUT CURRENT (mA) MAX1177/MAX1178/MAX1188 16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range 1.0 0.5 SHUTDOWN MODE 0 STANDBY MODE -0.5 -1.0 -1.5 -10 -5 0 5 ANALOG INPUT VOLTAGE (V) Figure 12b. MAX1188 Analog Input Current ______________________________________________________________________________________ 10 16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range SNR = (6.02 × N + 1.76) dB where N = 16 bits. In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. The SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all the other ADC output signals: SignalRMS SINAD(dB) = 20 × log (Noise + Distortion)RMS zation noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number of bits as follows: ENOB = SINAD −1.76 6.02 Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: V22 + V32 + V4 2 + V52 THD = 20 × log V1 where V1 is the fundamental amplitude and V2 through V5 are the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest frequency component. Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quanti- ______________________________________________________________________________________ 13 MAX1177/MAX1178/MAX1188 Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADC’s resolution (N bits): 16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range MAX1177/MAX1178/MAX1188 Functional Diagram REFADJ HBEN AVDD AGND DVDD DGND 5kΩ REFERENCE OUTPUT REGISTERS 8 BITS 8 BITS D0–D7 OR D8–D15 REF AIN INPUT SCALER CAPACITIVE DAC MAX1177 MAX1178 MAX1188 AGND SUCCESSIVEAPPROXIMATION REGISTER AND CONTROL LOGIC CLOCK CS EOC R/C Pin Configuration TOP VIEW Ordering Information (continued) PART TEMP RANGE INPUT PINVOLTAGE PACKAGE RANGE (V) D4/D12 1 20 D3/D11 D5/D13 2 19 D2/D10 MAX1178ACUP 0°C to +70°C 20 TSSOP ±5 D6/D14 3 18 D1/D9 MAX1178BCUP 0°C to +70°C 20 TSSOP ±5 D7/D15 4 17 D0/D8 MAX1178CCUP 0°C to +70°C 20 TSSOP ±5 16 DVDD MAX1178AEUP -40°C to +85°C 20 TSSOP ±5 15 DGND MAX1178BEUP -40°C to +85°C 20 TSSOP ±5 AVDD 7 14 CS MAX1178CEUP -40°C to +85°C 20 TSSOP ±5 AGND 8 13 HBEN MAX1188ACUP 0°C to +70°C 20 TSSOP ±10 12 REF MAX1188BCUP 0°C to +70°C 20 TSSOP ±10 11 REFADJ MAX1188CCUP 0°C to +70°C 20 TSSOP ±10 MAX1188AEUP -40°C to +85°C 20 TSSOP ±10 MAX1188BEUP -40°C to +85°C 20 TSSOP ±10 MAX1188CEUP -40°C to +85°C 20 TSSOP ±10 R/C 5 EOC 6 MAX1177 MAX1178 MAX1188 AIN 9 AGND 10 TSSOP Chip Information TRANSISTOR COUNT: 15,383 PROCESS: BiCMOS 14 ______________________________________________________________________________________ 16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range TSSOP4.40mm.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX1177/MAX1178/MAX1188 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)