19-2999; Rev 0; 10/03 KIT ATION EVALU LE B A IL A AV Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL ♦ EV Kit Available—MAX5858AEVKit Ordering Information PART MAX5858AECM TEMP RANGE PIN-PACKAGE -40°C to +85°C 48 TQFP-EP* *EP = Exposed paddle. N.C. N.C. AVDD REFR OUTPA OUTNA AGND OUTPB OUTNB DVDD DGND AVDD Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 DA9/PD DA8/DACEN DA7/F2EN DA6/F1EN DA5/G3 DGND DVDD DA4/G2 DA3/G1 DA2/G0 DA1 DA0 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 EP MAX5858A REFO REN PLLF PGND PVDD CLKXN CLKXP PLLEN LOCK CW DB0 DB1 DB3 DB2 IDE DB4 CLK DGND 13 14 15 16 17 18 19 20 21 22 23 24 DB5 DVDD Communications SatCom, LMDS, MMDS, HFC, DSL, WLAN, Point-to-Point Microwave Links Wireless Base Stations Direct Digital Synthesis Instrumentation/ATE ♦ Interleave Data Mode ♦ Differential Clock Input Modes DB7 DB6 Applications ♦ Integrated 1.24V Low-Noise Bandgap Reference ♦ Single-Resistor Gain Control DB8 The MAX5858A features full-scale current outputs of 2mA to 20mA and operates from a 2.7V to 3.3V single supply. The DAC supports three modes of power-control operation: normal, low-power standby, and complete power-down. In power-down mode, the operating current is reduced to 1µA. The MAX5858A is packaged in a 48-pin TQFP with exposed paddle (EP) for enhanced thermal dissipation and is specified for the extended (-40°C to +85°C) operating temperature range. ♦ Internal PLL Multiplier ♦ 2.7V to 3.3V Single Supply ♦ Full Output Swing and Dynamic Performance at 2.7V Supply ♦ Superior Dynamic Performance 73dBc SFDR at fOUT = 20MHz UMTS ACLR = 63dB at fOUT = 30.7MHz ♦ Programmable Channel Gain Matching DB9 The MAX5858A features digital control of channel gain matching to within ±0.4dB in sixteen 0.05dB steps. Channel matching improves sideband suppression in analog quadrature modulation applications. The onchip 1.24V bandgap reference includes a control amplifier that allows external full-scale adjustments of both channels through a single resistor. The internal reference can be disabled and an external reference can be applied for high-accuracy applications. Features ♦ 10-Bit Resolution, Dual DAC ♦ 300Msps Update Rate ♦ Integrated 4x/2x/1x Interpolating Filters TQFP-EP NOTE: EXPOSED PADDLE CONNECTED TO GND. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5858A General Description The MAX5858A dual, 10-bit, 300Msps digital-to-analog converter (DAC) provides superior dynamic performance in wideband communication systems. The MAX5858A integrates two 10-bit DAC cores, 4x/2x/1x programmable digital interpolation filters, phase-lock loop (PLL) clock multiplier, and a 1.24V reference. The MAX5858A supports single-ended and differential modes of operation. The MAX5858A dynamic performance is maintained over the entire power-supply operating range of 2.7V to 3.3V. The analog outputs support a compliance voltage of -1.0V to +1.25V. The 4x/2x/1x programmable interpolation filters feature excellent passband distortion and noise performance. Interpolating filters minimize the design complexity of analog reconstruction filters while lowering the data bus and the clock speeds of the digital interface. The PLL multiplier generates all internal, synchronized highspeed clock signals for interpolating filter operation and DAC core conversion. The internal PLL helps minimize system complexity and lower cost. To reduce the I/O pin count, the DAC can also operate in interleave data mode. This allows the MAX5858A to be updated on a single 10-bit bus. MAX5858A Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL ABSOLUTE MAXIMUM RATINGS AVDD, DVDD, PVDD to AGND, DGND, PGND ..........-0.3V to +4V DA9–DA0, DB9–DB0, CW, REN, PLLF, PLLEN to AGND, DGND, PGND........................................................-0.3V to +4V IDE to AGND, DGND, PGND ...................-0.3V to (DVDD + 0.3V) CLKXN, CLKXP to PGND .........................................-0.3V to +4V OUTP_, OUTN_ to AGND.......................-1.25V to (AVDD + 0.3V) CLK, LOCK to DGND...............................-0.3V to (DVDD + 0.3V) REFR, REFO to AGND .............................-0.3V to (AVDD + 0.3V) AGND to DGND, DGND to PGND, AGND to PGND ..................................................-0.3V to +0.3V Maximum Current into Any Pin (excluding power supplies) ............................................±50mA Continuous Power Dissipation (TA = +70°C) 48-Pin TQFP-EP (derate 36.2mW/°C above +70°C) ....2.899W Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, fDAC = 165Msps, no interpolation, PLL disabled, external reference, VREFO = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 10 Bits Integral Nonlinearity INL RL = 0 -1.25 ±0.5 +1.25 LSB Differential Nonlinearity DNL Guaranteed monotonic, RL = 0 -0.75 ±0.25 +0.75 LSB Offset Error VOS LSB Gain Error (See Gain Error Parameter Definitions Section) GE -0.5 ±0.1 +0.5 Internal reference (Note 1) -10 ±1.6 +11 External reference -8 ±1.2 +8 % DYNAMIC PERFORMANCE Maximum DAC Update Rate fDAC 4x/2x interpolation modes 300 Glitch Impulse fOUT = 5MHz, TA ≥ +25°C fDAC = 165Msps Spurious-Free Dynamic Range to Input Update Rate Nyquist SFDR fDAC = 300Msps, 2x interpolation Spurious-Free Dynamic Range Within a Window Msps 5 SFDR 68 76 fOUT = 20MHz 73 fOUT = 50MHz 66 fOUT = 70MHz 65 fOUT = 5MHz 76 fOUT = 40MHz 73 fOUT = 60MHz 72 fDAC = 200Msps, 2x interpolation, fOUT = 40MHz, span = 20MHz fDAC = 165Msps, fOUT = 5MHz, span = 4MHz pV-s dBc 85 dBc 76.5 85 Multitone Power Ratio, 8 Tones, ~300kHz Spacing MTPR fDAC = 165Msps, fOUT = 20MHz 76 dBc Adjacent Channel Leakage Ratio with UMTS ACLR fDAC =122.88Msps, fOUT = 30.72MHz 63 dB 2 _______________________________________________________________________________________ Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, fDAC = 165Msps, no interpolation, PLL disabled, external reference, VREFO = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER Total Harmonic Distortion to Nyquist Noise Spectral Density SYMBOL CONDITIONS MIN TYP MAX UNITS THD fDAC = 165Msps, fOUT = 5MHz -72 dBc nD fDAC = 165Msps, fOUT = 5MHz -143 dBm/Hz Output Channel-to-Channel Isolation fOUT = 5MHz 80 dB Gain Mismatch Between Channels fOUT = 5MHz ±0.05 dB Phase Mismatch Between Channels fOUT = 5MHz ±0.15 Degrees 50 pA/√Hz Wideband Output Noise ANALOG OUTPUT Full-Scale Output Current Range IFS Output Voltage Compliance Range Output Leakage Current Power-down or standby mode 2 20 mA -1.0 +1.25 V -5 +5 µA REFERENCE Reference Output Voltage Output-Voltage Temperature Drift VREF0 REN = AGND 1.14 TCVREF Reference Output Drive Capability REN = AVDD Reference Input Voltage Range Reference Supply Rejection Current Gain IFS/IREF 1.24 1.34 V ±50 ppm/°C 50 µA 0.10 1.32 V 0.2 mV/V 32 mA/mA INTERPOLATION FILTER (2x interpolation) -0.005dB fOUT/ 0.5fDAC Passband Width Stopband Rejection 0.398 -0.01dB 0.402 -0.1dB 0.419 -3dB 0.478 0.604fDAC / 2 to 1.396fDAC / 2 74 0.600fDAC / 2 to 1.400fDAC / 2 62 0.594fDAC / 2 to 1.406fDAC / 2 53 0.532fDAC / 2 to 1.468fDAC / 2 14 MHz/ MHz dB Group Delay 18 Data clock cycles Impulse Response Duration 22 Data clock cycles _______________________________________________________________________________________ 3 MAX5858A ELECTRICAL CHARACTERISTICS (continued) MAX5858A Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, fDAC = 165Msps, no interpolation, PLL disabled, external reference, VREFO = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INTERPOLATION FILTER (4x interpolation) Passband Width fOUT/ 0.5fDAC Stopband Rejection -0.005dB 0.200 -0.01dB 0.201 -0.1dB 0.210 -3dB 0.239 0.302fDAC / 2 to 1.698fDAC / 2 74 0.300fDAC / 2 to 1.700fDAC / 2 63 0.297fDAC / 2 to 1.703 fDAC / 2 53 0.266fDAC / 2 to 1.734fDAC / 2 14 Group Delay 22 Impulse Response Duration 27 MHz/ MHz dB Data clock cycles Data clock cycles LOGIC INPUTS (IDE, CW, REN, DA9–DA0, DB9–DB0, PLLEN) Digital Input-Voltage High VIH Digital Input-Voltage Low VIL 2 Digital Input-Current High IH VIH = 2V -1 Digital Input-Current Low IIL VIL = 0.8V -1 Digital Input Capacitance CIN V 0.8 V +1 µA +1 3 µA pF DIGITAL OUTPUTS (CLK, LOCK) Digital Output-Voltage High VOH ISOURCE = 0.5mA, Figure 1 Digital Output-Voltage Low VOL ISINK = 0.5mA, Figure 1 0.9 × DVDD V 0.1 × DVDD V DIFFERENTIAL CLOCK INPUT (CLKXP, CLKXN) Clock Input Internal Bias PVDD / 2 Differential Clock Input Swing V 0.5 Clock Input Impedance Single-ended clock drive VP-P 5 kΩ TIMING CHARACTERISTICS No interpolation Input Data Rate fDATA 2x interpolation 4x interpolation 165 PLL disabled PLL enabled 150 75 PLL disabled PLL enabled 4 fCLK Msps 75 37.5 No interpolation, PLL enabled Clock Frequency at CLK Input 150 75 165 2x interpolation, PLL enabled 75 150 4x interpolation, PLL enabled 37.5 75 _______________________________________________________________________________________ MHz Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, fDAC = 165Msps, no interpolation, PLL disabled, external reference, VREFO = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER Output Settling Time SYMBOL ts CONDITIONS MIN To ±0.1% error band (Note 2) TYP MAX 11 UNITS ns Output Rise Time 10% to 90% (Note 2) 2.5 ns Output Fall Time 90% to 10% (Note 2) 2.5 ns PLL disabled 1.5 PLL enabled 2.2 PLL disabled 0.4 PLL enabled 1.4 PLL disabled 1.8 PLL enabled 2.4 PLL disabled 1.2 PLL enabled 1.3 Data-to-CLK Rise Setup Time (Note 3) tDCSR Data-to-CLK Rise Hold Time (Note 3) tDCHR Data-to-CLK Fall Setup Time (Note 3) tDCSF Data-to-CLK Fall Hold Time (Note 3) tDCHF Control Word to CW Fall Setup Time tCWS 2.5 ns Control Word to CW Fall Hold Time tCWH 2.5 ns CW High Time 5 ns CW Low Time 5 ns DACEN Rise-to-VOUT Stable PD Fall-to-VOUT Stable Clock Frequency at CLKXP/CLKXN Input tSTB tPDSTB fCLKDIFF CLKXP/CLKXN Differential Clock Input to CLK Output Delay tCXD Minimum CLKXP/CLKXN Clock High Time Minimum CLKXP/CLKXN Clock Low Time External reference ns ns ns ns 0.7 µs 0.5 ms Differential clock, PLL disabled 300 PLL disabled MHz 4.6 ns tCXH 1.5 ns tCXL 1.5 ns POWER REQUIREMENTS Analog Power-Supply Voltage AVDD Analog Supply Current IAVDD Digital Power-Supply Voltage DVDD 2.7 (Note 4) 45 2.7 3.3 V 49 mA 3.3 V _______________________________________________________________________________________ 5 MAX5858A ELECTRICAL CHARACTERISTICS (continued) MAX5858A Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, fDAC = 165Msps, no interpolation, PLL disabled, external reference, VREFO = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25°C guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS fDAC = 60Msps Digital Supply Current (Note 4) IDVDD fDAC = 165Msps fDAC = 200Msps PLL Power-Supply Voltage PLL Supply Current (Note 4) Standby Current 34 2x interpolation 75 4x interpolation 72 No interpolation 54 2x interpolation 146 4x interpolation 140 61 172 186 4x interpolation 165 178 3.3 fDAC = 60Msps 17 fDAC = 165Msps 46 52 fDAC = 200Msps, 2x interpolation or 4x interpolation 55 61 ISTANDBY (Note 5) 4.4 4.8 IPD (Note 5) 1 IPVDD PTOT fDAC = 165Msps fDAC = 200Msps No interpolation 324 2x interpolation 487 4x interpolation 498 No interpolation 438 2x interpolation 735 4x interpolation 721 2x interpolation 816 4x interpolation 795 Including the internal reference voltage tolerance. Measured single ended with 50Ω load and complementary output connected to ground. Guaranteed by design, not production tested. Tested with an output frequency of fOUT = 5MHz. All digital inputs at 0 or DVDD. Clock signal disabled. 0.5mA TO OUTPUT PIN 1.6V 5pF 0.5mA Figure 1. Load Test Circuit for CLK Outputs 6 MAX 2x interpolation 2.7 fDAC = 60Msps Note 1: Note 2: Note 3: Note 4: Note 5: TYP No interpolation PVDD Power-Down Current Total Power Dissipation (Note 4) MIN _______________________________________________________________________________________ UNITS mA V mA mA µA 486 mW Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (NO INTERPOLATION, fDAC = 65MHz) 80 70 60 60 SFDR (dBc) 70 50 AOUT = -12dBS 40 AOUT = 0dBFS 100 80 AOUT = 0dBFS AOUT = -12dBFS 40 60 40 30 30 20 20 20 10 10 10 PLL DISABLED 0 10 20 30 40 50 60 70 80 10 15 20 25 30 35 30 40 50 60 70 SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (2x INTERPOLATION, fDAC = 300MHz) SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (2x INTERPOLATION, fDAC = 165MHz) SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (4x INTERPOLATION, fDAC = 165MHz) AOUT = 0dBFS 40 80 70 AOUT = 0dBFS AOUT = -12dBFS 50 40 60 40 30 30 20 20 20 10 10 20 30 40 50 60 70 5 0 80 10 15 20 25 30 35 OUTPUT FREQUENCY (MHz) 40 45 80 3 6 9 12 15 18 21 SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (4x INTERPOLATION, fDAC = 300MHz) 100 MAX5858A toc07 AOUT = -6dBFS 90 0 OUTPUT FREQUENCY (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (4x INTERPOLATION, fDAC = 300MHz) 100 PLL DISABLED 0 OUTPUT FREQUENCY (MHz) AOUT = -6dBFS 90 80 70 70 60 SFDR (dBc) SFDR (dBc) 10 10 PLL DISABLED 0 AOUT = 0dBFS AOUT = -12dBFS 50 30 PLL ENABLED AOUT = -6dBFS 90 SFDR (dBc) 60 SFDR (dBc) 60 100 MAX5858A toc06 80 70 AOUT = -12dBFS AOUT = -6dBFS 90 80 MAX5858A toc08 MAX5858A toc04 100 70 0 20 OUTPUT FREQUENCY (MHz) 80 0 10 0 OUTPUT FREQUENCY (MHz) AOUT = -6dBFS 50 5 0 OUTPUT FREQUENCY (MHz) 100 90 90 PLL DISABLED 0 MAX5858A toc05 0 AOUT = -12dBFS AOUT = 0dBFS 50 30 PLL DISABLED AOUT = -6dBFS 90 70 50 0 SFDR (dBc) AOUT = -6dBFS 90 SFDR (dBc) AOUT = -6dBFS 80 SFDR (dBc) 100 MAX5858A toc02 90 MAX5858A toc01 100 SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (2x INTERPOLATION, fDAC = 300MHz) MAX5858A toc03 SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (NO INTERPOLATION, fDAC = 165MHz) AOUT = -12dBFS AOUT = 0dBFS 50 40 60 40 30 30 20 20 10 10 PLL ENABLED 0 AOUT = -12dBFS AOUT = 0dBFS 50 PLL DISABLED 0 0 5 10 15 20 25 30 OUTPUT FREQUENCY (MHz) 35 40 0 5 10 15 20 25 30 35 40 OUTPUT FREQUENCY (MHz) _______________________________________________________________________________________ 7 MAX5858A Typical Operating Characteristics (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS = 20mA, differential output, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS = 20mA, differential output, TA = +25°C, unless otherwise noted.) SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (NO INTERPOLATION, fDAC = 165MHz) 80 70 AOUT = -6dBFS AOUT = -12dBFS 50 40 60 TA = +85°C 50 0 TA = +25°C 40 -20 -30 -40 -50 -60 -70 30 30 20 20 10 10 -90 0 0 -100 -40 -15 10 35 60 FFT PLOT FOR DAC UPDATE NYQUIST WINDOW (NO INTERPOLATION, fDAC = 165MHz, fOUT = 10MHz, AOUT = 0dBFS) 30 40 50 60 70 80 7.8 8.2 8.6 9.0 9.4 9.8 10.2 10.6 11.0 11.4 90 -40 -50 -60 -70 FFT PLOT FOR DAC UPDATE NYQUIST WINDOW (4x INTERPOLATION, fDAC = 200MHz, fOUT = 10MHz, AOUT = 0dBFS) 0 -20 -10 -20 OUTPUT POWER (dBm) -30 OUTPUT FREQUENCY (MHz) MAX5858A toc13 0 -10 OUTPUT POWER (dBm) -20 20 FFT PLOT FOR DAC UPDATE NYQUIST WINDOW (2x INTERPOLATION, fDAC = 200MHz, fOUT = 10MHz, AOUT = 0dBFS) MAX5858A toc12 0 10 OUTPUT FREQUENCY (MHz) TEMPERATURE (°C) -10 -80 0 85 -30 -40 -50 -60 -70 -30 -40 -50 -60 -70 -80 -80 -90 -90 -90 -100 -100 -100 0 8.25 fDAC = 165MHz fOUT = 10MHz AOUT = -6dBFS -10 16.50 33.00 66.00 82.50 49.50 24.75 41.25 57.75 74.25 MAX5858A toc14 60 SFDR (dBc) 70 SFDR (dBc) TA = -10°C OUTPUT POWER (dBm) 80 90 MAX5858A toc10 AOUT = 0dBFS 90 100 MAX5858A toc09 100 FFT PLOT (±2MHz WINDOW) -80 0 10 20 30 40 50 60 70 80 90 100 OUTPUT FREQUENCY (MHz) 0 10 20 30 40 50 60 70 80 90 100 OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) 8 MAX5858A toc11 SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE (NO INTERPOLATION, fDAC = 165MHz, fOUT = 5MHz) OUTPUT POWER (dBm) MAX5858A Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL _______________________________________________________________________________________ Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL MAX5858A Typical Operating Characteristics (continued) (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS = 20mA, differential output, TA = +25°C, unless otherwise noted.) 8-TONE MTPR PLOT (NO INTERPOLATION, fDAC = 165MHz, fCENTER = 19.9503MHz) fT1 -30 -20 fT2 -50 -60 2 x fT1 - fT2 2 x fT2 - fT1 -80 fT1 -30 -40 fT6 fT4 fT2 fT5 -50 fT7 fT3 -60 0 fT8 -70 -20 4.5 4.7 4.9 5.1 5.3 OUTPUT FREQUENCY (MHz) 19.0 19.5 20.0 20.5 21.0 OUTPUT FREQUENCY (MHz) -40 -50 -60 -70 -80 A 35.8MHz -20 B A: IN-BAND-RANGE B: OUT-OF-BAND RANGE -30 -40 -50 -60 -70 -90 9.15 17.30 33.60 66.20 82.50 49.90 25.25 41.75 58.05 74.35 OUTPUT FREQUENCY (MHz) fT8 29.0 29.5 30.0 30.5 31.0 OUTPUT FREQUENCY (MHz) 31.5 fT5 = 30.2281MHz fT6 = 30.5952MHz fT7 = 30.8924MHz fT8 = 31.1546MHz ACLR UMTS PLOT (NO INTERPOLATION, fDAC = 122.88MHz, fDATA = 122.88MHz, fCENTER = 30.72MHz) -20 ACLR = 63dB -30 -40 -50 -60 -70 -80 -80 -100 1.00 fT3 -10 OUTPUT POWER (dBm) -30 fT7 -70 fT1 = 28.7597MHz fT2 = 29.1008MHz fT3 = 29.3628MHz fT4 = 29.6862MHz MAX5858A toc19 -10 OUTPUT POWER (dBm) OUTPUT POWER (dBm) -20 -60 fT5 = 20.2524MHz fT6 = 20.5344MHz fT7 = 20.8365MHz fT8 = 21.1386MHz 0 MAX5858A toc18 -10 fT5 -50 21.5 8-TONE MTPR PLOT FOR NYQUIST WINDOW 8-TONE MTPR PLOT FOR NYQUIST WINDOW (4x INTERPOLATION, fDAC = 286.4MHz, fCENTER = 20MHz, (NO INTERPOLATION, fDAC = 165MHz, INPUT TONES SPACING ~ 300kHz, AOUT = -18dBFS) fCENTER = 19.9569MHz, AOUT = -18dBFS) MTPR = 76dBc fT2 -90 fT1 = 18.8022MHz fT2 = 19.0237MHz fT3 = 19.2654MHz fT4 = 19.6481MHz -1 fT6 fT4 -40 -100 28.5 -100 18.5 5.5 fT1 -30 -80 -90 -100 AOUT = -18dBFS BW = 3MHz -10 -80 -90 MAX5858A toc17 -10 -40 -70 AOUT = -18dB FS BW = 3MHz MAX5858A toc20 OUTPUT POWER (dBm) -20 0 OUTPUT POWER (dBm) fT1 = 4.9448MHz fT2 = 5.0656MHz OUTPUT POWER (dBm) AOUT = -6dBFS BW = 1MHz MAX5858A toc15 0 -10 8-TONE MTPR PLOT (4x INTERPOLATION, fDAC = 286.4MHz, fCENTER = 29.9572MHz) MAX5858A toc16 2-TONE IMD PLOT (NO INTERPOLATION, fDAC = 165MHz) -90 -90 -100 -100 28.6 1.0 15.2 57.2 42.9 85.8 71.5 114.4 143.2 100.1 128.7 OUTPUT FREQUENCY (MHz) 0 6.14MHz/div 61.44 OUTPUT FREQUENCY (MHz) _______________________________________________________________________________________ 9 Typical Operating Characteristics (continued) (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS = 20mA, differential output, TA = +25°C, unless otherwise noted.) -40 -50 -60 -70 -30 -40 -50 -60 -70 -30 -40 -50 -60 -70 -80 -80 -90 -90 -90 -100 -100 -100 0 122.88 OUTPUT FREQUENCY (MHz) FFT PLOT FOR PLL DISABLED AND PLL ENABLED (fOUT = 10MHz, 2x INTERPOLATION) NOISE DENSITY (dBm/Hz) MAX5858A toc24 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 PLL ENABLED PLL DISABLED -120 5 1MHz/div OUTPUT FREQUENCY (MHz) 10 15 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 6.14MHz/div 12.288MHz/div 0 61.44 122.88 OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) PHASE NOISE WITH PLL DISABLED AND ENABLED (fOUT = fDATA/4, 2x INTERPOLATION) INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE PLL ENABLED fDATA = 125MHz 0.5 PLL ENABLED fDATA = 100MHz 0.4 0.3 0.2 INL (LSB) 12.288MHz/div -80 MAX5858A toc25 0 ACLR = 63dB -20 MAX5858A toc26 -30 MAX5858A toc23 ACLR = 63dB -20 OUTPUT POWER (dBm) OUTPUT POWER (dBm) -20 -0 -10 OUTPUT POWER (dBm) -10 -0 -10 MAX5858A toc22 ACLR = 63dB MAX5858A toc21 -0 ACLR WITH UMTS PLOT (2x INTERPOLATION, fDAC = 245.76MHz, fDATA = 122.88MHz, fCENTER = 30.72MHz) ACLR WITH UMTS PLOT (2x INTERPOLATION, fDAC = 245.76MHz, fDATA = 122.88MHz, fCENTER = 30.72MHz) ACLR WITH UMTS PLOT (NO INTERPOLATION, fDAC = 122.88MHz, fDATA = 122.88MHz, fCENTER = 30.72MHz) OUTPUT POWER (dBm) MAX5858A Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL PLL ENABLED fDATA = 150MHz 0.1 0 -0.1 PLL DISABLED fDATA = 75MHz -0.2 -0.3 -0.4 RL = 0 -0.5 0 0 0.5MHz/div 5 150 300 450 600 750 DIGITAL INPUT CODE OFFSET FREQUENCY (MHz) ______________________________________________________________________________________ 900 1050 Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL POWER DISSIPATION vs. fDAC 0 -0.10 950 350 NO INTERPOLATION 300 2x INTERPOLATION 850 750 4x INTERPOLATION 650 550 250 -0.20 450 RL = 0 -0.30 300 450 600 750 900 68 102 136 165 0 50 100 150 200 250 fDAC (MHz) POWER DISSIPATION vs. SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 4x INTERPOLATION fCLK = 200MHz fOUT = 5MHz 700 600 500 400 NO INTERPOLATION fCLK = 165MHz fOUT = 5MHz 300 200 2.9 3.0 3.1 SUPPLY VOLTAGE (V) 3.2 3.3 1.28 1.27 1.26 1.25 1.24 1.23 1.22 1.21 1.20 1.28 300 MAX5858A toc32 MAX5858A toc30 800 2.8 34 fDAC (MHz) 2x INTERPOLATION fCLK = 200MHz fOUT = 5MHz 2.7 350 0 DIGITAL INPUT CODE 1000 900 200 1050 INTERNAL REFERENCE VOLTAGE (V) 150 INTERNAL REFERENCE VOLTAGE (V) 0 POWER DISSIPATION (mW) 400 MAX5858A toc28 fOUT = 5MHz MAX5858A toc31 INL (LSB) 0.10 1050 MAX5858A toc28 0.20 450 POWER DISSIPATION (mW) MAX5858A toc27 0.30 POWER DISSIPATION vs. fDAC POWER DISSIPATION (mW) DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE 1.27 1.26 1.25 1.24 1.23 1.22 1.21 1.20 2.7 2.8 2.9 3.0 3.1 SUPPLY VOLTAGE (V) 3.2 3.3 -40 -15 10 35 60 85 TEMPERATURE (°C) ______________________________________________________________________________________ 11 MAX5858A Typical Operating Characteristics (continued) (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS = 20mA, differential output, TA = +25°C, unless otherwise noted.) MAX5858A Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL Typical Operating Characteristics (continued) (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS = 20mA, differential output, TA = +25°C, unless otherwise noted.) DYNAMIC RESPONSE RISE TIME DYNAMIC RESPONSE FALL TIME MAX5858A toc33 MAX5858A toc34 200mV/div RL = 50Ω SINGLE ENDED 200mV/div RL = 50Ω SINGLE ENDED 10ns/div 10ns/div Pin Description PIN 1 2 12 NAME DA9/PD FUNCTION Channel A Input Data Bit 9 (MSB)/Power-Down Control Bit: 0: Enter DAC standby mode (DACEN = 0) or power up DAC (DACEN = 1). 1: Enter power-down mode. Channel A Input Data Bit 8/DAC Enable Control Bit: 0: Enter DAC standby mode with PD = 0. DA8/DACEN 1: Power up DAC with PD = 0. X: Enter power-down mode with PD = 1 (X = don’t care.) 3 DA7/F2EN Channel A Input Data Bit 7/Second Interpolation Filter Enable Bit: 0: Interpolation mode is determined by F1EN. 1: Enable 4x interpolation mode. (F1EN must equal 1.) 4 DA6/F1EN Channel A Input Data Bit 6/First Interpolation Filter Enable Bit: 0: Interpolation disable. 1: Enable 2x interpolation. 5 DA5/G3 6, 19, 47 DGND Digital Ground 7, 18, 48 DVDD Digital Power Supply. See Power Supplies, Bypassing, Decoupling, and Layout section. 8 DA4/G2 Channel A Input Data Bit 5/Channel A Gain Adjustment Bit 3 Channel A Input Data Bit 4/Channel A Gain Adjustment Bit 2 9 DA3/G1 Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 1 10 DA2/G0 Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 0 11 DA1 Channel A Input Data Bit 1 12 DA0 Channel A Input Data Bit 0 (LSB) ______________________________________________________________________________________ Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL PIN NAME FUNCTION 13 DB9 Channel B Input Data Bit 9 (MSB) 14 DB8 Channel B Input Data Bit 8 15 DB7 Channel B Input Data Bit 7 16 DB6 Channel B Input Data Bit 6 17 DB5 Channel B Input Data Bit 5 20 CLK Clock Output/Input. CLK becomes an input when the PLL is enabled. CLK is an output when the PLL is disabled. 21 IDE Interleave Data Mode Enable. When IDE is high, data for both DAC channels is written through port A (bits DA9–DA0). When IDE is low, channel A data is latched on the rising edge of CLK and channel B data is latched on the falling edge of CLK. 22 DB4 Channel B Input Data Bit 4 23 DB3 Channel B Input Data Bit 3 24 DB2 Channel B Input Data Bit 2 25 DB1 Channel B Input Data Bit 1 26 DB0 Channel B Input Data Bit 0 (LSB) 27 CW Active-Low Control-Word Write Pulse. The control word is latched on the falling edge of CW. 28 LOCK 29 PLLEN PLL Enabled Input. PLL in enabled when PLLEN is high. 30 CLKXP Differential Clock Input Positive Terminal. Connect to PGND when the PLL is enabled. Bypass CLKXP with a 0.01µF capacitor to PGND when CLKXN is in single-ended mode. 31 CLKXN Differential Clock Input Negative Terminal. Connect to PVDD when the PLL is enabled. Bypass CLKXN with a 0.01µF capacitor to PGND when CLKXP is in single-ended mode. 32 PVDD 33 PGND PLL Ground 34 PLLF PLL Loop Filter. Connect a 4.12kΩ resistor in series with a 100pF capacitor between PLLF and PGND. 35 REN Active-Low Reference Enable. Connect REN to AGND to activate the on-chip 1.24V reference. 36 REFO 37, 38 N.C. No Connection. Not connected internally. 39 REFR Full-Scale Current Adjustment. To set the output full-scale current, connect an external resistor RSET between REFR and AGND. The output full-scale current is equal to 32 × VREFO/RSET. 40, 46 AVDD Analog Power Supply. See Power Supplies, Bypassing, Decoupling, and Layout section. 41 OUTNB Channel B Negative Analog Current Output 42 OUTPB Channel B Positive Analog Current Output 43 AGND Analog Ground 44 OUTNA Channel A Negative Analog Current Output 45 OUTPA Channel A Positive Analog Current Output — EP PLL Lock Signal Output. High level indicates that PLL is locked to the CLK signal. PLL Power Supply. See Power Supplies, Bypassing, Decoupling, and Layout section. Reference I/O. REFO serves as the reference input when the internal reference is disabled. If the internal 1.24V reference is enabled, REFO serves as the output for the internal reference. When the internal reference is enabled, bypass REFO to AGND with a 0.1µF capacitor. Exposed Paddle. Connect to the ground plane. ______________________________________________________________________________________ 13 MAX5858A Pin Description (continued) Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL MAX5858A Block Diagram DVDD PVDD CLKXP AVDD CLKXN CLK LOCK PLLEN PLLF PLL CLOCK MULTIPLIER MAX5858A OUTPA 10 10 2x DIGITAL INTERPOLATION FILTER INPUT REGISTER DA9–DA0 10 2x DIGITAL INTERPOLATION FILTER 10 10-BIT 300MHz DAC OUTNA OUTPB 10 DB9–DB0 10 2x DIGITAL INTERPOLATION FILTER INPUT REGISTER 10 2x DIGITAL INTERPOLATION FILTER 10 10-BIT 300MHz DAC OUTNB IDE CW F1EN 1.2V REFERENCE AND CONTROL AMPLIFIER CONTROL REGISTER DGND F2EN PGND REFO REN REFR AGND RSET Detailed Description The MAX5858A dual, high-speed, 10-bit, current-output DAC provides superior performance in communication systems requiring low-distortion analog-signal reconstruction. The MAX5858A combines two DAC cores with 2x/4x programmable digital interpolation filters, a PLL clock multiplier, divide-by-N clock output, and an onchip 1.24V reference. The current outputs of the DACs can be configured for differential or single-ended operation. The full-scale output current range is adjustable from 2mA to 20mA to optimize power dissipation and gain control. The MAX5858A accepts an input data rate of up to 165MHz or a DAC conversion rate of up to 300MHz. The inputs are latched on the rising edge of the clock whereas the output latches on the following rising edge. The two-stage digital interpolation filters are programmable to 4x, 2x, or no interpolation. When operating in 4x interpolation mode, the interpolator increases the DAC conversion rate by a factor of four, providing a four-fold increase in separation between the reconstructed waveform spectrum and its first image. The on-chip PLL clock multiplier generates and distributes all internal, synchronized high-speed clock signals required by the input data latches, interpolation filters, 14 and DAC cores. The on-chip PLL includes phase-detector, VCO, prescalar, and charge-pump circuits. The PLL can be enabled or disabled through PLLEN. The analog and digital sections of the MAX5858A have separate power-supply inputs (AVDD and DVDD). Also, a separate supply input is provided for the PLL clock multiplier (PVDD). AVDD, DVDD, and PVDD operate from a 2.7V to 3.3V single supply. The MAX5858A features three modes of operation: normal, standby, and power-down. These modes allow efficient power management. In power-down, the MAX5858A consumes only 1µA of supply current. Wake-up time from standby mode to normal DAC operation is 0.7µs. Programming the DAC An 8-bit control word routed through channel A’s data port programs the gain matching, interpolator configuration, and operational mode of the MAX5858A. The control word is latched on the falling edge of CW. Table 1 describes the control word format and function. The gain on channel A can be adjusted to achieve gain matching between two channels in a user’s system. The gain on channel A can be adjusted from +0.4dB to -0.35dB in steps of 0.05dB by using bits G3 to G0 (see Table 3). ______________________________________________________________________________________ Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL At power-up, the MAX5858A is configured in no-interpolation mode with a gain adjustment setting of 0dB and a fully operational converter. In shutdown, the MAX5858A consumes only 1µA of supply current, and in standby the current consumption is 4.4mA. Wake-up time from standby mode to normal operation is 0.7µs. Interpolation Filters The MAX5858A features a two stage, 2x digital interpolating filter based on 43-tap and 23-tap FIR topology. F1EN and F2EN enable the interpolation filters. F1EN = 1 enables the first filter for 2x interpolation and F2EN = 2 enables the second filter for combined 4x interpolation. To bypass and disable both interpolation filters (no-interpolation mode or 1x mode) set F1EN = F2EN = 0. When set for 1x mode the filters are powered down and consume virtually no current. An illegal condition is defined by: F1EN = 0, F2EN = 1 (see Table 2 for configuration modes). The programmable interpolation filters multiply the MAX5858A input data rate by a factor of two or four to separate the reconstructed waveform spectrum and the first image. The original spectral images, appearing around multiples of the DAC input data rate, are attenuated at least 60dB by the internal digital filters. This feature provides three benefits: 1) Image separation reduces complexity of analog reconstruction filters. 2) Lower input data rates eliminate board level highspeed data transmission. 3) Sin(x)/x roll-off is reduced over the effective bandwidth. Figure 2 shows an application circuit and Figure 3 illustrates a practical example of the benefits when using the MAX5858A with 4x-interpolation mode. The example illustrates signal synthesis of a 20MHz IF with a ±10MHz bandwidth. Three options can be considered to address the design requirements. The tradeoffs for each solution are depicted in Table 4. Table 1. Control Word Format and Function MSB LSB PD DACEN F2EN F1EN G3 CONTROL WORD PD DACEN G2 G1 G0 X X FUNCTION Power-down: The part enters power-down mode if PD = 1. DAC Enable: When DACEN = 0 and PD = 0, the part enters standby mode. F2EN Filter Enable: When F2EN = 1 and F1EN = 1, 4x interpolation is enabled. When F2EN = 0, the interpolation mode is determined by F1EN. F1EN Filter Enable: When F1EN = 1 and F2EN = 0, 2x interpolation is active. With F1EN = 0 and F2EN = 0, the interpolation is disabled. G3 Bit 3 (MSB) of gain adjust word. G2 Bit 2 of gain adjust word. G1 Bit 1 of gain adjust word. G0 Bit 0 (LSB) of gain adjust word. Table 3. Gain Difference Setting Table 2. Configuration Modes MODE PD DACEN F2EN F1EN No interpolation 0 1 0 2x interpolation 0 1 4x interpolation 0 1 G3 G2 G1 G0 0 GAIN ADJUSTMENT ON CHANNEL A (dB) 0 1 +0.4 0 0 0 0 1 1 0 1 0 0 0 -0.35 1 1 1 1 Standby 0 0 X X Power-down 1 X X X Power-up 0 1 X X X = Don’t care. F1EN = 0, F2EN = 1: illegal condition ______________________________________________________________________________________ 15 MAX5858A Device Power-Up and States of Operation MAX5858A Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL FS ANALOG OUT MAINTAINED OVER ENTIRE SUPPLY RANGE 2.7V TO 3.3V SINGLE SUPPLY 2.7V TO 3.3V SINGLE 10-BIT BUS SAVES I/O PINS DIGITAL BASEBAND OFDM PROCESSOR QAM-MAPPER DATA LATCH 10-BIT BUS INTERPOLATING FILTERS 4x/2x 10 DATA LATCH 10-BIT BUS INTERPOLATING FILTERS 4x/2x 10 CHA DAC AOUT CHB DAC BOUT INTERLEAVE DATA LATCH DIV-4 DIV-2 DIV-1 MAX5858A DATA CLOCK OUT fDATA = 71.6MHz CLOCK SOURCE fDAC = 286.4MHz Figure 2. Typical Application Circuit Table 4. Benefits of Interpolation OPTION 16 SOLUTION ADVANTAGE DISADVANTAGE 1 • No interpolation • 2.6x oversample • fDAC = fDATA = 78MHz • Low data rate • Low clock rate • High order filter • Filter gain/phase match 2 • • • • No interpolation 8x oversample fDAC = fDATA = 240MHz Push image to fIMAGE = 210MHz • Lower order filter • Filter gain/phase match • High clock rate • High data rate 3 • • • • 4x interpolation fDAC = 286.4MHz, fDATA = 71.6MHz Passband attenuation = 0.1dB Push image to 256MHz • • • • • None Low data rate Low order filter 60dB image attenuate Filter gain/phase match ______________________________________________________________________________________ Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL MAX5858A IMAGE SEPARATION = 18MHz LESS THAN ONE OCTAVE HIGH ORDER ANALOG FILTER SOLUTION 1 fOUT 20MHz ±10MHz IMAGE fDAC - fOUT 48MHz fDAC 78MHz IMAGE fDAC + fOUT 108MHz FREQUENCY AXIS NOT TO SCALE SOLUTION 2 LOWER ORDER ANALOG FILTER fOUT 20MHz BW = ±10MHz IMAGE SEPARATION = 180MHz HIGH-SPEED CLK = 240MHz fDAC IMAGE IMAGE fDAC - fOUT 240MHz fDAC + fOUT 210MHz 270MHz FREQUENCY AXIS NOT TO SCALE SOLUTION 3 SIMPLE ANALOG FILTER NEW FIRST IMAGE SEPARATION > 3 OCTAVES DIGITAL FILTER ATTENUATION >60dB fDATA 71.6MHz fOUT 20MHz BW = ±10MHz fDAC IMAGE IMAGE fDAC - fOUT 286MHz fDAC + fOUT 256MHz 316MHz FREQUENCY AXIS NOT TO SCALE Figure 3. MAX5858A in 4x Interpolation Mode This example demonstrates that 4x interpolation with digital filtering yields significant benefits in reducing system complexity, improving dynamic performance and lowering cost. Data can be written to the MAX5858A at much lower speeds while achieving image attenuation greater than 60dB and image separation beyond three octaves. The main benefit is in analog reconstruction fil- ter design. Reducing the filter order eases gain/phase matching while lowering filter cost and saving board space. Because the data rate is lowered to 71.6MHz, the setup and hold times are manageable and the clock signal source is simplified, which results in improved system reliability and lower cost. ______________________________________________________________________________________ 17 MAX5858A Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL PLL Clock Multiplier and Clocking Modes The MAX5858A features an on-chip PLL clock multiplier that generates all internal, synchronized high-speed clock signals required by the input data latches, interpolation filters, and DAC cores. The on-chip PLL includes a phase-detector, VCO, prescalar, and charge-pump circuits. The PLL can be enabled or disabled through PLLEN. To enable PLL set PLLEN = 1. With the PLL enabled (PLLEN = 1) and 4x/2x interpolation enabled, an external low-frequency clock reference source is applied to CLK pin. The clock reference source serves as the input data clock. The on-chip PLL multiplies the clock reference by a factor of two (2x) or a factor of four (4x). The input data rate range and CLK frequency are set by the selected interpolation mode. In 2x interpolation mode, the data rate range is 75MHz to 150MHz. In 4x interpolation mode the data rate range is 37.5MHz to 75MHz. Note: When the PLL is enabled, CLK becomes an input, requiring CLKXP to be pulled low and CLKXN to be pulled high. To obtain best phase noise performance, disable the PLL function. With the PLL disabled (PLLEN = 0) and 4x/2x interpolation enabled, an external conversion clock is applied at CLKXN/CLKXP. The conversion clock at CLKXN/CLKXP has a frequency range of 0MHz to 300MHz (see Table 5). This clock is buffered and distributed by the MAX5858A to drive the interpolation filters and DAC cores. In this mode, CLK becomes a divide-by-N (DIVN) output at either a divide-by-two or divide-by-four rate. The DIV-N factor is set by the selected interpolation mode. The CLK output, at DIV-N rate, must be used to synchronize data into the MAX5858A data ports. In this mode, keep the capacitive load at the CLK output low (10pF or less at fDAC = 165MHz). With the interpolation disabled (1x mode) and the PLL disabled (PLLEN = 0), the input clock at CLKXN/CLKXP can be used to directly update the DAC cores. In this mode, the maximum data rate is 165MHz. Internal Reference and Control Amplifier The MAX5858A provides an integrated 50ppm/°C, 1.24V, low-noise bandgap reference that can be disabled and overridden with an external reference voltage. REFO serves either as an external reference input or an integrated reference output. If REN is connected to AGND, the internal reference is selected and REFO provides a 1.24V (50µA) output. Buffer REFO with an external amplifier, when driving a heavy load. The MAX5858A also employs a control amplifier designed to simultaneously regulate the full-scale output current (I FS ) for both outputs of the devices. Calculate the output current as: IFS = 32 ✕ IREF where I REF is the reference output current (I REF = VREFO/RSET) and IFS is the full-scale output current. RSET is the reference resistor that determines the amplifier output current of the MAX5858A (Figure 4). This current is mirrored into the current-source array where IFS is equally distributed between matched current segments and summed to valid output current readings for the DACs. OPTIONAL EXTERNAL BUFFER FOR HEAVIER LOADS REN AGND 1.24V BANDGAP REFERENCE MAX4040 REFO CCOMP* REFR AGND IREF = *COMPENSATION CAPACITOR (CCOMP ≈ 100nF). CURRENTSOURCE ARRAY IREF VREF RSET RSET AGND MAX5858A Figure 4. Setting IFS with the Internal 1.24V Reference and the Control Amplifier 18 ______________________________________________________________________________________ IFS Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL Detailed Timing The MAX5858A accepts an input data rate up to 165MHz or the DAC conversion rate of 300MHz. The input latches on the rising edge of the clock, whereas the output latches on the following rising edge. AVDD 10µF REN 0.1µF AGND 1.24V BANDGAP REFERENCE AVDD EXTERNAL 1.24V REFERENCE REFO CURRENTSOURCE ARRAY REFR MAX6520 IFS IREF AGND RSET MAX5858A AGND Figure 5. MAX5858A with External Reference Table 5. PLL Clocking Modes PLLEN F2EN F1EN DIFFERENTIAL CLOCK FREQUENCY fCLKDIFF (MHz) CLOCK FREQUENCY fCLK (MHz) DAC RATE fDAC INTERPOLATION MAX SIGNAL BANDWIDTH (MHz) 1 0 0 N/A (connect CLXP low and CLXN high) 0 to 165 (input) fCLK 1x 82 1 0 1 N/A (connect CLXP low and CLXN high) 75 to 150 (input) 2 x fCLK 2x 63 1 1 1 N/A (connect CLXP low and CLXN high) 37 to 75 (input) 4 x fCLK 4x 31 0 0 0 0 to 165 fCLKDIFF (output) fCLKDIFF 1x 82 0 0 1 0 to 300 fCLKDIFF /2 (output) fCLKDIFF 2x 63 0 1 1 0 to 300 fCLKDIFF /4 (output) fCLKDIFF 4x 31 0 1 0 1 1 0 Illegal ______________________________________________________________________________________ 19 MAX5858A External Reference To disable the internal reference of the MAX5858A, connect REN to AVDD. Apply a temperature-stable, external reference to REFO to set the full-scale output (Figure 5). For improved accuracy and drift performance, choose a fixed output voltage reference such as the MAX6520 bandgap reference. MAX5858A Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL Figure 6 depicts the write cycle of the MAX5858A in 4x interpolation mode. With the interpolation feature enabled, the device can operate with the PLL enabled or disabled. With the PLL disabled (PLLEN = 0), the clock signal is applied to CLKXP/CLKXN and internally divided by 4 to generate the DAC’s CLK signal. The CLK signal is a divide-by-four output used to synchronize data into the MAX5858A data ports. The CLKXP/CLKXN signal drives the interpolation filters and DAC cores at the desired conversion rate. If the PLL is enabled (PLLEN = 1), CLK becomes an input and the clock signal is applied to CLK. In Figure 6, the CLK signal is multiplied by a factor of four by the PLL and distributed to the interpolation filters and DAC cores. In this mode, CLKXP must be pulled low and CLKXN pulled high. The MAX5858A can operate with a single-ended clock input used as both data clock and conversion clock. To operate the device in this mode, disable the interpolation filters and enable the PLL (PLLEN = 1). Apply a singleended clock input at CLK. The CLK signal acts as the data synchronization clock and DAC core conversion clock. Though the PLL is enabled, the lock pin (LOCK) is not valid and the PLL is internally disconnected from interpolating filters and DAC cores. In this mode, CLKXP must be pulled low and CLKXN pulled high. Figure 6 shows the timing for the control word write pulse (CW). An 8-bit control word routed through channel A’s data port programs the gain matching, interpolator configuration, and operational mode of the MAX5858A. The control word is latched on the falling edge of CW. The CW signal is asynchronous with conversion clocks CLK and CLKXN/CLKXP; therefore, the conversion clock (CLK or CLKXN/CLKXP) can run uninterrupted when a control word is written to the device. CLKXN1 tCXD tCXD CLKXP1 tCWH CW tCWS CLK 2 DA0–DA9/ CONTROL WORD DAN DB0–DB9 DBN CONTROL WORD DAN+1 DBN+1 tDCSR 1. CLKXP AND CLKXN MUST BE PRESENT WHEN PLL IS DISABLED, WITH PLLEN CONNECTED TO GND. THE DIAGRAM SHOWS 4x INTERPOLATION. 2. CLK IS AN OUTPUT WHEN PLL IS DISABLED WITH PLLEN CONNECTED TO GND, OTHERWISE, IT IS AN INPUT. Figure 6. Timing Diagram for Noninterleave Data Mode (IDE = Low) 20 ______________________________________________________________________________________ tDCHR Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL MAX5858A CLKXN1 tCXD CLKXP CLK tCXD 1 2 DA0–DA9 DAN tDCSR DBN+1 tDCSF DAN+1 DBN+2 DAN+2 tDCHF tDCHR 1. CLKXP AND CLKXN MUST BE PRESENT WHEN PLL IS DISABLED, WITH PLLEN CONNECTED TO GND. THE DIAGRAM SHOWS 4x INTERPOLATION. 2. CLK IS AN OUTPUT WHEN PLL IS DISABLED WITH PLLEN CONNECTED TO GND, OTHERWISE, IT IS AN INPUT. Figure 7. Timing Diagram for Interleave Data Mode (IDE = High) The MAX5858A can operate in interleave data mode by setting IDE = 1. In interleave data mode, data for both DAC channels is written through input port A. Channel B data is written on the falling edge of the CLK signal and then channel A data is written on the following rising edge of the CLK signal. Both DAC outputs (channel A and B) are updated simultaneously on the next rising edge of CLK. In interleave data mode, the maximum input data rate per channel is one-half the rate of noninterleave mode. Interleave data mode is an attractive feature that lowers digital I/O pin count, reduces digital ASIC cost and improves system reliability (Figure 7). AVDD DVDD PVDD 50Ω OUTPA DA0–DA9 VOUTA, SINGLE ENDED 1/2 100Ω MAX5858A 10 OUTNA 50Ω Applications Information Differential-to-Single-Ended Conversion The MAX5858A exhibits excellent dynamic performance to synthesize a wide variety of modulation schemes, including high-order QAM modulation with OFDM. Figure 8 shows a typical application circuit with output transformers performing the required differential-to-single-ended signal conversion. In this configuration, the MAX5858A operates in differential mode, which reduces even-order harmonics, and increases the available output power. 50Ω OUTPB DB0–DB9 VOUTB, SINGLE ENDED 1/2 100Ω 10 MAX5858A OUTNB 50Ω AGND DGND PGND Figure 8. Application with Output Transformer Performing Differential to Single-Ended Conversion ______________________________________________________________________________________ 21 MAX5858A Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL Differential DC-Coupled Configuration Figure 9 shows the MAX5858A output operating in differential, DC-coupled mode. This configuration can be used in communication systems employing analog quadrature upconverters and requiring a baseband sampling, dual-channel, high-speed DAC for I/Q synthesis. In these applications, information bandwidth can extend from 10MHz down to several hundred kilohertz. DC-coupling is desirable in order to eliminate long discharge time constants that are problematic with large, expensive coupling capacitors. Analog quadrature upconverters have a DC common-mode input requirement of typically 0.7V to 1.0V. The MAX5858A differential I/Q outputs can maintain the desired full-scale original level at the required 0.7V to 1.0V DC common-mode voltage when powered from a single 2.85V (±5%) supply. The MAX5858A meets this low-power requirement with minimal reduction in dynamic range while eliminating the need for level-shifting resistor networks. AVDD DVDD PVDD 50Ω DA0–DA9 OUTPA 1/2 MAX5858A 10 OUTNA 50Ω 50Ω DB0–DB9 OUTPB 1/2 MAX5858A 10 OUTNB Power Supplies, Bypassing, Decoupling, and Layout Grounding and power-supply decoupling strongly influence the MAX5858A performance. Unwanted digital crosstalk can couple through the input, reference, power-supply, and ground connections, which can affect dynamic specifications, like signal-to-noise ratio or spurious-free dynamic range. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX5858A. Observe the grounding and power-supply decoupling guidelines for highspeed, high-frequency applications. Follow the power supply and filter configuration to achieve optimum dynamic performance. Use of a multilayer printed circuit (PC) board with separate ground and power-supply planes is recommended. Run high-speed signals on lines directly above the ground plane. The MAX5858A has separate analog and digital ground buses (AGND, PGND, and DGND, respectively). Provide separate analog, digital, and clock ground sections on the PC board with only one point connecting the three planes. The ground connection points should be located underneath the device and connected to the exposed paddle. Run digital signals above the digital ground plane and analog/clock signals above the analog/clock ground plane. Digital signals should be kept away from sensitive analog, clock, and reference inputs. Keep digital signal paths short and metal trace lengths matched to avoid propagation delay and data skew mismatch. 22 50Ω AGND DGND PGND Figure 9. Application with DC-Coupled Differential Outputs The MAX5858A includes three separate power-supply inputs: analog (AV DD ), digital (DV DD ), and clock (PVDD). Use a single linear regulator power source to branch out to three separate power-supply lines (AVDD, DVDD, PVDD) and returns (AGND, DGND, PGND). Filter each power-supply line to the respective return line using LC filters comprising ferrite beads and 10µF capacitors. Filter each supply input locally with 0.1µF ceramic capacitors to the respective return lines. Note: To maintain the dynamic performance of the Electrical Characteristics, ensure the voltage difference between DVDD, AVDD, and PVDD does not exceed 150mV. Thermal Characteristics and Packaging Thermal Resistance 48-lead TQFP-EP: θJA = 27.6°C/W Keep the device junction temperature below +125°C to meet specified electrical performance. Lower the power-supply voltage to maintain specified performance when the DAC update rate approaches 300Msps and the ambient temperature equals +85°C. ______________________________________________________________________________________ Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL In this package, the data converter die is attached to an EP leadframe with the back of the frame exposed at the package bottom surface, facing the PC board side of the package. This allows a solid attachment of the package to the PC board with standard infrared (IR)flow soldering techniques. A specially created land pattern on the PC board, matching the size of the EP, ensures the proper attachment and grounding of the DAC. Designing vias* into the land area and implementing large ground planes in the PC board design achieve optimal DAC performance. Use an array of 3 ✕ 3 (or greater) vias (0.3mm diameter per via hole and 1.2mm pitch between via holes) for this 48-pin TQFPEP package. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of the next-largest spectral component. SFDR is usually measured in dBc with respect to the carrier frequency amplitude or in dB FS with respect to the DAC’s fullscale range. Depending on its test condition, SFDR is observed within a predefined window or to Nyquist. Multitone Power Ratio (MTPR) A series of equally spaced tones are applied to the DAC with one tone removed from the center of the range. MTPR is defined as the worst-case distortion (usually a 3rd-order harmonic product of the fundamental frequencies), which appears as the largest spur at the frequency of the missing tone in the sequence. This test can be performed with any number of input tones; however, four and eight tones are among the most common test conditions for CDMA- and GSM/EDGE-type applications. Intermodulation Distortion (IMD) Dynamic Performance Parameter Definitions The two-tone IMD is the ratio expressed in dBc of either output tone to the worst 3rd-order (or higher) IMD products. Adjacent Channel Leakage Ratio (ACLR) Commonly used in combination with wideband codedivision multiple-access (WCDMA), ACLR reflects the leakage power ratio in dB between the measured power within a channel relative to its adjacent channel. ACLR provides a quantifiable method of determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited RF signal passes through a nonlinear device. Static Performance Parameter Definitions Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of all essential harmonics (within a Nyquist window) of the input signal to the fundamental itself. This can be expressed as: THD = 20 × log V22 + V32 + V4 2... + ...VN2 / V1 Integral Nonlinearity (INL) Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between an actual step height and the ideal value of 1 LSB. A DNL error specification no more negative than -1 LSB guarantees monotonic transfer function. Offset Error Offset error is the current flowing from positive DAC output when the digital input code is set to zero. Offset error is expressed in LSBs. where V1 is the fundamental amplitude, and V2 through VN are the amplitudes of the 2nd through Nth-order harmonics. *Vias connect the land pattern to internal or external copper planes. ______________________________________________________________________________________ 23 MAX5858A The MAX5858A is packaged in a 48-pin TQFP-EP package, providing design flexibility, increased thermal efficiency, and optimized AC performance of the DAC. The EP enables the implementation of grounding techniques, which are necessary to ensure highest performance operation. MAX5858A Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL Gain Error A gain error is the difference between the ideal and the actual full-scale output current on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. The ideal current is defined by reference voltage at VREFO / IREF x 32. Settling Time The settling time is the amount of time required from the start of a transition until the DAC output settles to its new output value to within the converter’s specified accuracy. 24 Glitch Impulse A glitch is generated when a DAC switches between two codes. The largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011…111 to 100…000. This occurs due to timing variations between the bits. The glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. The glitch impulse is usually specified in pV-s. Chip Information TRANSISTOR COUNT: 178,376 PROCESS: CMOS ______________________________________________________________________________________ Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x Interpolation Filters and PLL 48L,TQFP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX5858A Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)