ADS7843 SBAS090B – SEPTEMBER 2000 – REVISED MAY 2002 TOUCH SCREEN CONTROLLER FEATURES DESCRIPTION ● 4-WIRE TOUCH SCREEN INTERFACE The ADS7843 is a 12-bit sampling Analog-to-Digital Converter (ADC) with a synchronous serial interface and low onresistance switches for driving touch screens. Typical power dissipation is 750µW at a 125kHz throughput rate and a +2.7V supply. The reference voltage (VREF) can be varied between 1V and +VCC, providing a corresponding input voltage range of 0V to VREF. The device includes a shutdown mode which reduces typical power dissipation to under 0.5µW. The ADS7843 is specified down to 2.7V operation. ● RATIOMETRIC CONVERSION ● SINGLE SUPPLY: 2.7V to 5V ● UP TO 125kHz CONVERSION RATE ● ● ● ● SERIAL INTERFACE PROGRAMMABLE 8- OR 12-BIT RESOLUTION 2 AUXILIARY ANALOG INPUTS FULL POWER-DOWN CONTROL Low power, high speed, and onboard switches make the ADS7843 ideal for battery-operated systems such as personal digital assistants with resistive touch screens and other portable equipment. The ADS7843 is available in an SSOP-16 package and is specified over the –40°C to +85°C temperature range. APPLICATIONS ● ● ● ● ● PERSONAL DIGITAL ASSISTANTS PORTABLE INSTRUMENTS POINT-OF-SALES TERMINALS PAGERS TOUCH SCREEN MONITORS US Patent No. 6246394 PENIRQ +VCC X+ X– SAR DCLK Y+ Y– Four Channel Multiplexer CS Comparator CDAC IN3 IN4 Serial Interface and Control DIN DOUT BUSY VREF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) +VCC to GND ........................................................................ –0.3V to +6V Analog Inputs to GND ............................................ –0.3V to +VCC + 0.3V Digital Inputs to GND ............................................. –0.3V to +VCC + 0.3V Power Dissipation .......................................................................... 250mW Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ........................................ –40°C to +85°C Storage Temperature Range ......................................... –65°C to +150°C Lead Temperature (soldering, 10s) ............................................... +300°C NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR (LSB) ADS7843E " PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE ±2 SSOP-16 DBQ –40°C to +85°C " " " " PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS7843E ADS7843E ADS7843E ADS7843E/2K5 Rails, 100 Tape and Reel, 2500 NOTES: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PIN CONFIGURATION PIN DESCRIPTION Top View 2 SSOP PIN NAME +VCC X+ Y+ X– Y– GND IN3 IN4 VREF +VCC PENIRQ +VCC 1 16 DCLK X+ 2 15 CS Y+ 3 14 DIN X– 4 13 BUSY 12 DOUT 1 2 3 4 5 6 7 8 9 10 11 12 DOUT 13 BUSY 14 DIN 15 CS 16 DCLK ADS7843 Y– 5 GND 6 11 PENIRQ IN3 7 10 +VCC IN4 8 9 VREF DESCRIPTION Power Supply, 2.7V to 5V. X+ Position Input. ADC input Channel 1. Y+ Position Input. ADC input Channel 2. X– Position Input Y– Position Input Ground Auxiliary Input 1. ADC input Channel 3. Auxiliary Input 2. ADC input Channel 4. Voltage Reference Input Power Supply, 2.7V to 5V. Pen Interrupt. Open anode output (requires 10kΩ to 100kΩ pull-up resistor externally). Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high impedance when CS is HIGH. Busy Output. This output is high impedance when CS is HIGH. Serial Data Input. If CS is LOW, data is latched on rising edge of DCLK. Chip Select Input. Controls conversion timing and enables the serial input/output register. External Clock Input. This clock runs the SAR conversion process and synchronizes serial data I/O. ADS7843 www.ti.com SBAS090B ELECTRICAL CHARACTERISTICS At TA = –40°C to +85°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, fCLK = 16 • fSAMPLE = 2MHz, 12-bit mode, and digital inputs = GND or +VCC, unless otherwise noted. ADS7843E PARAMETER ANALOG INPUT Full-Scale Input Span Absolute Input Range CONDITIONS MIN Positive Input – Negative Input Positive Input Negative Input 0 –0.2 –0.2 Capacitance Leakage Current VREF +VCC +0.2 +0.2 V V V pF µA 12 0.1 0.1 30 70 ±2 ±6 1.0 ±4 1.0 12 500 30 100 100 5 6 Ω Ω 125 VIN = 2.5Vp-p at 50kHz 1.0 CS = GND or +VCC Bits Bits LSB(1) LSB LSB LSB LSB µVrms dB Clk Cycles Clk Cycles kHz ns ns ps dB 3 +VCC 5 13 2.5 0.001 fSAMPLE = 12.5kHz CS = +VCC DIGITAL INPUT/OUTPUT Logic Family Logic Levels, Except PENIRQ VIH VIL VOH VOL PENIRQ VOL Data Format UNITS 11 SWITCH DRIVERS On-Resistance Y+, X+ Y–, X– REFERENCE INPUT Range Resistance Input Current MAX 25 0.1 SYSTEM PERFORMANCE Resolution No Missing Codes Integral Linearity Error Offset Error Offset Error Match Gain Error Gain Error Match Noise Power-Supply Rejection SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Multiplexer Settling Time Aperture Delay Aperture Jitter Channel-to-Channel Isolation TYP 40 3 V GΩ µA µA µA CMOS | IIH | ≤ +5µA | IIL | ≤ +5µA IOH = –250µA IOL = 250µA +VCC • 0.7 –0.3 +VCC • 0.8 +VCC +0.3 +0.8 TA = 0°C to +85°C, 100kΩ Pull-Up 0.4 V V V 0.8 V 3.6 650 3 V µA µA µA 1.8 mW +85 °C Straight Binary POWER-SUPPLY REQUIREMENTS +VCC Quiescent Current Power Dissipation Specified Performance 2.7 280 220 fSAMPLE = 12.5kHz Shutdown Mode with DCLK = DIN = +VCC +VCC = +2.7V TEMPERATURE RANGE Specified Performance –40 NOTE: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, 1LSB is 610µV. ADS7843 SBAS090B 3 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. POWER-DOWN SUPPLY CURRENT vs TEMPERATURE 400 140 350 120 Supply Current (nA) Supply Current (µA) SUPPLY CURRENT vs TEMPERATURE 300 250 200 100 80 60 40 150 20 100 –40 –20 0 20 60 40 80 –40 100 –20 0 20 40 60 80 100 Temperature (°C) Temperature (°C) SUPPLY CURRENT vs +VCC MAXIMUM SAMPLE RATE vs +VCC 320 1M 300 Sample Rate (Hz) Supply Current (µA) fSAMPLE = 12.5kHz 280 VREF = +VCC 260 240 220 100k 10k VREF = +VCC 200 180 1k 2 2.5 3.5 3 4 4.5 5 2 2.5 3 +VCC (V) 0.15 0.6 0.10 0.4 Delta from +25˚C (LSB) Delta from +25˚C (LSB) 4 4.5 5 CHANGE IN OFFSET vs TEMPERATURE CHANGE IN GAIN vs TEMPERATURE 0.05 0.00 –0.05 0.2 0.0 –0.2 –0.4 –0.10 –0.6 –0.15 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 Temperature (°C) Temperature (°C) 4 3.5 +VCC (V) ADS7843 www.ti.com SBAS090B TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. REFERENCE CURRENT vs TEMPERATURE 18 12 16 Reference Current (µA) Reference Current (µA) REFERENCE CURRENT vs SAMPLE RATE 14 10 8 6 4 14 12 10 8 2 6 0 0 25 50 75 100 –40 125 –20 0 20 40 60 80 Sample Rate (kHz) Temperature (°C) SWITCH-ON RESISTANCE vs +VCC (X+, Y+: +VCC to Pin; X–, Y–: Pin to GND) SWITCH-ON RESISTANCE vs TEMPERATURE (X+, Y+: +VCC to Pin; X–, Y–: Pin to GND) 8 100 8 Y– 7 7 Y– X– 6 X– RON (Ω) RON (Ω) 6 5 4 5 Y+ 4 X+ Y+ 3 3 X+ 2 2 1 1 2 2.5 3 3.5 4 4.5 5 –40 0 –20 +VCC (V) 20 40 60 80 100 Temperature (°C) MAXIMUM SAMPLING RATE vs RIN 2 1.8 INL: R = 2k INL: R = 500 DNL: R = 2k DNL: R = 500 1.6 LSB Error 1.4 1.2 1 0.8 0.6 0.4 0.2 0 20 40 60 80 100 120 140 Sampling Rate (kHz) ADS7843 SBAS090B 160 180 200 5 www.ti.com THEORY OF OPERATION ANALOG INPUT The ADS7843 is a classic Successive Approximation Register (SAR) ADC. The architecture is based on capacitive redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a 0.6µs CMOS process. The basic operation of the ADS7843 is shown in Figure 1. The device requires an external reference and an external clock. It operates from a single supply of 2.7V to 5.25V. The external reference can be any voltage between 1V and +VCC. The value of the reference voltage directly sets the input range of the converter. The average reference input current depends on the conversion rate of the ADS7843. The analog input to the converter is provided via a fourchannel multiplexer. A unique configuration of low on-resistance switches allows an unselected ADC input channel to provide power and an accompanying pin to provide ground for an external device. By maintaining a differential input to the converter and a differential reference architecture, it is possible to negate the switch’s on-resistance error (should this be a source of error for the particular measurement). See Figure 2 for a block diagram of the input multiplexer on the ADS7843, the differential input of the ADC, and the converter’s differential reference. Table I and Table II show the relationship between the A2, A1, A0, and SER/DFR control bits and the configuration of the ADS7843. The control bits are provided serially via the DIN pin—see the Digital Interface section of this data sheet for more details. When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs (see Figure 2) is captured on the internal capacitor array. The input current on the analog inputs depends on the conversion rate of the device. During the sample period, the source must charge the internal sampling capacitor (typically 25pF). After the capacitor has been fully charged, there is no further input current. The rate of charge transfer from the analog source to the converter is a function of conversion rate. +2.7V to +5V 1µF + to 10µF (Optional) ADS7843 0.1µF Touch Screen Auxiliary Inputs Serial/Conversion Clock 1 +VCC DCLK 16 2 X+ CS 15 3 Y+ DIN 14 4 X– BUSY 13 Converter Status 5 Y– DOUT 12 Serial Data Out 6 GND 7 IN3 +VCC 10 8 IN4 VREF Chip Select Serial Data In Pen Interrupt PENIRQ 11 100kΩ (optional) 9 0.1µF FIGURE 1. Basic Operation of the ADS7843. A2 A1 A0 X+ 0 1 0 1 0 0 1 1 1 1 0 0 +IN Y+ IN3 IN4 –IN(1) X SWITCHES Y SWITCHES +REF(1) –REF(1) +IN GND GND GND GND OFF ON OFF OFF ON OFF OFF OFF +VREF +VREF +VREF +VREF GND GND GND GND +IN +IN NOTE: (1) Internal node, for clarification only—not directly accessible by the user. TABLE I. Input Configuration, Single-Ended Reference Mode (SER/DFR HIGH). A2 A1 A0 X+ 0 1 0 1 0 0 1 1 1 1 0 0 +IN Y+ IN3 IN4 –IN(1) X SWITCHES Y SWITCHES +REF(1) –REF(1) +IN –Y –X GND GND OFF ON OFF OFF ON OFF OFF OFF +Y +X +VREF +VREF –Y –X GND GND +IN +IN NOTE: (1) Internal node, for clarification only—not directly accessible by the user. TABLE II. Input Configuration, Differential Reference Mode (SER/DFR LOW). 6 ADS7843 www.ti.com SBAS090B PENIRQ +VCC VREF A2-A0 (Shown 001B) SER/DFR (Shown HIGH) X+ X– Y+ +IN +REF CONVERTER Y– –IN –REF IN3 IN4 GND FIGURE 2. Simplified Diagram of Analog Input. REFERENCE INPUT The voltage difference between +REF and –REF (shown in Figure 2) sets the analog input range. The ADS7843 will operate with a reference in the range of 1V to +VCC. There are several critical items concerning the reference input and its wide voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output code is also reduced. This is often referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 4096. Any offset or gain error inherent in the ADC will appear to increase, in terms of LSB size, as the reference voltage is reduced. For example, if the offset of a given converter is 2LSBs with a 2.5V reference, it will typically be 5LSBs with a 1V reference. In each case, the actual offset of the device is the same, 1.22mV. With a lower reference voltage, more care must be taken to provide a clean layout including adequate bypassing, a clean (low noise, low ripple) power supply, a lownoise reference, and a low-noise input signal. the ADS7843 as shown in Figure 1. This particular application shows the device being used to digitize a resistive touch screen. A measurement of the current Y position of the pointing device is made by connecting the X+ input to the ADC, turning on the Y+ and Y– drivers, and digitizing the voltage on X+ (shown in Figure 3). For this measurement, the resistance in the X+ lead does not affect the conversion (it does affect the settling time, but the resistance is usually small enough that this is not a concern). +VCC Y+ The voltage into the VREF input is not buffered and directly drives the Capacitor Digital-to-Analog Converter (CDAC) portion of the ADS7843. Typically, the input current is 13µA with VREF = 2.7V and fSAMPLE = 125kHz. This value will vary by a few microamps depending on the result of the conversion. The reference current diminishes directly with both conversion rate and reference voltage. As the current from the reference is drawn on each bit decision, clocking the converter more quickly during a given conversion period will not reduce overall current drain from the reference. There is also a critical item regarding the reference when making measurements where the switch drivers are on. For this discussion, it’s useful to consider the basic operation of X+ +IN +REF Converter –IN –REF Y– GND FIGURE 3. Simplified Diagram of Single-Ended Reference (SER/DFR HIGH, Y Switches Enabled, X+ is Analog Input). ADS7843 SBAS090B VREF 7 www.ti.com However, since the resistance between Y+ and Y– is fairly low, the on-resistance of the Y drivers does make a small difference. Under the situation outlined so far, it would not be possible to achieve a 0V input or a full-scale input regardless of where the pointing device is on the touch screen because some voltage is lost across the internal switches. In addition, the internal switch resistance is unlikely to track the resistance of the touch screen, providing an additional source of error. switches. Note that there is an important consideration regarding power dissipation when using the ratiometric mode of operation, see the Power Dissipation section for more details. As a final note about the differential reference mode, it must be used with +VCC as the source of the +REF voltage and cannot be used with VREF. It is possible to use a high precision reference on VREF and single-ended reference mode for measurements which do not need to be ratiometric. Or, in some cases, it could be possible to power the converter directly from a precision reference. Most references can provide enough power for the ADS7843, but they might not be able to supply enough current for the external load (such as a resistive touch screen). This situation can be remedied as shown in Figure 4. By setting the SER/DFR bit LOW, the +REF and –REF inputs are connected directly to Y+ and Y–. This makes the A/D conversion ratiometric. The result of the conversion is always a percentage of the external resistance, regardless of how it changes in relation to the on-resistance of the internal DIGITAL INTERFACE +VCC Figure 5 shows the typical operation of the ADS7843’s digital interface. This diagram assumes that the source of the digital signals is a microcontroller or digital signal processor with a basic serial interface. Each communication between the processor and the converter consists of eight clock cycles. One complete conversion can be accomplished with three serial communications, for a total of 24 clock cycles on the DCLK input. Y+ +IN X+ +REF The first eight clock cycles are used to provide the control byte via the DIN pin. When the converter has enough information about the following conversion to set the input multiplexer, switches, and reference inputs appropriately, the converter enters the acquisition (sample) mode and, if needed, the internal switches are turned on. After three more clock cycles, the control byte is complete and the converter enters the conversion mode. At this point, the input sample-and-hold goes into the hold mode and the internal switches may turn off. The Converter –IN –REF Y– GND FIGURE 4. Simplified Diagram of Differential Reference (SER/ DFR LOW, Y Switches Enabled, X+ is Analog Input). CS tACQ DCLK DIN 1 S 8 A2 A1 1 8 1 8 A0 MODE SER/ DFR PD1 PD0 (START) Idle Acquire Conversion Idle BUSY DOUT 11 10 9 8 7 6 5 4 3 (MSB) X/Y SWITCHES(1) (SER/DFR HIGH) OFF X/Y SWITCHES(1, 2) (SER/DFR LOW) OFF 2 1 0 Zero Filled... (LSB) ON OFF ON OFF NOTES: (1) Y Drivers are on when X+ is selected input channel (A2-A0 = 001B), X Drivers are on when Y+ is selected input channel (A2-A0 = 101B). Y– will turn on when power-down mode is entered and PD1, PD0 = 00B. (2) Drivers will remain on if power-down mode is 11B (no power-down) until selected input channel, reference mode, or power-down mode is changed. FIGURE 5. Conversion Timing, 24 Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required with Dedicated Serial Port. 8 ADS7843 www.ti.com SBAS090B next 12th clock cycles accomplish the actual A/D conversion. If the conversion is ratiometric (SER/DFR LOW), the internal switches are on during the conversion. A 13th clock cycle is needed for the last bit of the conversion result. Three more clock cycles are needed to complete the last byte (DOUT will be LOW). These will be ignored by the converter. 16-Clocks per Conversion The control bits for conversion n + 1 can be overlapped with conversion ‘n’ to allow for a conversion every 16 clock cycles, as shown in Figure 6. This figure also shows possible serial communication occurring with other serial peripherals between each byte transfer between the processor and the converter. Control Byte BIT See Figure 5 for the placement and order of the control bits within the control byte. Tables III and IV give detailed information about these bits. The first bit, the ‘S’ bit, must always be HIGH and indicates the start of the control byte. The ADS7843 will ignore inputs on the DIN pin until the start bit is detected. The next three bits (A2-A0) select the active input channel or channels of the input multiplexer (see Tables I and II and Figure 2). The MODE bit determines the number of bits for each conversion, either 12 bits (LOW) or 8 bits (HIGH). The SER/DFR bit controls the reference mode: either singleended (HIGH) or differential (LOW). (The differential mode is also referred to as the ratiometric conversion mode.) In singleended mode, the converter’s reference voltage is always the difference between the VREF and GND pins. In differential mode, the reference voltage is the difference between the currently enabled switches. See Tables I and II and Figures 2 through 4 for more information. The last two bits (PD1-PD0) select the power-down mode as shown in Table V. If both inputs are HIGH, the device is always powered up. If both inputs are LOW, the device enters a power-down mode between conversions. When a new conversion is initiated, the device will resume normal operation instantly—no delay is needed to allow the device to power up and the very first conversion will be valid. There are two power-down modes: one where PENIRQ is disabled and one where it is enabled. Bit 7 (MSB) Bit 6 Bit 5 Bit 4 S A2 A1 A0 Bit 3 Bit 2 MODE SER/DFR Bit 1 Bit 0 (LSB) PD1 PD0 NAME 7 DESCRIPTION S Start Bit. Control byte starts with first HIGH bit on DIN. A new control byte can start every 16th clock cycle in 12-bit conversion mode or every 12th clock cycle in 8-bit conversion mode. 6-4 A2-A0 Channel Select Bits. Along with the SER/DFR bit, these bits control the setting of the multiplexer input, switches, and reference inputs, see Tables I and II. 3 MODE 12-Bit/8-Bit Conversion Select Bit. This bit controls the number of bits for the following conversion: 12 bits (LOW) or 8 bits (HIGH). 2 SER/DFR Single-Ended/Differential Reference Select Bit. Along with bits A2-A0, this bit controls the setting of the multiplexer input, switches, and reference inputs, see Tables I and II. 1-0 PD1-PD0 Power-Down Mode Select Bits. See Table V for details. TABLE IV. Descriptions of the Control Bits within the Control Byte. PD1 TABLE III. Order of the Control Bits in the Control Byte. PD0 PENIRQ DESCRIPTION 0 0 Enabled Power-down between conversions. When each conversion is finished, the converter enters a low power mode. At the start of the next conversion, the device instantly powers up to full power. There is no need for additional delays to assure full operation and the very first conversion is valid. The Y– switch is on while in power-down. 0 1 Disabled Same as mode 00, except PENIRQ is disabled. The Y– switch is off while in power-down mode. 1 0 Disabled Reserved for future use. 1 1 Disabled No power-down between conversions, device is always powered. TABLE V. Power-Down Selection. CS DCLK 1 DIN 8 1 8 S 1 8 1 S CONTROL BITS CONTROL BITS BUSY DOUT 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 FIGURE 6. Conversion Timing, 16 Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required with Dedicated Serial Port. ADS7843 SBAS090B 9 www.ti.com This is possible provided that each conversion completes within 1.6ms of starting. Otherwise, the signal that has been captured on the input sample-and-hold may droop enough to affect the conversion result. Note that the ADS7843 is fully powered while other serial communications are taking place during a conversion. FS = Full-Scale Voltage = VREF(1) 1LSB = VREF(1)/4096 1LSB 11...111 Digital Timing Figure 7 and Table VI provide detailed timing for the digital interface of the ADS7843. Output Code 11...110 11...101 00...010 00...001 SYMBOL DESCRIPTION MIN TYP MAX UNITS tACQ Acquisition Time 1.5 tDS DIN Valid Prior to DCLK Rising 100 ns tDH DIN Hold After DCLK HIGH 10 ns tDO DCLK Falling to DOUT Valid 00...000 µs 200 0V NOTES: (1) Reference voltage at converter: +REF – (–REF). See Figure 2. (2) Input voltage at converter, after multiplexer: +IN – (–IN). See Figure 2 ns tDV CS Falling to DOUT Enabled 200 ns tTR CS Rising to DOUT Disabled 200 ns tCSS CS Falling to First DCLK Rising 100 ns tCSH CS Rising to DCLK Ignored 0 ns tCH DCLK HIGH 200 ns tCL DCLK LOW 200 ns tBD DCLK Falling to BUSY Rising 200 FIGURE 8. Ideal Input Voltages and Output Codes. 8-Bit Conversion ns tBDV CS Falling to BUSY Enabled 200 ns tBTR CS Rising to BUSY Disabled 200 ns FS – 1LSB Input Voltage(2) (V) TABLE VI. Timing Specifications (+VCC = +2.7V and Above, TA = –40°C to +85°C, CLOAD = 50pF). Data Format The ADS7843 output data is in Straight Binary format, as shown in Figure 8. This figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise. The ADS7843 provides an 8-bit conversion mode that can be used when faster throughput is needed and the digital result is not as critical. By switching to the 8-bit mode, a conversion is complete four clock cycles earlier. This could be used in conjunction with serial interfaces that provide 12-bit transfers or two conversions could be accomplished with three 8-bit transfers. Not only does this shorten each conversion by four bits (25% faster throughput), but each conversion can actually occur at a faster clock rate. This is because the internal settling time of the ADS7843 is not as critical—settling to better than 8 bits is all that is needed. The clock rate can be as much as 50% faster. The faster clock rate and fewer clock cycles combine to provide a 2x increase in conversion rate. CS tCSS tCL tCH tBD tBD tD0 tCSH DCLK tDS DIN tDH PD0 tBDV tBTR BUSY tDV tTR DOUT 11 10 FIGURE 7. Detailed Timing Diagram. 10 ADS7843 www.ti.com SBAS090B POWER DISSIPATION There are two major power modes for the ADS7843: full power (PD1-PD0 = 11B) and auto power-down (PD1-PD0 = 00B). When operating at full speed and 16 clocks per conversion ( see Figure 6), the ADS7843 spends most of its time acquiring or converting. There is little time for auto power-down, assuming that this mode is active. Therefore, the difference between full power mode and auto power-down is negligible. If the conversion rate is decreased by simply slowing the frequency of the DCLK input, the two modes remain approximately equal. However, if the DCLK frequency is kept at the maximum rate during a conversion but conversions are simply done less often, the difference between the two modes is dramatic. Figure 9 shows the difference between reducing the DCLK frequency (“scaling” DCLK to match the conversion rate) or maintaining DCLK at the highest frequency and reducing the number of conversions per second. In the later case, the converter spends an increasing percentage of its time in power-down mode (assuming the auto power-down mode is active). Another important consideration for power dissipation is the reference mode of the converter. In the single-ended reference mode, the converter’s internal switches are on only when the analog input voltage is being acquired (see Figure 5). Thus, the external device, such as a resistive touch screen, is only powered during the acquisition period. In the differential reference mode, the external device must be powered throughout the acquisition and conversion periods (see Figure 5). If the conversion rate is high, this could substantially increase power dissipation. Supply Current (µA) fCLK = 16 • fSAMPLE 100 fCLK = 2MHz TA = 25°C +VCC = +2.7V 1 1k 10k For optimum performance, care should be taken with the physical layout of the ADS7843 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, during any single conversion for an ‘n-bit’ SAR converter, there are n ‘windows’ in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high-power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the DCLK input. With this in mind, power to the ADS7843 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. A 1µF to 10µF capacitor may also be needed if the impedance of the connection between +VCC and the power supply is high. The reference should be similarly bypassed with a 0.1µF capacitor. If the reference voltage originates from an op amp, make sure that it can drive the bypass capacitor without oscillation. The ADS7843 draws very little current from the reference on average, but it does place larger demands on the reference circuitry over short periods of time (on each rising edge of DCLK during a conversion). The ADS7843 architecture offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high frequency noise can be filtered out, voltage variation due to line frequency (50Hz or 60Hz) can be difficult to remove. 1000 10 devices have fairly “clean” power and grounds because most of the internal components are very low power. This situation would mean less bypassing for the converter’s power and less concern regarding grounding. Still, each situation is unique and the following suggestions should be reviewed carefully. 100k 1M fSAMPLE (Hz) FIGURE 9. Supply Current versus Directly Scaling the Frequency of DCLK with Sample Rate or Keeping DCLK at the Maximum Possible Frequency. LAYOUT The following layout suggestions should provide the most optimum performance from the ADS7843. However, many portable applications have conflicting requirements concerning power, cost, size, and weight. In general, most portable The GND pin should be connected to a clean ground point. In many cases, this will be the “analog” ground. Avoid connections which are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply entry or battery connection point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. In the specific case of use with a resistive touch screen, care should be taken with the connection between the converter and the touch screen. Since resistive touch screens have fairly low resistance, the interconnection should be as short and robust as possible. Longer connections will be a source of error, much like the on-resistance of the internal switches. Likewise, loose connections can be a source of error when the contact resistance changes with flexing or vibrations. ADS7843 SBAS090B 11 www.ti.com PACKAGE DRAWING MSOI004D – JANUARY 1995 – REVISED OCTOBER 2000 DBQ (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0.012 (0,30) 0.008 (0,20) 0.025 (0,64) 24 0.005 (0,13) M 13 0.244 (6,20) 0.228 (5,80) 0.008 (0,20) NOM 0.157 (3,99) 0.150 (3,81) 1 Gage Plane 12 A 0.010 (0,25) 0°– 8° 0.069 (1,75) MAX 0.035 (0,89) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) PINS ** 16 20 24 28 A MAX 0.197 (5,00) 0.344 (8,74) 0.344 (8,74) 0.394 (10,01) A MIN 0.188 (4,78) 0.337 (8,56) 0.337 (8,56) 0.386 (9,80) DIM 4073301/E 10/00 NOTES: A. B. C. D. 12 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). 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