PCI 9050 Errata Rev. 1.3 August 2001 Errata Documentation A. Affected Silicon Revision This document details errata in the following silicon: Product PCI 9050 B. Part Number PCI 9050-1 Description 160-pin PQFP Package Status Production Released Silicon Documentation Revision The following documentation is the baseline functional description of the silicon. Errata are defined as behaviors in the affected silicon that do not match behaviors detailed in this documentation. Document PCI 9050 Data Book C. Revision 2.0 Description PCI 9050-1 Data Book Publication Date June 2001 Errata Summary # 1 2 3 4 5 Description Reads from Local Configuration Registers Expansion ROM Space Enable Delayed read during 32K PCI clocks timeout Retracted Erratum: LOCK# de-assertion during an idle phase Read Ahead Mode (PCI Read No Flush Mode) with Burst Enabled -1- 9050-SIL-ER-P0-1.3 Confidential D. Errata Details 1. Reads from Local Configuration Registers Problem: If bit 7 of the base address for the I/O or Memory mapped Configuration Registers (PCI configuration register offset 14h or 10h) is set to 1, the local configuration registers can not be read. Under this condition, they will all return zeroes when the PCI master (typically the host) attempts to read them. The Local Configuration registers can be written to from both the PCI master and the EEPROM. In other words, the information is correctly written into the Local Configuration registers, but it can not be read the PCI Master. If bit 7 is set to 0, the Local Configuration registers can be read correctly. In a PCI system, the BIOS determines the base address (i.e. sets the value of bit 7) during the initial configuration cycle. Solutions/Workarounds: (any) 1. During adapter hardware and driver development, it may be desirable to read the configuration registers to confirm that the Local Configuration registers were programmed properly. If the BIOS has bit 7 set to 0, a PCI master can read these registers. If the BIOS has set bit 7 to 1, change the PCI base address of the memory or I/O mapped local configuration registers so that bit 7 is 0. This value is easily changed by writing to offsets 10h and 14h, which hold the base addresses. For example, say the host assigns a value of 0000FC81h for the I/O mapped local configuration register (PCR 14h). Use PLXMON or your own driver to change this base address to 0000FC01h (type PCR 14 0000FC01 at the PLXMON command prompt). This solution risks that BIOS did not assign the address range to another device. 2. Assign 256 bytes of I/O spaces to one of the un-used Local Spaces in the Serial EEPROM. Swap the PCI Base for the un-used Local Address Spaces to PCI Base Address 1 for I/O Mapped Configuration Registers after the system booted. 3. Use the PCI 9052, which is pin and register compatible with the PCI 9050. Impact: In the production phase, for some types of adapters it is never necessary to read the Local Configuration registers. In these cases, this erratum has no impact. However, in some situations, it is desirable to read the Local Configuration registers. Situations, which are impacted, are; 1. Interrupt Status. If there is only one local interrupt source, the erratum has no impact. However, if there are two local interrupt sources, the PCI master can not read the Local Configuration registers to determine where the interrupt come from. In this case, the interrupt status should be stored -2- 9050-SIL-ER-P0-1.3 Confidential in local memory or an on-board register. The PCI master should read the status from the local memory or register. 2. User Inputs (1,2,3, and 4), used for transferring bit or status data from the local side. If messages need to be passed to the host, a section of local memory can be defined and a direct slave read access could be made to retrieve the data. 3. Serial EEPROM read and valid bits, for host-initiated reads of an external serial EEPROM. This mode is generally used only in development. 2. Expansion ROM Space Enable Problem: If the PCI BIOS does not set the Expansion ROM Space enable bit in the PCI 9050 during initialization, the PCI 9050 will return all 0’s for the range, indicating that there is no Expansion ROM. This problem applies only to boards that need to use Expansion ROM Space. Solutions/Workarounds: (either) 1. Most standard PCI BIOS do not set the enable bit during initialization. Therefore, to use an Expansion ROM, in most cases requires modification to the BIOS. 2. Use the PCI 9052 (which is pin and register compatible with the PCI 9050). The PCI 9052 provides the EROMRR[0] bit (programmable by EEPROM) to enable Expansion ROM. 3. Delayed read during 32K PCI clocks timeout Problem: As per the PCI specification, a master must complete a delayed read. When a delayed read is not completed within 32K PCI clocks, the target with the pending delayed read should discard it (protect against violations or PCI 2.0 devices). The PCI 9050 will discard a delayed read if it is not completed within 32K PCI clocks, only if the PCI Spec r2.1 Features register bit is set (CNTRL[14] = 1). There is a one-clock window (last clock of 32K timeout) in which the PCI 9052 discards the delayed read. During this 1clock window, new PCI cycles are not monitored. If a new PCI cycle is begun during that 1- clock window, the PCI 9050 ignores the PCI cycle. Therefore, a master abort will occur on the PCI bus. Solution/Workaround: This is an extremely rare occurrence. If you encounter it, software should recover both the timeout and master abort with a retry. 4. LOCK# de-assertion during an idle phase This erratum was previously published. However, it has since been determined to not be an issue in the PCI 9050, and therefore this erratum is retracted. -3- 9050-SIL-ER-P0-1.3 Confidential 5. Read Ahead Mode (PCI Read No Flush Mode) with Burst Enabled Problem: During Read Ahead Mode (PCI Read No Flush Mode) (CNTRL[16] = 1) transactions when Bursting is enabled, the PCI 9050 will prefetch corrupted data after the first successful prefetch attempt. This will only occur when both the PCI Read No Flush Mode is set (CNTRL[16] = 1) and Bursting is enabled. Bursting is enabled in any of the four Local Address Spaces or the Expansion ROM Space by setting bit 0 of the corresponding register (LAS0BRD[0] = 1 for Local Address Space 0; LAS1BRD[0] = 1 for Local Address Space 1; LAS2BRD[0] = 1 for Local Address Space 2; LAS3BRD[0] = 1 for Local Address Space 3; and EROMBRD[0] = 1 for Expansion ROM Space). Solutions/Workarounds: (any) 1. Disable bursting on the Local Bus Address Spaces and Expansion ROM Space. Read Ahead Mode (PCI Read No Flush Mode) transactions will then operate correctly. 2. Do not use Read Ahead Mode (PCI Read No Flush Mode) (CNTRL[16] = 0). 3. Use the PCI 9052, which is pin and register compatible with the PCI 9050. Read Ahead mode and Burst mode can both be enabled in the PCI 9052. Copyright 2001 by PLX Technology, Inc. All rights reserved. PLX is a trademark of PLX Technology, Inc. which may be registered in some jurisdictions. All other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX Technology reserves the right, without notice, to make changes in product design or specification. -4- 9050-SIL-ER-P0-1.3 Confidential