HUF76132P3, HUF76132S3S
Data Sheet
January 2003
75A, 30V, 0.011 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs
Features
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET™ process. This
advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable
and battery-operated products.
• 75A, 30V
• Logic Level Gate Drive
• Ultra Low On-Resistance, rDS(ON) = 0.011Ω
• Temperature Compensating PSPICE® Model
• Temperature Compensating SABER© Model
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Formerly developmental type TA76132.
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
Symbol
PART NUMBER
PACKAGE
D
BRAND
HUF76132P3
TO-220AB
76132P
HUF76132S3S
TO-263AB
76132S
G
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF76132S3ST.
S
Packaging
JEDEC TO-220AB
JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
©2003 Fairchild Semiconductor Corporation
GATE
DRAIN
(FLANGE)
SOURCE
HUF76132P3, HUF76132S3S Rev. C1
HUF76132P3, HUF76132S3S
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
30
V
Drain to Gate Voltage (R GS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR
30
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±20
V
Drain Current
Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
75
44
41
Figure 4
A
A
A
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Figures 6, 17, 18
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
0.97
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-40 to 150
oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TA = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
30
-
-
V
VDS = 25V, VGS = 0V
-
-
1
µA
VDS = 25V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±20V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
BVDSS
IDSS
IGSS
ID = 250µA, VGS = 0V (Figure 12)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS , ID = 250µA (Figure 11)
1
-
3
V
Drain to Source On Resistance
rDS(ON)
ID = 75A, VGS = 10V (Figure 9, 10)
-
0.0085
0.011
Ω
ID = 44A, VGS = 5V (Figure 9)
-
0.013
0.016
Ω
ID = 41A, VGS = 4.5V (Figure 9)
-
0.015
0.018
Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
R θJC
(Figure 3)
-
-
1.03
oC/W
Thermal Resistance Junction to Ambient
RθJA
TO-220, TO-262 and TO-263
-
-
62
oC/W
VDD = 15V, ID ≅ 41A,
RL = 0.366Ω, VGS = 4.5V,
RGS = 6.2Ω
(Figures 15, 21, 22)
-
-
185
ns
-
17
-
ns
-
105
-
ns
td(OFF)
-
33
-
ns
tf
-
42
-
ns
tOFF
-
-
113
ns
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
©2003 Fairchild Semiconductor Corporation
tON
td(ON)
tr
HUF76132P3, HUF76132S3S Rev. C1
HUF76132P3, HUF76132S3S
Electrical Specifications
TA = 25oC, Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
-
72
ns
-
11
-
ns
-
37
-
ns
td(OFF)
-
65
-
ns
tf
-
42
-
ns
tOFF
-
-
160
ns
-
44
52
nC
-
25
30
nC
-
1.8
2.2
nC
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 15V, ID ≅ 75A,
RL = 0.20, VGS = 10V,
RGS = 6.8Ω
(Figures 16, 21, 22)
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
VDD = 15V, ID ≅ 44A,
RL = 0.341Ω
Ig(REF) = 1.0mA
VGS = 0V to 1V
(Figures 14, 19, 20)
Threshold Gate Charge
Qg(TH)
Gate to Source Gate Charge
Qgs
-
4.80
-
nC
Gate to Drain “Miller” Charge
Qgd
-
13.50
-
nC
-
1650
-
pF
-
850
-
pF
-
200
-
pF
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
MIN
TYP
MAX
UNITS
ISD = 44A
-
-
1.25
V
trr
ISD = 44A, dISD/dt = 100A/µs
-
-
71
ns
QRR
ISD = 44A, dISD/dt = 100A/µs
-
-
104
nC
VSD
Reverse Recovery Time
Reverse Recovered Charge
Typical Performance Curves
TEST CONDITIONS
Unless Otherwise Specified
80
1.0
VGS = 10V
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
TA , AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
©2003 Fairchild Semiconductor Corporation
150
60
40
VGS = 4.5V
20
0
25
50
75
100
125
150
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
HUF76132P3, HUF76132S3S Rev. C1
HUF76132P3, HUF76132S3S
Typical Performance Curves
Unless Otherwise Specified (Continued)
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10 -1
100
10 1
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
2000
TC = 25oC
FOR TEMPERATURES
ABOVE 25 oC DERATE PEAK
IDM, PEAK CURRENT (A)
1000
CURRENT AS FOLLOWS:
VGS = 10V
I
=
150 - TC
I25
125
VGS = 5V
100
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
50
10-5
10-4
10 -3
10-2
t, PULSE WIDTH (s)
10-1
100
101
FIGURE 4. PEAK CURRENT CAPABILITY
ID, DRAIN CURRENT (A)
TJ = MAX RATED
TC = 25oC
100
100µs
IAS, AVALANCHE CURRENT (A)
500
1000
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD ) +1]
100
1ms
10
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
1
STARTING TJ = 25oC
STARTING TJ = 150oC
BVDSS MAX = 30V
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
100
10
0.01
0.1
1
tAV, TIME IN AVALANCHE (ms)
10
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
©2003 Fairchild Semiconductor Corporation
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
HUF76132P3, HUF76132S3S Rev. C1
HUF76132P3, HUF76132S3S
Typical Performance Curves
120
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID, DRAIN CURRENT (A)
100
VGS = 5V
VGS = 10V
-40oC
150oC
VGS = 4.5V
100
I D, DRAIN CURRENT (A)
120
Unless Otherwise Specified (Continued)
80
25oC
60
40
80
VGS = 3.5V
60
40
VGS = 3V
20
20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25 oC
VDD = 15V
0
0
0
1
2
3
4
VGS, GATE TO SOURCE VOLTAGE (V)
5
0
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
ON RESISTANCE (mΩ)
rDS(ON), DRAIN TO SOURCE
16
ID = 51A
14
ID = 25A
12
10
8
6
2
4
6
8
4
1.2
1.0
0.8
0.6
-60
10
0
60
120
180
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
1.0
0.8
0
60
120
180
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2003 Fairchild Semiconductor Corporation
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
VGS = VDS, ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
3
1.6 PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, I D = 75A
1.4
VGS, GATE TO SOURCE VOLTAGE (V)
0.6
-60
2
FIGURE 8. SATURATION CHARACTERISTICS
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID = 75A
1
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
18
VGS = 4V
ID = 250µA
1.1
1.0
0.9
-60
0
60
120
TJ , JUNCTION TEMPERATURE (oC)
180
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
HUF76132P3, HUF76132S3S Rev. C1
HUF76132P3, HUF76132S3S
Typical Performance Curves
Unless Otherwise Specified (Continued)
10
2500
CISS
VGS , GATE TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
2000
VGS = 0V, f = 1MHz
CISS = C GS + CGD
CRSS = CGD
COSS ≈ CDS + C GD
1500
COSS
1000
500
CRSS
0
0
5
15
10
25
20
VDD = 15V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 75A
ID = 51A
ID = 25A
2
0
0
30
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
40
30
20
Qg, GATE CHARGE (nC)
50
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
400
400
300
VGS = 10V, VDD = 15V, ID = 75A, RL= 0.20Ω
SWITCHING TIME (ns)
SWITCHING TIME (ns)
VGS = 4.5V, VDD = 15V, ID = 41A, RL= 0.312Ω
tr
200
tf
100
td(OFF)
300
td(OFF)
200
tf
tr
100
td(ON)
td(ON)
0
0
10
20
30
40
0
50
0
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
20
30
40
10
RGS, GATE TO SOURCE RESISTANCE (Ω)
50
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
VDS
BVDSS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tP
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
©2003 Fairchild Semiconductor Corporation
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
HUF76132P3, HUF76132S3S Rev. C1
HUF76132P3, HUF76132S3S
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10
VGS
Qg(5)
+
-
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
-
VDD
10%
0
10%
DUT
RGS
VGS
90%
VGS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
©2003 Fairchild Semiconductor Corporation
10%
50%
50%
PULSE WIDTH
FIGURE 22. SWITCHING TIME WAVEFORM
HUF76132P3, HUF76132S3S Rev. C1
HUF76132P3, HUF76132S3S
PSPICE Electrical Model
SUBCKT HUF76132 2 1 3 ;
REV May 1998
CA 12 8 2.35e-9
CB 15 14 2.35e-9
CIN 6 8 1.45e-9
LDRAIN
DPLCAP
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
10
RLDRAIN
RSLC1
51
RSLC2
5
51
ESLC
EVTHRES
+ 19 8
+
IT 8 17 1
LGATE
GATE
1
11
+
50
RDRAIN
6
8
ESG
DBREAK
+
EBREAK 11 7 17 18 33.34
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
LDRAIN 2 5 1e-9
LGATE 1 9 5.42e-9
LSOURCE 3 7 4.16e-9
DRAIN
2
5
EVTEMP
RGATE +
18 22
9
20
21
EBREAK
17
18
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
8
SOURCE
3
7
RSOURCE
RLSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.5e-4
RGATE 9 20 2.61
RLDRAIN 2 5 10
RLGATE 1 9 54.2
RLSOURCE 3 7 41.6
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 6.5-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
S1A
12
S2A
14
13
13
8
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
VBAT
5
8
EDS
-
-
IT
14
+
+
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*450),3))}
.MODEL DBODYMOD D (IS = 1.79e-12 IKF = 20 RS = 5.32e-3 TRS1 = 7e-4 TRS2 = 1.21e-6 CJO = 2.65e-9 TT = 3.24e-8 M = 4.2e-1 XTI=6)
.MODEL DBREAKMOD D (RS = 8.25e-2 TRS1 = 9.12e-4 TRS2 = 8.14e-7)
.MODEL DPLCAPMOD D (CJO = 1.3e-9 IS = 1e-30 N = 10 M = 6.1e-1)
.MODEL MMEDMOD NMOS (VTO = 1.86 KP = 4 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.61)
.MODEL MSTROMOD NMOS (VTO = 2.2 KP = 120 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.63 KP =1e-1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 26.1 RS=1e-1)
.MODEL RBREAKMOD RES (TC1 = 9.97e-4 TC2 = 1.24e-7)
.MODEL RDRAINMOD RES (TC1 = 7.2e-2 TC2 = 1e-4)
.MODEL RSLCMOD RES (TC1 = 1.07e-3 TC2 = 1.25e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-11 TC2 = 1e-11)
.MODEL RVTHRESMOD RES (TC1 = -2e-3 TC2 = -9.2e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.08e-3 TC2 = 9.73e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -6.00 VOFF= -1.00)
VON = -1.00 VOFF= -6.00)
VON = 0.00 VOFF= 1.65)
VON = 1.65 VOFF= 0.00)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2003 Fairchild Semiconductor Corporation
HUF76132P3, HUF76132S3S Rev. C1
HUF76132P3, HUF76132S3S
SABER Electrical Model
nom temp=25 deg c
30v LL Ultrafet
REV May 1998
template huf76132 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is=1.79e-12,cjo=2.65e-9,tt=3.24e-8, m=4.2e-1, xti=6)
d..model dbreakmod = ()
d..model dplcapmod = (cjo=1.3e-9,is=1e-30,n=10,m=6.1e-1)
m..model mmedmod = (type=_n,vto=1.86,kp=4,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.2,kp=120,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.63,kp=1e-1,is=1e-30, tox=1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-6.00,voff=-1.00)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-1.00,voff=-6.00)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=0,voff=1.65)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=1.65,voff=0)
LDRAIN
DPLCAP
DRAIN
2
5
10
RSLC1
51
RLDRAIN
RDBREAK
RSLC2
c.ca n12 n8 = 2.35e-9
c.cb n15 n14 = 2.35e-9
c.cin n6 n8 = 1.45e-9
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
l.ldrain n2 n5 = 5.42e-9
l.lgate n1 n9 = 1.00e-9
l.lsource n3 n7 = 4.16e-9
EVTEMP
RGATE + 18 22
9
20
MWEAK
DBODY
EBREAK
+
17
18
MMED
MSTRO
CIN
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
71
11
16
6
RLGATE
-
8
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
S1A
12
res.rbreak n17 n18 = 1, tc1=9.97e-4,tc2=1.24e-7
res.rdbody n71 n5 =5.32e-3, tc1=7.0e-4, tc2=1.21e-6
res.rdbreak n72 n5 =8.25e-2, tc1=9.12e-4, tc2=8.14e-7
res.rdrain n50 n16 = 3.5e-4, tc1=7.2e-2,tc2=1e-4
res.rgate n9 n20 = 2.61
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 54.2
res.rlsource n3 n7 = 41.6
res.rslc1 n5 n51 = 1e-6, tc1=1.07e-3,tc2=-1.25e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 6.5e-3, tc1=1e-11,tc2=1e-11
res.rvtemp n18 n19 = 1, tc1=-1.08e-3,tc2=9.73e-7
res.rvthres n22 n8 = 1, tc1=-2e-3,tc2=-9.2e-6
21
RDBODY
DBREAK
50
-
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
72
ISCL
S2A
13
8
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 33.34
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/450))** 3))
}
}
©2003 Fairchild Semiconductor Corporation
HUF76132P3, HUF76132S3S Rev. C1
HUF76132P3, HUF76132S3S
SPICE Thermal Model
th
JUNCTION
REV May 1998
HUF76132
CTHERM1 th 6 5.00e-3
CTHERM2 6 5 1.18e-2
CTHERM3 5 4 15.5e-2
CTHERM4 4 3 1.85e-2
CTHERM5 3 2 2.00e-2
CTHERM6 2 tl 2.5e-2
RTHERM1
RTHERM1 th 6 1.51e-2
RTHERM2 6 5 1.51e-2
RTHERM3 5 4 3.03e-2
RTHERM4 4 3 6.05e-2
RTHERM5 3 2 1.81e-1
RTHERM6 2 tl 2.45e-1
RTHERM2
CTHERM1
6
CTHERM2
5
RTHERM3
CTHERM3
SABER Thermal Model
SABER thermal model HUF76132
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 6.50e-3
ctherm.ctherm2 6 5 = 1.18e-2
ctherm.ctherm3 5 4 = 1.55e-2
ctherm.ctherm4 4 3 = 1.85e-2
ctherm.ctherm5 3 2 = 2.00e-2
ctherm.ctherm6 2 tl = 2.50e-2
rtherm.rtherm1 th 6 = 1.51e-2
rtherm.rtherm2 6 5 = 1.51e-2
rtherm.rtherm3 5 4 = 3.03e-2
rtherm.rtherm4 4 3 = 6.05e-2
rtherm.rtherm5 3 2 = 1.81e-1
rtherm.rtherm6 2 tl = 2.45e-1
}
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
©2003 Fairchild Semiconductor Corporation
CASE
HUF76132P3, HUF76132S3S Rev. C1
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Rev. I2