SN74ALVCHR16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056G – SEPTEMBER 1995 – REVISED JUNE 1999 D D D D D D D D DGG OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus+ Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process B-Port Outputs Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required UBE (Universal Bus Exchanger) Allows Synchronous Data Exchange ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages PRE SEL0 1A1 GND 1A2 1A3 VCC 1A4 1A5 1A6 GND 1A7 1A8 1A9 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2A9 SEL1 SEL2 NOTE: For tape and reel order entry: The DGGR package is abbreviated to GR, and the DLR package is abbreviated to LR. description This 9-bit, 4-port universal bus exchanger is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCHR16409 allows synchronous data exchange between four different buses. Data flow is controlled by the select (SEL0–SEL4) inputs. A data-flow state is stored on the rising edge of the clock (CLK) input if the select-enable (SELEN) input is low. Once a data-flow state has been established, data is stored in the flip-flop on the rising edge of CLK if SELEN is high. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 CLK SELEN 1B1 GND 1B2 1B3 VCC 1B4 1B5 1B6 GND 1B7 1B8 1B9 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2B9 SEL4 SEL3 The data-flow control logic is designed to allow glitch-free data transmission. The B outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω series resistors to reduce overshoot and undershoot. When preset (PRE) transitions high, the outputs are disabled immediately, without waiting for a clock pulse. To leave the high-impedance state, both PRE and SELEN must be low and a clock pulse must be applied. To ensure the high-impedance state during power up or power down, PRE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC, UBE, and Widebus+ are trademarks of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALVCHR16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056G – SEPTEMBER 1995 – REVISED JUNE 1999 description (continued) Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCHR16409 is characterized for operation from –40°C to 85°C. Function Tables INPUTS CLK SEND PORT X X OUTPUT RECEIVE PORT X L B0† L X H H ↑ L L ↑ H H X H B0† B0† L X † Output level before the indicated steady-state input conditions were established 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCHR16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056G – SEPTEMBER 1995 – REVISED JUNE 1999 DATA-FLOW CONTROL INPUTS PRE SEL0 DATA FLOW SELEN CLK SEL1 SEL2 SEL3 SEL4 H X X L H ↑ X X X X X X X X X X L L ↑ 0 No change 0 0 0 0 None, all I/Os off L L ↑ 0 0 0 0 1 Not used L L ↑ 0 0 0 1 0 Not used L L ↑ 0 0 0 1 1 Not used L L ↑ 0 0 1 0 0 Not used L L ↑ 0 0 1 0 1 Not used L L ↑ 0 0 1 1 0 Not used L L ↑ 0 0 1 1 1 Not used L L ↑ 0 1 0 0 0 2A to 1A and 1B to 2B L L ↑ 0 1 0 0 1 2A to 1A L L ↑ 0 1 0 1 0 2B to 1B L L ↑ 0 1 0 1 1 2A to 1A and 2B to 1B L L ↑ 0 1 1 0 0 1A to 2A and 1B to 2B L L ↑ 0 1 1 0 1 1A to 2A L L ↑ 0 1 1 1 0 1B to 2B L L ↑ 0 1 1 1 1 1A to 2A and 2B to 1B L L ↑ 1 0 0 0 0 1A to 1B and 2B to 2A L L ↑ 1 0 0 0 1 1A to 1B L L ↑ 1 0 0 1 0 2A to 2B L L ↑ 1 0 0 1 1 1A to 1B and 2A to 2B L L ↑ 1 0 1 0 0 1B to 1A and 2A to 2B L L ↑ 1 0 1 0 1 1B to 1A L L ↑ 1 0 1 1 0 2B to 2A L L ↑ 1 0 1 1 1 1B to 1A and 2B to 2A L L ↑ 1 1 0 0 0 2B to 1A and 2A to 1B L L ↑ 1 1 0 0 1 1B to 2A L L ↑ 1 1 0 1 0 2B to 1A L L ↑ 1 1 0 1 1 2B to 1A and 1B to 2A L L ↑ 1 1 1 0 0 1A to 2B and 1B to 2A L L ↑ 1 1 1 0 1 1A to 2B L L ↑ 1 1 1 1 0 2A to 1B L L ↑ 1 1 1 1 1 1A to 2B and 2A to 1B POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 All outputs disabled 3 SN74ALVCHR16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056G – SEPTEMBER 1995 – REVISED JUNE 1999 logic diagram (positive logic) CLK SELEN 56 1 PRE 55 28 SEL2 2 29 SEL0 SEL1 SEL3 Flow and Storage Control 27 30 SEL4 3 3 2Ax 1Ax CLK D 1A 1Ax CLK D 2A CLK D 1Bx 2Ax 2Bx 2Bx 3 1B 3 1Ax 1Ax 1Bx 2Bx 2Ax 1Bx 2Ax 1Bx CLK D 2B 2Bx One of Nine Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCHR16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056G – SEPTEMBER 1995 – REVISED JUNE 1999 recommended operating conditions (see Note 4) VCC Supply voltage VIH High-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V MIN MAX 1.65 3.6 2 0.35 × VCC Low-level input voltage VI VO Input voltage 0 Output voltage 0 0.7 VCC = 2.7 V to 3.6 V IOL ∆t/∆v Low level output current Low-level V 1.7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High level output current High-level V 0.8 VCC VCC VCC = 1.65 V VCC = 2.3 V –2 VCC = 2.7 V VCC = 3 V –8 –6 V V mA –12 VCC = 1.65 V VCC = 2.3 V 2 VCC = 2.7 V VCC = 3 V 8 Input transition rise or fall rate V 0.65 × VCC VIL IOH UNIT 6 mA 12 10 ns/V TA Operating free-air temperature –40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALVCHR16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056G – SEPTEMBER 1995 – REVISED JUNE 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA IOH = –4 mA VOH 6 mA IOH = –6 2.3 V 1.9 2.3 V 1.7 MAX 2.4 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 2.3 V 0.4 2.3 V 0.55 3V 0.55 IOL = 8 mA IOL = 12 mA 2.7 V 0.6 3V 0.8 VI = VCC or GND VI = 0.58 V 3.6 V 1 65 V 1.65 23V 2.3 VI = 1.7 V VI = 0.8 V 3V VI = 2 V VI = 0 to 3.6 V‡ IOZ§ ICC VO = VCC or GND VI = VCC or GND, ∆ICC Ci One input at VCC – 0.6 V, Control inputs Cio A or B ports IO = 0 Other inputs at VCC or GND VI = VCC or GND VO = VCC or GND UNIT V 3V VI = 1.07 V VI = 0.7 V II(hold) ( ) 1.65 V VCC–0.2 1.2 2.7 V IOL = 6 mA II TYP† IOH = –8 mA IOH = –12 mA IOL = 4 mA VOL MIN ±5 V µA 25 –25 45 µA –45 75 –75 3.6 V ±500 3.6 V ±10 µA 3.6 V 40 µA 3 V to 3.6 V 750 µA 3.3 V 4 3.3 V 8 pF pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. § For I/O ports, the parameter IOZ includes the input leakage current. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCHR16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056G – SEPTEMBER 1995 – REVISED JUNE 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw tsu th Clock frequency Hold time MIN MAX VCC = 2.7 V MIN 120 MAX VCC = 3.3 V ± 0.3 V MIN 120 4.2 4.2 3 A or B before CLK↑ † 1.9 1.9 1.4 SEL before CLK↑ † 5.1 4.2 3.5 SELEN before CLK↑ † 2.5 2.5 1.8 PRE before CLK↑ † 1 1 0.7 A or B after CLK↑ † 0.8 0.8 1 SEL after CLK↑ † 0 0 0 SELEN after CLK↑ † 0.5 0.5 0.8 UNIT MAX 120 † Pulse duration, CLK high or low Set p time Setup MAX † VCC = 2.5 V ± 0.2 V MHz ns ns ns † This information was not available at the time of publication. timing diagram CLK tsu th tsu th SELEN SEL (0-4) ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tsu Selected Input Port Selected Output Port th tpd CLK to Output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74ALVCHR16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056G – SEPTEMBER 1995 – REVISED JUNE 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER fmax tpd CLK ten CLK CLK tdi dis PRE VCC = 1.8 V TO (OUTPUT) MIN † TYP VCC = 2.5 V ± 0.2 V MIN MAX 120 VCC = 2.7 V MIN MAX 120 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 120 MHz A or B † 1.5 6.9 7 1.5 6.2 ns A or B † 2.4 7.8 7.6 2 6.8 ns † 2.3 7.1 6.4 2 6.1 † 2.8 7.7 7 2.5 6.4 A or B ns † This information was not available at the time of publication. operating characteristics, TA = 25°C PARAMETER Cpd d Power dissipation capacitance TEST CONDITIONS All outputs enabled All outputs disabled CL = 50 pF, pF VCC = 1.8 V TYP † f = 10 MHz † This information was not available at the time of publication. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 † VCC = 2.5 V TYP VCC = 3.3 V TYP 60 60 60 60 UNIT pF SN74ALVCHR16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056G – SEPTEMBER 1995 – REVISED JUNE 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 2 × VCC S1 1 kΩ From Output Under Test Open GND CL = 30 pF (see Note A) 1 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74ALVCHR16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056G – SEPTEMBER 1995 – REVISED JUNE 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCHR16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056G – SEPTEMBER 1995 – REVISED JUNE 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 1.5 V 1.5 V 0V 0V tsu 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH Output Control (low-level enabling) 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPLZ 3V 1.5 V VOL + 0.3 V VOH 1.5 V VOL Output Waveform 2 S1 at GND (see Note B) VOL tPHZ tPZH tPHL 1.5 V 2.7 V 1.5 V tPZL 2.7 V Input VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input Output 1.5 V Input 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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