ETC RTL8305SB

RTL8305SB
REALTEK SINGLE CHIP
5-PORT 10/100 MBPS SWITCH CONTROLLER
RTL8305SB
1. Features.............................................................................2
2. General Description .........................................................3
3. Block Diagram..................................................................4
4. Pin Assignments ...............................................................5
5. Pin Descriptions................................................................7
5.1 Media Connection Pins ...............................................7
5.2 Configuration Pins ......................................................7
5.3 Port4 External MAC Interface Pins.............................8
5.4 Miscellaneous Pins....................................................13
5.5 Per Port LED Pins .....................................................14
5.6 Power Pins.................................................................15
5.7 Reserved Pins ............................................................16
5.8 Serial EEPROM and SMI Pins..................................16
5.9 Strapping Pins ...........................................................17
5.10 Port Status Strapping Pins .......................................19
6. Register Description.......................................................21
6.1 PHY0 to 4: PHY Register of Each Port.....................22
6.1.1 Register0: Control Register ...............................22
6.1.2 Register1: Status Register..................................23
6.1.3 Register4: Auto-Negotiation Advertisement Register...........23
6.1.4 Register5: Auto-Negotiation Link Partner Ability Register.....24
6.1.5 Register6: Auto-Negotiation Expansion Register.......24
6.2 PHY0: EEPROM Register0 ......................................25
6.2.1 Register16: EEPROM Byte0 and 1 Register .....25
6.2.2 Register17: EEPROM Byte2 and 3 Register .....25
6.2.3 Register18~20: EEPROM EthernetID Register.25
6.2.4 Register21: EEPROM Byte10 and 11 Register .26
6.2.5 Register22: EEPROM Byte12 and 13 Register .26
6.3 PHY1: EEPROM Register1 ......................................27
6.3.1 Register16~23: EEPROM (Byte 14~29) Register......27
6.3.2 Register24~31: EEPROM VLAN (Byte 30~44) Register....27
6.4 PHY2: Pin & EEPROM Register..............................28
6.4.1 Register16: Pin Register ....................................28
6.4.2 Register17: Pin & EEPROM Register for VLAN......29
6.5 PHY3: Port Control Register.....................................30
6.5.1 Register16: Port Control Register......................30
6.5.2 Register17: EEPROM (Byte 46) Register .........31
6.5.3 Register18~20: EEPROM (Byte 47~52) Register......31
7. Functional Description ..................................................32
7.1 Switch Core Functional Overview ............................32
7.1.1 Application ........................................................32
7.1.2 Port4 ..................................................................32
7.1.3 Port Status Configuration ..................................36
7.1.4 Enable Port ........................................................36
7.1.5 Flow Control......................................................37
7.1.6 Address Search, Learning and Aging ................38
7.1.7 Address Direct Mapping Mode..........................38
7.1.8 Half Duplex Operation ......................................38
7.1.9 Inter-Frame Gap ................................................38
7.1.10 Illegal Frame....................................................38
2002/04/09
1
7.2 Physical Layer Functional Overview ....................... 39
7.2.1 Auto-Negotiation for UTP ................................ 39
7.2.2 10Base-T Transmit Function ............................ 39
7.2.3 10Base-T Receive Function.............................. 39
7.2.4 Link Monitor..................................................... 39
7.2.5 100Base-TX Transmit Function........................ 39
7.2.6 100Base-TX Receive Function ......................... 39
7.2.7 100Base-FX ...................................................... 39
7.2.8 100Base-FX Transmit Function........................ 40
7.2.9 100Base-FX Receive Function ......................... 40
7.2.10 100Base-FX Far-End-Fault-Indication (FEFI) 40
7.2.11 Reduced Fiber Interface .................................. 40
7.2.12 Power Saving Mode........................................ 40
7.2.13 Reg0.11 Power Down Mode ........................... 40
7.2.14 Crossover Detection and Auto Correction ...... 41
7.2.15 Polarity Detection and Correction................... 41
7.3 Advanced Functional Overview ............................... 42
7.3.1 Reset ................................................................. 42
7.3.2 Setup and Configuration ................................... 42
7.3.3 Example of Serial EEPROM: 24LC02 ............. 43
7.3.4 24LC02 Device Operation ................................ 43
7.3.5 SMI ................................................................... 44
7.3.6 Head-Of-Line Blocking .................................... 44
7.3.7 802.1Q Port Based VLAN ................................ 44
7.3.8 QoS Function .................................................... 46
7.3.9 Insert/Remove VLAN Priority Tag................... 46
7.3.10 Filtering/Forwarding Reserved Control Frame47
7.3.11 Broadcast Storm Control................................. 47
7.3.12 Broadcast In/Out Drop.................................... 47
7.3.13 Loop Detection ............................................... 48
7.3.14 MAC Loopback return to External ................. 49
7.3.15 Reg0.14 PHY Loopback return to Internal ..... 50
7.3.16 LED ................................................................ 50
7.3.17 2.5V Power Generation................................... 52
7.3.18 Crystal/Oscillator ............................................ 52
8. Serial EEPROM Description........................................ 53
9. Electrical Characteristics ............................................. 57
9.1 Absolute Maximum Ratings:.................................... 57
9.2 Operating Range:...................................................... 57
9.3 DC Characteristics.................................................... 57
9.4 AC Characteristics.................................................... 58
9.5 Digital Timing Characteristics.................................. 59
9.6 Thermal Data............................................................ 59
10. Application Information ............................................. 60
10.1 UTP (10Base-T/100Base-TX) Application ............ 60
10.2 100Base-FX Application:....................................... 62
11. System Application Diagram...................................... 63
12. Design and Layout Guide ........................................... 64
13. Mechanical Dimensions .............................................. 65
Rev.1.0
RTL8305SB
1. Features
5-port integrated switch controller with memory and
transceiver for 10Base-T and 100Base-TX with
5-port 10/100M UTP or
4-port 10/100M UTP + 1-port MII/SNI
Supports PHY mode MII /SNI for router applications
and MAC mode MII for HomePNA or VDSL solutions
All ports support 100Base-FX with optional flow
control enable/disable and full/half duplex setting
Non-blocking wire-speed reception and transmission
and non-head-of-line-blocking forwarding
Fully compliant with IEEE 802.3/802.3u
auto-negotiation function
Built-in high efficiency SRAM for packet buffer and
1K entry look-up table, and 16 entry CAM
Supports broadcast storm filtering function
Supports IEEE802.3x full duplex flow control and
back pressure half duplex flow control
Supports SMI (Serial Management Interface:
MDC/MDIO) for programming and diagnostics
Supports loop detection function with one LED to
indicate the existence of loop
Supports loopback function for diagnosis
Flexible 802.1Q Port based VLAN. Up to 5 VLAN
Supports 802.1Q tag VLAN function
Supports ARP VLAN for broadcast packets
Supports Leaky VLAN for unicast packets
2002/04/09
2
Supports QoS function on each port:
QoS based on: (1) Port-based (2) VLAN tag
(3) TCP/IP header’s TOS/DS
Supports two level priority queues
Weighted round robin service
Supports VLAN priority tag Insert/Remove function
Optional 1536 or 1552 byte maximum packet length
Supports reserved control frames (DID=
0180C2000003~0180C200000F) filtering function
Flexible LED indicators for link, activity, speed,
full/half duplex and collision
LEDs blink upon reset for LED diagnostics
Supports two Power Reduction methods:
Power saving mode by cable detection
Power down mode (by PHY register 0.11)
Robust baseline wander correction for improved
100BASE-TX performance
Optional Crossover Detection and Auto Correction
function
Physical layer port Polarity Detection and Correction
function
Optional EEPROM interface for configuration
25MHz crystal or OSC input. Single 3.3V power
system like by translating of an external transistor
0.25 µm, CMOS technology, 3.3V/2.5V with 3.3V
input tolerant, 128 pin PQFP package
Rev.1.0
RTL8305SB
2. General Description
The RTL8305SB is a Fast Ethernet switch, which integrates memory, five MACs, and five physical layer transceivers for
10Base-T and 100Base-TX operation into a single chip. All ports support 100Base-FX, which share pins (TX+-/RX+-) with
UTP ports and need no SD+/- pins, a development using Realtek proprietary technology. Due to the lack of auto-negotiation in
100Base-FX applications, the RTL8305SB can be forced into half or full duplex mode and can enable or disable flow control
in fiber mode.
The five ports are separated into 3 groups (GroupX/GroupY/Port4) for flexible port configuration using strapping pins upon
reset. The SetGroup pin is used to select port members in GroupX and GroupY. While the port members is determined, you
can use mode selection pin (GxMode/Gymode/P4Mode[1:0]) to select operating interfaces such as 10/100Base-TX,
100Base-FX. Each group has 4 pins to select initial port status (ANEG/Force, 100/10, Full/Half, Enable/Disable Flow Control)
upon reset. Upon reset, in addition to using strapping pins, the RTL8305SB also can be configured with an EEPROM or
read/write operation by a CPU through the MDC/MDIO interface.
The fifth port (port 4) supports an external MAC interface, which can be set to PHY mode MII, PHY mode SNI, or MAC
mode MII to work with a routing engine, HomePNA or VDSL transceiver. In order to accomplish diagnostics in complex
network systems, the RTL8305SB also provides a loopback feature in each port for a variable CPU system.
The RTL8305SB contains a 1K entry address look-up table and supports a 16 entry CAM to avoid hash collisions and to
maintain forwarding performance. The RTL8305SB supports IEEE 802.3x full duplex flow control and back- pressure half
duplex flow control. The broadcast storm filtering function is provided to filter unusual broadcast storm issues and has an
intelligent switch engine to prevent Head-Of -Line blocking problems.
The RTL8305SB supports 5 groups of VLANs which can be configured with port based VLAN and/or 802.1Q tag VLAN.
ARP broadcast and Leaky VLAN are also supported for advanced applications.
The RTL8305SB supports several types of QoS functions with two level priority queues to improve multi-media or real-time
networking applications. The QoS functions are based on: 1) Port based priority; 2) 802.1Q VLAN priority tag; 3) The
TOS/DS (DiffServ) field of TCP/IP. In order to avoid the flow control function effecting the quality of high priority frames, the
RTL8305SB supports an intelligent flow control for high priority frames by setting DisFCAutoOff to automatically turn off
flow control for 1~2 seconds whenever the congestion port receives high priority frames. When the QoS function is enabled, a
VLAN tag can be inserted or removed at the output port. The RTL8305SB will insert a VLAN priority-tag (VID=0x000) for
untagged frames or remove the tag for all tagged frames.
Maximum packet length can be 1536 or 1552 bytes according to the initial configuration (strapping upon reset). The filtering
function is supported for the 802.1D specified reserved group MAC addresses (01-80-C2-00-00-03 to 01-80-C2-00-00-0F).
The RTL8305B provides flexible LED functions for diagnostics, which include: 1) Four combinations of link, activity, speed,
duplex and collision which are designed for convenient LED displays, such as bi-color LEDs; 2) Reset blinking; 3) Blinking
time selection. The RTL8305SB also provides a loop detection function and alarm, for network existence notification, with an
output pin which can be designed as a visual LED or a status input pin for a CPU.
The RTL8305SB implements a power saving mode on a per port basis. One port automatically enters power saving mode 10
seconds after the cable is disconnected from it. The RTL8305SB also implements a power down mode on a per port basis.
Users can set MII Reg.0.11 to force the corresponding port to enter the power down mode, which disables all transmit/receive
functions, except SMI (MDC/MDIO management interface).
Each physical layer channel of the RTL8305SB consists of a 4B5B encoder/decoder, a Manchester encoder/decoder, a
scrambler/descrambler, a transmit output driver, output wave shaping filters, a digital adaptive equalizer, a PLL circuit and a
DC restoration circuit for clock/data recovery. Friendly crossover auto detection and correction functions are also supported
for easy cable connection.
The integrated chip benefits from low power consumption, advanced functions with flexible configurations for 5-port SOHO
switch, Home Gateway, xDSL/Cable router, and other IA applications.
2002/04/09
3
Rev.1.0
RTL8305SB
3. Block Diagram
ENBRDCTRL
ENANEG_BKPRS
RESET#
Global
W aveform
Shaping
IBREF
functions
X1
X2
CK25MOUT
RX+-[0]
TX+-[0]
10B ased-T or
100B ased-T
PH Y ceiver
M A C0
Sw itch
Engine0
Look-up
Table
RX+-[1]
TX+-[1]
10B ased-T or
100B ased-T
PH Y ceiver
M A C1
Sw itch
Engine1
PacketB uffer
RX+-[2]
TX+-[2]
10B ased-T or
100B ased-T
PH Y ceiver
M A C2
Sw itch
Engine2
RX+-[3]
TX+-[3]
10B ased-T or
100B ased-T
PH Y ceiver
M A C3
Sw itch
Engine3
10B ased-T or
100B ased-T
PH Y ceiver
M A C4
Sw itch
Engine4
RX+-[4]
TX+-[4]
TXC/RXC
r
TXD/RXD
RXC/TXC
RXDV/TXEN
RXD/TXD
COL
SEL_MIIMAC
M AC
m ode
TXEN/RXDV
Inter
face
LED
PH Y
m ode
M ode
Select
C ircuit
controlle
EN_RST_BLNK
LED_BLNK_TIME
LED_SPD[4:0]
LED_ACT[4:0]
LED_DUP[4:0]
LED_ADD[4:0]
P4MODE[1:0]
2002/04/09
4
Rev.1.0
RTL8305SB
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
G ND
TEST#
VD D
LED _AD D [4]/G YM O D E
P4M O D E[0]
P4M O D E[1]
LED _AD D [3]/G XM O D E
LED _AD D [2]/SETG R O U P
G ND
LED _AD D [1]/D ISVLAN
LED _AD D [0]/D ISFC AU TO O FF
LO O PLED #/D ISTAG PR I
EN _R ST_BLN K
LED _BLN K_TIM E
D ISPO R TPR I[4]
VD D
D ISPO R TPR I[3]
D ISPO R TPR I[2]
D ISPO R TPR I[1]
D ISPO R TPR I[0]
Q W EIG H T[1]
Q W EIG H T[0]
D ISBR D C TR L
G ND
EN AN EG _BKPR S
G YEN FC
G XEN FC
SD A_M D IO
SC L_M D C
EN EEPR O M
R ESER VED 1
C K25M O U T
VD D
EN _AU TO XO VER
SEL_M IIM AC #/D ISD SPR I
M R XD [3]/PTXD [3]
M R XD [2]/PTXD [2]
G ND
4. Pin Assignments
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
RTL8305SB
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
GND
M R XD [1]/PTXD [1]
VD D
M R XD [0]/PTXD [0]
M R XD V/PTXEN
M R XC /PTXC
M C O L/PC O L
M TXD [3]/PR XD [3]/P4IR TAG [1]
M TXD [2]/PR XD [2]/P4IR TAG [0]
M TXD [1]/PR XD [1]/LED M O D E[1]
M TXD [0]/PR XD [0]/LED M O D E[0]
VD D
M TXEN /PR XD V
M TXC /PR XC
M G ND
P4LN KSTA#
P4D U PSTA/P4FU LL
P4SPD STA/P4SPD 100
P4FLC TR L/P4EN FC
X2
X1
VD D
R TT2
R TT3
R ESET#
G ND
RG ND
TG N D
TXO P[0]
TXO N [0]
TVD D
TVD D
TXO N [1]
TXO P[1]
TG N D
RG ND
R XIP[1]
R XIN [1]
R VD D
R VD D
R XIN [2]
R XIP[2]
RG ND
TG N D
TXO P[2]
TXO N [2]
TVD D
TVD D
TXO N [3]
TXO P[3]
TG N D
RG ND
R XIP[3]
R XIN [3]
R VD D
R VD D
R XIN [4]
R XIP[4]
RG ND
TG N D
TXO P[4]
TXO N [4]
TVD D
M VD D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
LED _D U P[0]/P4A N EG
LED _A CT[0]/G X A N EG
LED _SPD [0]/G Y A N EG
VDD
LED _D U P[1]/G X SPD 100
LED _A CT[1]/G Y SPD 100
LED _SPD [1]/G X FU LL
LED _D U P[2]/G Y FU LL
LED _A CT[2]/EN FO RW A RD
GND
LED _SPD [2]/BCIN D RO P
VDD
LED _D U P[3]/M A X 1536
LED _A CT[3]/RESERV ED 2
LED _SPD [3]/EN D EFER
LED _D U P[4]/48PA SS1
LED _A CT[4]/D ISA RP
LED _SPD [4]/D ISLEA K Y
V CTRL
AGND
AGND
IBREF
RV D D
AVDD
RX IN [0]
RX IP[0]
128 Pin RTL8305SB
2002/04/09
5
Rev.1.0
RTL8305SB
' I ' stands for inputs; 'O' stands for outputs; 'A' stands for analog; 'D' stands for digital
NAME
RGND
TGND
TXOP[0]
TXON[0]
TVDD
TVDD
TXON[1]
TXOP[1]
TGND
RGND
RXIP[1]
RXIN[1]
RVDD
RVDD
RXIN[2]
RXIP[2]
RGND
TGND
TXOP[2]
TXON[2]
TVDD
TVDD
TXON[3]
TXOP[3]
TGND
RGND
RXIP[3]
RXIN[3]
RVDD
RVDD
RXIN[4]
RXIP[4]
RGND
TGND
TXOP[4]
TXON[4]
TVDD
MVDD
GND
RESET#
RTT3
RTT2
VDD
X1
X2
P4FLCTRL/P4ENFC
P4SPDSTA/P4SPD100
P4DUPSTA/P4FULL
P4LNKSTA#
MGND
MTXC/PRXC
MTXEN/PRXDV
VDD
MTXD[0]/PRXD[0]/LEDMODE[0]
MTXD[1]/PRXD[1]/LEDMODE[1]
MTXD[2]/PRXD[2]/P4IRTAG[0]
MTXD[3]/PRXD[3]/P4IRTAG[1]
MCOL/PCOL
MRXC/PTXC
MRXDV/PTXEN
MRXD[0]/PTXD[0]
VDD
MRXD[1]/PTXD[1]
GND
2002/04/09
PIN No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
TYPE
AGND
AGND
AO
AO
AVDD
AVDD
AO
AO
AGND
AGND
AI
AI
AVDD
AVDD
AI
AI
AGND
AGND
AO
AO
AVDD
AVDD
AO
AO
AGND
AGND
AI
AI
AVDD
AVDD
AI
AI
AGND
AGND
AO
AO
AVDD
DVDD
DGND
I
O
O
DVDD
I
O
I
I
I
I
DGND
I/O
O
DVDD
I/O
I/O
I/O
I/O
I/O
I/O
I
I
DVDD
I
DGND
6
NAME
GND
MRXD[2]/PTXD[2]
MRXD[3]/PTXD[3]
SEL_MIIMAC#/DISDSPRI
EN_AUTOXOVER
VDD
CK25MOUT
RESERVED1
ENEEPROM
SCL_MDC
SDA_MDIO
GXENFC
GYENFC
ENANEG_BKPRS
GND
DISBRDCTRL
QWEIGHT[0]
QWEIGHT[1]
DISPORTPRI[0]
DISPORTPRI[1]
DISPORTPRI[2]
DISPORTPRI[3]
VDD
DISPORTPRI[4]
LED_BLNK_TIME
EN_RST_BLNK
LOOPLED#/DISTAGPRI
LED_ADD[0]/DISFCAUTOOFF
LED_ADD[1]/DISVLAN
GND
LED_ADD[2]/SETGROUP
LED_ADD[3]/GXMODE
P4MODE[1]
P4MODE[0]
LED_ADD[4]/GYMODE
VDD
TEST#
GND
LED_DUP[0]/P4ANEG
LED_ACT[0]/GXANEG
LED_SPD[0]/GYANEG
VDD
LED_DUP[1]/GXSPD100
LED_ACT[1]/GYSPD100
LED_SPD[1]/GXFULL
LED_DUP[2]/GYFULL
LED_ACT[2]/ENFORWARD
GND
LED_SPD[2]/BCINDROP
VDD
LED_DUP[3]/MAX1536
LED_ACT[3]/RESERVED2
LED_SPD[3],/ENDEFER
LED_DUP[4]/48PASS1
LED_ACT[4]/DISARP
LED_SPD[4]/DISLEAKY
VCTRL
AGND
AGND
IBREF
RVDD
AVDD
RXIN[0]
RXIP[0]
PIN No.
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
TYPE
DGND
I
I
I/O
I
DVDD
O
I/O
I
I/O
I/O
I
I
I
DGND
I
I
I
I
I
I
I
DVDD
I
I
I
I/O
I/O
I/O
DGND
I/O
I/O
I
I
I/O
DVDD
I/O
DGND
I/O
I/O
I/O
DVDD
I/O
I/O
I/O
I/O
I/O
GND
I/O
DVDD
I/O
I/O
I/O
I/O
I/O
I/O
O
AGND
AGND
A
AVDD
AVDD
AI
AI
Rev.1.0
RTL8305SB
5. Pin Descriptions
' I ' stands for inputs; 'O' stands for outputs; 'A' stands for analog; 'D' stands for digital
Upon reset: defined as a short time after at the end of a hardware reset. After reset: defined as the time after the specified
"Upon Reset" time.
5.1 Media Connection Pins
Pin Name
RXIP[4:0]
RXIN[4:0]
TXOP[4:0]
TXON[4:0]
Pin No. Type
11,12,15, AI
16,27,28,
31,32
127,128
3,4
7,8
19,20
23,24
35,36
AO
Description
Differential Receive Data Input: Shared by 100Base-TX, 10Base-T
and 100Base-FX.
UTP or FX depends on pin GxMode/GyMode/P4Mode[1:0].
Note: The 8305SB uses these pins for UTP and Fiber. The 8305S uses
these pins for UTP only.
Differential Transmit Data Output: Shared by 100Base-TX, 10Base-T
and 100Base-FX.
UTP or FX depends on pin GxMode/GyMode/P4Mode[1:0].
Note: The 8305SB uses these pins for UTP and Fiber. The 8305S uses
these pins for UTP only.
Default
5.2 Configuration Pins
Pin Name
Pin No.
ENANEG_BKPRS
78
Type
I
Description
Enable Auto-Negotiation Back Pressure: This pin sets back pressure
for auto-negotiation mode for all UTP ports.
1: Enable
0: Disable
8305SB=ENANEG_BKPRS, 8305S=ENBKPRS. This pin has the same
function for both the RTL8305SB and RTL8305S. The RTL8305SB also
supports Force mode (through P4ENFC/GxENFC/GyENFC), but this pin
is used only for Auto-Negotiation mode. The pin name is changed to
differentiate between “Enable back pressure for Auto-Negotiation mode”
and “Enable backpressure for Force mode.”
Default
1
Disable Broadcast Storm Control:
1= Disable
0= Enable
8305SB=DISBRDCTRL, 8305S=ENBRDCTRL. The RTL8305SB will
disable this function when pin DISBRDCTRL is left floating. However, the
RTL8305S will enable this function when pin ENBRDCTRL is left floating.
LED Blink Time: This pin selects the blinking speed of the activity and
collision LEDs.
1: On 43ms, then Off 43ms
0: On 120ms, then Off 120ms
Enable Reset Blink: This pin enables the blinking of the LEDs upon
reset for diagnosis purposes.
1: Enable reset LED blinking
0: Disable reset LED blinking
8305SB=EN_RST_BLNK, 8305S=DIS_RST_BLNK#. This pin has the
same function for both the RTL8305SB and RTL8305S. The pin name
has been changed for convenience.
1
DISBRDCTRL
80
I
LED_BLNK_TIME
89
I
EN_RST_BLNK
90
I
2002/04/09
7
1
1
Rev.1.0
RTL8305SB
5.3 Port4 External MAC Interface Pins
The external device should be 2.5V compatible, because the digital output of the RTL8305SB is 2.5V. The input or
input/output pins listed below do not have internal pull-high resistors for connecting to external devices. External pull-high
resistors are recommended for those floating input pins without internal pull-high resistor if reduced power consumption is
desired.
In order to differentiate between MAC and PHY mode, the name of the pins change for PHY mode. For example:
RTL8305SB=MRXD[0]/PTXD[0], RTL8305S=MRXD[0]/MTXD[0].
Tip: Connect the input of Port4 to the output of the external device.
Pin Name
MRXD[3:0]/
PTXD[3:0]
Pin No. Type
67,66,63,
I
61
MRXDV/PTXEN
60
I
MRXC/PTXC
59
I/O
MCOL/PCOL
58
I/O
Description
For MAC mode MII, these pins are MRXD[3:0], MII receive data nibble.
For PHY mode MII, these pins are PTXD[3:0], MII transmit data nibble.
For PHY mode SNI, PTXD[0] is serial transmit data.
Because this pin can be connected to a 2.5V or 3.3V devices, these pins
have no internal pull-high resistor.
RTL8305SB = MRXD[3:0] / PTXD[3:0], RTL8305S = MRXD[3:0] /
MTXD[3:0]. In order to differentiate between MAC and PHY modes,
the RTL8305SB changes the pin name for PHY mode.
For MAC mode MII, this pin represents MRXDV, MII receive data valid.
For PHY mode MII, this pin represents PTXEN, MII transmit enable.
For PHY mode SNI, this pin represents PTXEN, transmit enable.
Because this pin can be connected to a 2.5V or 3.3V device, this pin has
no internal pull-high resistor.
RTL8305SB = MRXDV/PTXEN, RTL8305S = MRXDV/MTXEN. In
order to differentiate between MAC and PHY mode, the RTL8305SB
changes the pin name for PHY mode.
For MAC mode MII, it is receive clock, MRXC (acts as input).
For PHY mode MII/PHY mode SNI, it is transmit clock, PTXC (acts as output).
Because this pin can be connected to a 2.5V or 3.3V device, this pin has
no internal pull-high resistor.
RTL8305SB = MRXC/PTXC, RTL8305S = MRXC/MTXC. In order to
differentiate between MAC and PHY mode, the RTL8305SB changes
the pin name for PHY mode.
For MAC mode MII, this pin represents MCOL collision (acts as input)
For PHY mode MII/PHY mode SNI, this pin represents PCOL collision
(acts as output)
Because this pin can be connected to a 2.5V or 3.3V device, this pin has
no internal pull-high resistor.
RTL8305SB = MCOL/PCOL, RTL8305S = MCOL. In order to
differentiate between MAC and PHY mode, the RTL8305SB changes the
pin name for PHY mode.
Default
Cont…
2002/04/09
8
Rev.1.0
RTL8305SB
MTXD[3]/
PRXD[3]/
P4IRTag[1]
57
MTXD[2]/
PRXD[2]/
P4IRTag[0]
56
MTXD[1]/PRXD[1]/
LEDMode[1]
55
MTXD[0]/PRXD[0]/
LEDMode[0]
54
I/O
I/O
Output after reset:
For MAC mode MII (P4Mode[1:0]=11), these pins are MTXD[3:0],
MII transmit data of MAC.
For PHY mode MII (P4Mode[1:0]=01), these pins are PRXD[3:0], MII
receive data of PHY.
For PHY mode SNI (P4Mode[1:0]=00), PRXD[0] is SNI serial receive data.
Input upon reset: P4IRTag[1:0]
Insert/Remove Priority Tag of Port4.
11: Do not insert/remove Tag from Output High and Low Queue of Port4.
10: Insert Tag from Output High and Low Queue of Port4.
01: Insert Tag from Output High Queue only of Port4.
00: Remove Tag from Output High and Low Queue of Port4.
RTL8305SB = MTXD[3:2]/PRXD[3:2]/P4IRTag[1:0], RTL8305S =
MTXD[3:2]/MRXD[3:2]. In order to differentiate between MAC and
PHY mode, the RTL8305SB changes the pin name for PHY mode. For
RTL8305SB: These pins are input pins used for strapping upon reset and
used as output pins (output data) after reset. For RTL8305S: These pins
are used as output pins (output data) after reset.
These pins are used for Port4 only. Use serial EEPROM for other ports.
Output after reset:
For MAC mode MII (P4Mode[1:0]=11), these pins are MTXD[3:0],
MII transmit data of MAC.
For PHY mode MII (P4Mode[1:0]=01), these pins are PRXD[3:0], MII
receive data of PHY.
For PHY mode SNI (P4Mode[1:0]=00), PRXD[0] is SNI serial receive
data.
Input upon reset: LEDMode[1:0]
Each port has four LED indicator pins. Each pin may has different
indicator meaning set by pins LEDMode[1:0].
LEDMode[1:0]=11 : Speed + Link/Act + Duplex/Col + Link/Act/Spd.
LEDMode[1:0]=10 : Speed + Act + Duplex/Col + Bi-color Link/Active.
LEDMode[1:0]=01 : Speed + RxAct + TxAct + Link.
LEDMode[1:0]=00 : Speed + Link/Act + Col + Duplex.
All LED statuses are represented as active-low or high depending on
input strapping, except Bi-color Link/Act in Bi-color LED mode, whose
polarity depends on Spd status.
Link/Act/Spd: Link, Activity, and Speed Indicator. On for link
established. Blinking every 43ms when the corresponding port is
transmitting or receiving in 100Mb/s. Blinking every 120ms when the
port is transmitting or receiving in 10Mb/s.
RTL8305SB = MTXD[1:0]/PRXD[1:0]/LEDMode[1:0], RTL8305S =
MTXD[1:0]/MRXD[1:0]. In order to differentiate between MAC and
PHY mode, the RTL8305SB changes the pin name for PHY mode. For
RTL8305SB: These pins are input pins used for strapping upon reset and
used as output pins (output data) after reset. For RTL8305S: These pins
are used as output pins (output data) after reset.
11
11
Cont…
2002/04/09
9
Rev.1.0
RTL8305SB
MTXEN/PRXDV
52
O
MTXC/PRXC
51
I/O
P4MODE[1:0]
97,98
I
P4LNKSTA#
49
I
For MAC mode MII, this pin represents MTXEN, MII transmit enable.
For PHY mode MII, this pin represents PRXDV, MII received data valid.
For PHY mode SNI, this pin represents PRXDV, received data valid.
RTL8305SB = MTXEN/PRXDV, RTL8305S = MTXEN/MRXDV. In
order to differentiate between MAC and PHY mode, the RTL8305SB
changes the pin name for PHY mode.
For MAC mode MII, it is transmit clock, MTXC (acts as input).
For PHY mode MII/PHY mode SNI, it is receive clock, PRXC (acts as output).
Because this pin can be connected to a 2.5V or 3.3V device, this pin has
no internal pull-high resistor.
RTL8305SB = MTXC/PRXC, RTL8305S = MTXC/MRXC. In order to
differentiate between MAC and PHY mode, the RTL8305SB changes
the pin name for PHY mode.
Select Port 4 operating mode:
11: UTP / MAC mode MII
10: 100Base-FX mode
01: PHY mode MII
00: PHY mode SNI
The RTL8305SB has 4 options and the RTL8305S has 3 options.
Port4 Link Status for MAC: When the PHY part of Port4 is not used,
this pin determines the link status of the Port4 MAC in real-time. That is
link status of real-time for MII MAC/MII PHY/SNI PHY only. This pin
is low active.
1: No Link.
0: Link
When P4MODE[1:0]=11 (UTP/MAC mode MII), this pin determines
the link status of MAC mode MII only in real time. The link status of
UTP mode is provided by the internal PHY in real time. If both UTP and
MII port are linked OK, UTP has higher priority.
When P4MODE[1:0]=10 (100Base-FX mode), this pin does nothing.
The internal PHY will provide the link status to the MAC in real time.
When P4MODE[1:0]=01 (PHY mode MII), this pin determines the link
status of Port4 in real time.
When P4MODE[1:0]=00 (PHY mode SNI), this pin determines the link
status of Port4 in real time.
This pin should be left floating in UTP or FX mode, and pulled down in
the other three modes.
In MAC mode MII/ PHY mode MII/ PHY mode SNI, configuration of
this pin will not set the link status of the internal register. The link status
depends on the external PHY or MAC.
1
11
1
Cont…
2002/04/09
10
Rev.1.0
RTL8305SB
P4DUPSTA/
P4FULL
48
I
Port4 Duplex Status: Port4 initial configuration pin for Duplex upon
reset for PHY of UTP or FX mode and Duplex Status for MAC of other
mode in real time after reset.
1: Full duplex
0: Half duplex
When P4MODE[1:0]=11 (UTP/MAC mode MII), this pin provides the
initial duplex configuration for the PHY part upon reset (UTP) then
determines the duplex status of MAC mode MII in real time after reset.
The duplex status of the PHY part (UTP) is provided by the internal
PHY in real time after reset.
When P4MODE[1:0]=10 (100Base-FX mode), this pin provides the
initial register configuration of duplex for PHY part upon reset (FX).
The duplex status of the PHY part (FX) is provided by the internal PHY
in real time after reset.
When P4MODE[1:0]=01 (PHY mode MII), this pin determines the
duplex status of Port4 in real time after reset.
When P4MODE[1:0]=00 (PHY mode SNI), this pin determines the
duplex status of Port4 in real time after reset.
8305SB = P4DUPSTA/P4FULL, 8305S = P4DUPSTA#.
In order to provide Full duplex as the default value for the PHY, this pin
is changed as high active.
In 100Base-Fx/ MAC mode MII/ PHY mode MII/ PHY mode SNI, the
configuration of this pin after reset will not set the link status of the
internal register. The link status depends on the external PHY or MAC.
1
Cont…
2002/04/09
11
Rev.1.0
RTL8305SB
P4SPDSTA/
P4SPD100
47
I
P4FLCTRL/
P4EnFC
46
I
Port4 Speed Status: Port4 initial configuration pin for Speed upon reset
for PHY of UTP mode only and Speed Status for MAC of other mode in
real time after reset.
1: 100Mbps
0: 10Mbps
When P4MODE[1:0]=11 (UTP/MAC mode MII), this pin provides the
initial configuration of speed for the PHY part upon reset (UTP) then
determines speed status of MAC mode MII in real time after reset. The
speed status of the PHY part (UTP) is provided by the internal PHY in
real time after reset.
When P4MODE[1:0]=10 (100Base-FX mode), speed is dedicated to
100M. This pin does nothing and should be left floating.
When P4MODE[1:0]=01 (PHY mode MII), this pin determines the
duplex status of Port4 in real time after reset.
When P4MODE[1:0]=00 (PHY mode SNI), speed is dedicated to
10MHz clock rate. This pin should be pulled down.
For the application listed below, this pin should be left floating:
For P4MODE[1:0]=10 (100Base-FX mode).
For the application listed below, this pin should be pulled down:
For PHY mode SNI, speed is dedicated to 10MHz clock rate.
8305SB = P4SPDSTA/P4SPD100, 8305S = P4SPDSTA#.
In order to provide 100M for the default value for PHY, this pin is
changed as high active.
Port4 Flow Control: Port4 initial configuration pin for Flow Control
upon reset for PHY of UTP and FX mode and Flow Control Status for
MAC of other mode in real time after reset.
1=Enable Flow Control ability.
0=Disable Flow Control ability.
When P4MODE[1:0]=11 (UTP/MAC mode MII), this pin provides the
initial configuration of flow control for the PHY part upon reset (UTP)
then determines the flow control status of MAC mode MII in real time
after reset. The flow control status of PHY part (UTP) is provided by the
internal PHY in real time after reset.
When P4MODE[1:0]=10 (100Base-FX mode), this pin provides the
initial configuration of flow control for the PHY part upon reset (FX).
When P4MODE[1:0]=01 (PHY mode MII), this pin determines the
duplex status of Port4 in real time after reset.
When P4MODE[1:0]=00 (PHY mode SNI), flow control should be
disabled. This pin should be pulled down.
8305SB = P4FLCTRL/P4EnFC, 8305S = P4FLCTRL#.
In order to enable flow control ability for the PHY, this pin is changed as
high active.
1
1
Cont…
2002/04/09
12
Rev.1.0
RTL8305SB
SEL_MIIMAC#/
DisDSPri
68
I/O
Output after reset = SEL_MIIMAC# used for LED:
When P4MODE[1:0]=11, this pin indicates whether the UTP path or the
MII MAC path is selected. Otherwise, this pin is of no use.
The LED statuses are represented as active-low or high depending on
input strapping.
=> If Input=1: Output 0= MII MAC port is selected. 1= UTP is selected.
=> If Input=0: Output 1= MII MAC port is selected. 0= UTP is selected.
While P4MODE[1:0]=11, RTL8305S supports UTP/MII MAC
auto-detection function via the link status of Port4 UTP and the status of
pin P4LNKSTA# and MAC mode MII. UTP has higher priority over the
MAC mode MII.
Input upon reset = DisDSPri. Disable Differentiated Service Priority.
1: Disable DS priority; 0: Enable DS priority
8305SB = SEL_MIIMAC#/DisDSPri, 8305S = SEL_MIIMAC#.
1
5.4 Miscellaneous Pins
Pin Name
X1
X2
CK25MOUT
Pin No.
44
45
71
Type
I
O
O
RESET#
40
I
IBREF
124
A
VCtrl
121
O
RTT3
41
O
RTT2
42
O
TEST#
101
I/O
2002/04/09
Description
25MHz crystal or oscillator clock input. The clock tolerance is +-50ppm.
To crystal input, when using an oscillator, this pin should be floating.
25MHz clock output. The source of this output is clock from X1 and X2.
This pin is used to support an extra 25M clock for the external device
(for example: HomePNA PHY).
The output voltage of the RTL8305SB is 2.5V. The output voltage of the
RTL8305S is 3.3V.
Active low reset signal: To complete reset function, this pin must be
asserted for at least 10ms. After reset, about 30ms is needed for the
RTL8305SB to complete internal test functions and initialization.
This pin is a Schmitt input.
Because this pin can be connected to a 2.5V or 3.3V device, this pin has
no internal pull-high resistor.
Control transmit output waveform Vpp: This pin should be grounded
through a 1.96KΩ resistor.
Voltage control to external regulator: This signal controls a power
PNP transistor to generate the 2.5V power supply.
8305SB = VCtrl, 8305S = TEST#.
Cap+ for future use: Reserve capacitors in layout for future use, but do
not use those capacitors in the BOM.
8305SB = RTT3, 8305S = TESTCLK.
Cap- for future use: Reserve capacitors in layout for future use, but do
not use those capacitors in the BOM.
8305SB = RTT2, 8305S = TESTDATA.
Reserved pin for internal use. Should be left floating.
13
Default
1
Rev.1.0
RTL8305SB
5.5 Per Port LED Pins
Each port has four LED indicator pins. Each pin may have different indicator meanings as set by pins LEDMode[1:0].
All LED statuses are represented as active-low or high depending on input strapping, except Bi-color Link/Act in Bi-color
LED mode, whose polarity depends on Spd status.
Those pins which are dual function pins are output for LED or input for strapping. Below are LED descriptions only.
Pin Name
LED_SPD[4:0]/…
Pin No.
120,
117,
113,
109,
105
Type
I/O
LED_ACT[4:0]/…
119,
116,
111,
108,
104
I/O
LED_DUP[4:0]/…
118,
115,
110,
107,
103
I/O
LED_ADD[4:0]/…
99,96,
95,93,
92
I/O
2002/04/09
Description
Output after reset = used for 1st LED:
LEDMode[1:0]=11 -> Speed (0n=100, Off=10)
LEDMode[1:0]=10 -> Speed (0n=100, Off=10)
LEDMode[1:0]=01 -> Speed (0n=100, Off=10)
LEDMode[1:0]=00 -> Speed (0n=100, Off=10)
Input upon reset = … Refer below for each pin.
Output after reset = used for 2nd LED:
LEDMode[1:0]=11 -> Link/Act: (On=Link, Off=no Link, Flash=Tx or
Rx activity)
LEDMode[1:0]=10 -> Act: (Off=no activity, ON=Tx or Rx activity)
LEDMode[1:0]=01 -> RxAct: (Off=no activity, ON=Rx activity)
LEDMode[1:0]=00 -> Link/Act: (On=Link, Off=no Link, Flash=Tx or
Rx activity)
Input upon reset = … Refer below for each pin.
Output after reset = used for 3rd LED:
LEDMode[1:0]=11 -> Duplex/Col: (On=Full, Off=Half with no
collision, Flash=Collision)
LEDMode[1:0]=10 -> Duplex/Col: (On=Full, Off=Half with no
collision, Flash=Collision)
LEDMode[1:0]=01 -> TxAct: (Off=no activity, ON=Tx activity)
LEDMode[1:0]=00 -> Col: (Off=Half with no collision, ON=Collide)
Input upon reset = … Refer below for each pin.
Output after reset = used for 4th LED:
LEDMode[1:0]=11 -> Link/Act/Spd: On for link established. Blinking
every 43ms when the corresponding port is transmitting or receiving in
100Mb/s. Blinking every 120ms when the port is transmitting or
receiving in 10Mb/s.
LEDMode[1:0]=10 -> Bi-color Link/Active: polarity depends on Spd
status. See Figure2 and Table1.
LEDMode[1:0]=01 -> Link: (On=Link, Off=no Link)
LEDMode[1:0]=00 -> Duplex: (On=Full, Off=Half)
Input upon reset = … Refer below for each pin.
8305SB = LED_ADD[4:0]/…, 8305S = NC.
14
Default
11111
11111
11111
11111
Rev.1.0
RTL8305SB
5.6 Power Pins
Pin Name
TVDD
Type
P
AVDD
Pin No.
5,6,21,
22,37
13,14
29,30
126
RVDD
125
P
MVDD
38
P
43,53
62,70
87,100
106,114
1,10,17,
26,33
2,9,18,
25,34
122
123
50
P
RVDD
VDD
RGND
TGND
AGND
MGND
GND
2002/04/09
39,64,
65,79
94,102
112
P
P
Description
3.3V Analog Transmit Power
2.5V Analog Receive Power
8305SB = 2.5V, 8305S = 3.3V.
3.3V Analog Power
8305SB = 3.3V AVDD, 8305S = 3.3V RVDD.
2.5V Analog Receive Power
8305SB = 2.5V RVDD, 8305S = 3.3V AVDD.
2.5V Internal RAM Power
8305SB = 2.5V, 8305S = 3.3V.
2.5V Digital Power
8305SB = 2.5V, 8305S = 3.3V.
P
Analog Ground
P
Analog Ground
P
Analog GND
Pin122 for 8305SB = AGND, 8305S = DGND.
Internal RAM GND
Pin50 for 8305SB = MGND, 8305S = GND.
Digital GND
Pin64 for 8305SB = GND, 8305S = MGND.
P
P
Default
15
Rev.1.0
RTL8305SB
5.7 Reserved Pins
Pin Name
RESERVED1
Pin No.
72
Type
I/O
Description
Reserved: Reserved pin for internal use. Should be left floating.
Default
1
5.8 Serial EEPROM and SMI Pins
The serial EEPROM and external device should be 2.5V compatible, as the output of the RTL8305SB is 2.5V.
If the external device output is 3.3V. There are 0.7V (3.3V–2.5V) on pull-high resistors which one side is a 3.3V external
device and the other side is 2.5V VDD. There are 0.7V (3.3V–2.5V) on pull-high resistors which one side is 3.3V VDD and
the other side is the 2.5V output of the RTL8305SB.
Pin Name
EnEEPROM
Pin No.
73
Type
I
SCL_MDC
74
I/O
SDA_MDIO
75
IO
2002/04/09
Description
Enable EEPROM: This pin sets the RTL8305SB to enable the loading
of the serial EEPROM upon reset.
1: Enable
0: Disable
8305SB = EnEEPROM, 8305S = NC.
SCL or MDC: This pin is tri state when pin RESET#=0.
When pin EnEEPROM=1, this pin becomes SCL (output) to load the serial
EEPROM upon reset. Then this pin changes as MDC (input) after reset. In
this case, this pin should be pulled-high (2.5V) by an external resistor.
When pin EnEEPROM=0, this pin is MDC (input): 0 to 25MHz clock,
sourced by an external device to sample MDIO. In this case, if, and only
if, this pin is floating, it needs an external pull-high (2.5V) resistor.
Because this pin can be connected to a 2.5V or 3.3V device, this pin has
no internal pull-high resistor.
8305SB = SCL_MDC, 8305S = NC.
SDA or MDIO: This pin is tri state when RESET#=0.
When pin EnEEPROM=1, this pin becomes SDA (input/output) to load
the serial EEPROM upon reset. Then this pin changes as MDIO
(input/output) after reset.
When pin EnEEPROM=0, this pin is MDIO (input/output).
It should be pulled-high by an external resistor.
Because this pin can be connected to a 2.5V or 3.3V device, this pin has
no internal pull-high resistor.
8305SB = SDA_MDIO, 8305S = NC.
16
Default
1
Rev.1.0
RTL8305SB
5.9 Strapping Pins
Those pins which are dual function pins are output for LED or input for strapping. Below are strapping descriptions only.
Pin Name
Pin No.
EN_AUTOXOVER
69
Type
I
QWeight[1]
QWeight[0]
82
81
I
DisPortPri[4]
DisPortPri[3]
DisPortPri[2]
DisPortPri[1]
DisPortPri[0]
88
86
85
84
83
I
LoopLED#
/DisTagPri
91
I/O
LED_ADD[0]/
DisFCAutoOff
LED_ADD[1]/
DISVLAN
92
93
I/O
I/O
Description
Enable Auto crossover function.
1: Enable auto crossover detection.
0: Disable auto crossover detection. MDI only.
Weighted round robin ration of priority queue.
The frame service rate of High-pri queue: Low-pri queue
11: 16:1
10: always high priority queue first
01: 8:1
00: 4:1
8305SB = QWeight[1:0], 8305S = NC.
Enable Port based priority QoS function.
DisPortPri[4]: 1=Disable port 4 priority. 0=Enable port 4 priority.
DisPortPri[3]: 1=Disable port 3 priority. 0=Enable port 3 priority.
DisPortPri[2]: 1=Disable port 2 priority. 0=Enable port 2 priority.
DisPortPri[1]: 1=Disable port 1 priority. 0=Enable port 1 priority.
DisPortPri[0]: 1=Disable port 0 priority. 0=Enable port 0 priority.
8305SB = DisPortPri[4:0], 8305S = NC.
Output after reset = LoopLED# used for LED: If the Loop detection
function is enabled, this pin indicates whether Network loop is detected
or not. Otherwise, this pin is of no use.
The LED statuses are represented as active-low or high depending on
input strapping.
=> If Input=1: Ouput 0= Network loop is detected. 1=No loop.
=> If Input=0: Ouput 1= Network loop is detected. 0= No loop.
Input upon reset = Disable 802.1p VLAN Tag priority based QoS
function.
1: Disable
0: Enable
8305SB = LoopLED#/DisTagPri, 8305S = EnP4LED. 8305SB moves
the EnP4LED option into EEPROM.
Output after reset = used for LED:
Input upon reset = Disable Auto Turn Off function of Flow Control
Ability.
1: Disable
0: Enable. Enable Auto turn off low priority queue's flow control ability
1~2 sec whenever the port received a VLAN-tag or TOS/DS high
priority frame. The flow control ability will re-enabled when there is not
received and high priority frame during 1~2 sec.
Output after reset = used for LED:
Input upon reset = Disable VLAN function.
1: Disable VLAN
0: Enable VLAN According to the internal registers
Default
1
11
11111
1
1
1
Cont…
2002/04/09
17
Rev.1.0
RTL8305SB
LED_ACT[2]/
EnForward
111
I/O
LED_SPD[2]/
BCInDrop
113
I/O
LED_DUP[3]/
Max1536
115
I/O
LED_DUP[4]/
48pass1
118
I/O
LED_SPD[3]/
EnDefer
117
LED_ACT[3]/
RESERVED2
116
LED_ACT[4]
/DisARP
119
I/O
LED_SPD[4]/
DisLeaky
120
I/O
2002/04/09
Output after reset = used for LED
Input upon reset = Enable to forward 802.1D specified reserved
group MAC addresses frame.
1: Forward reserved control frames, which DID=01-80-C2-00-00-03 to
01-80-C2-00-00-0F packets.
0: Filter reserved control packets, which DID=01-80-C2-00-00-03 to
01-80-C2-00-00-0F.
Output after reset = used for LED
Input upon reset = Broadcast Input Drop.
1: Use Broadcast Input drop mechanism.
0: Use Broadcast Output drop mechanism.
Output after reset = used for LED
Input upon reset = Maximum Frame Length 1536 Bytes
1: 1536 Bytes
0: 1552 Bytes
Output after reset = used for LED
Input upon reset = Back pressure Mode.
48pass1:
1: 48 pass 1: at most 48 consecutively collision to avoid repeater
partition when buffer is full.
0: Continuously collide to avoid packet loss when buffer is full.
EnDefer:
1: Enable Carrier Sense Deferring function for half duplex back pressure.
0: Disable Carrier Sense Deferring function for half duplex back pressure.
Output after reset = used for LED:
Input upon reset = Disable ARP broadcast to all VLAN.
1: Disable to broadcast the ARP broadcast packet to all VLANs.
0: Enable to broadcast the ARP broadcast packet to all VLANs.
ARP broadcast frame: DID is all F.
Output after reset = used for LED:
Input upon reset = Disable Leaky VLAN.
1: Disable to forward unicast frames to other VLAN.
0: Enable to forward unicast frames to other VLAN.
Broadcast and multicast frames adhere to the VLAN configuration.
18
1
1
1
111
1
1
Rev.1.0
RTL8305SB
5.10 Port Status Strapping Pins
Those pins which are dual function pins are output for LED or input for strapping. Below are strapping descriptions only.
Pin Name
LED_ADD[2]/
SetGroup
Pin No.
95
Type
I/O
LED_ADD[3]/
GxMode
96
I/O
LED_ADD[4]
/GyMode
99
I/O
LED_DUP[0]/
P4ANEG
103
I/O
LED_ACT[0]/
GxANEG
104
I/O
LED_SPD[0]
/GyANEG
105
I/O
LED_DUP[1]
/GxSpd100
107
I/O
Description
Output after reset = used for LED:
Input upon reset = Set group of port 1:
1: Port 0 is group X. Port 1, 2, and 3 are group Y
0: Port 0, and 1 are group X. Port 2, and 3 are group Y
Output after reset = used for LED:
Input upon reset = Group X operating mode:
1: UTP mode
0: FX mode
Output after reset = used for LED:
Input upon reset = Group Y operating mode:
1: UTP mode
0: FX mode
Output after reset = used for LED:
Input upon reset = Port4 Auto-Negotiation ability:
1: Enable auto-negotiation (NWAY mode)
0: Disable auto-negotiation (Force mode)
Upon reset, this pin sets Reg.0.12 of Port4. Strap after reset for initial
value of Port4 UTP mode only. This pin is not used for Port4 FX, MAC
mode MII, PHY mode MII, and PHY mode SNI.
Output after reset = used for LED:
Input upon reset = GroupX Auto-Negotiation ability:
1: Enable auto-negotiation (NWAY mode)
0: Disable auto-negotiation (Force mode)
Upon reset, this pin sets Reg.0. 12 of Group X. Strap after reset for initial
value of UTP mode only. This pin is not used for FX.
Output after reset = used for LED:
Input upon reset = GroupY Auto-Negotiation ability:
1: Enable auto-negotiation(NWAY mode)
0: Disable auto-negotiation (Force mode)
Upon reset, this pin sets Reg.0. 12 of Group Y. Strap after reset for initial
value of UTP mode only. This pin is not used for FX.
Output after reset = used for LED:
Input upon reset = GroupX 10Base-T/100Base-TX ability:
GxSpd100=1, GxFull=1
=> MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1
GxSpd100=1, GxFull=0
=> MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1
GxSpd100=0, GxFull=1;
=> MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1
GxSpd100=0, GxFull=0;
=> MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
Upon reset, this pin sets Reg.0.13. In addition, upon reset, this pin and
GxFull also sets Reg.4.8/4.7/4.6/4.5. Strap after reset for initial value of
Group X UTP mode only. This pin is not used for FX.
Default
1
1
1
1
1
1
1
Cont…
2002/04/09
19
Rev.1.0
RTL8305SB
LED_ACT[1]/
GySpd100
108
I/O
LED_SPD[1]/GxFu
ll
109
I/O
LED_DUP[2]/GyFu
ll
110
I/O
GxEnFC
76
I
GyEnFC
77
I
2002/04/09
Output after reset = used for LED:
Input upon reset = GroupY 10Base-T/100Base-TX ability:
GySpd100=1, GyFull=1
=> MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1
GySpd100=1, GyFull=0
=> MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1
GySpd100=0, GyFull=1;
=> MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1
GySpd100=0, GyFull=0;
=> MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
Upon reset, this pin sets Reg.0.13. In addition, upon reset, this pin and
GyFull also sets Reg.4.8/4.7/4.6/4.5. Strap after reset for initial value of
Group Y UTP mode only. This pin is not used for FX.
Output after reset = used for LED:
Input upon reset = GroupX Full Duplex ability:
Upon reset, this pin sets the default value of Reg.0.8. In addition, on
reset, this pin also sets Nway full-duplex ability on Reg.4.8 and Reg.4.6.
Strap after reset for initial value of Group X UTP or FX mode. FX can
be Force 100 Full or Force 100 Half.
Output after reset = used for LED:
Input upon reset = GroupY Full Duplex ability:
Upon reset, this pin sets the default value of Reg.0.8. On reset, this pin
also sets Nway full-duplex ability on Reg.4.8 and Reg.4.6.
Strap after reset for initial value of Group Y UTP or FX mode. FX can
be Force 100 Full or Force 100 Half.
GroupX Enable Flow Control ability:
1: Enable Reg4.10 (NWAY Full duplex only), or “Enable Force Full
pause ability of Force mode (UTP Force mode or FX mode)”, or “Enable
Force Half Back Pressure ability of Force mode (UTP Force mode or FX
mode)”.
0: Disable Reg4.10 (NWAY Full duplex only), or “Disable Force Full
pause ability of Force mode (UTP Force mode or FX mode)”, or
“Disable Force Half Back Pressure ability of Force mode (UTP Force
mode or FX mode)”.
Strap after reset for initial value of Group X “UTP NWAY Full”, or
“UTP Force Full or Half mode”, or “FX Full or Half mode”.
8305SB = GxEnFC, 8305S = NWAYHALF#.
For 8305SB, the function of NWAYHALF# is replaced by 3 pins:
GxFull, GyFull, P4Full.
GroupY Enable Flow Control ability:
1: Enable Reg4.10 (NWAY Full duplex only), or “Enable Force Full
pause ability of Force mode (UTP Force mode or FX mode)”, or “Enable
Force Half Back Pressure ability of Force mode (UTP Force mode or FX
mode).”
0: Disable Reg4.10 (NWAY Full duplex only), or “Disable Force Full
pause ability of Force mode (UTP Force mode or FX mode)”, or
“Disable Force Half Back Pressure ability of Force mode (UTP Force
mode or FX mode).”
Strap after reset for initial value of Group Y “UTP NWAY Full”, or
“UTP Force Full or Half mode”, or “FX Full or Half mode.”
8305SB = GyEnFC, 8305S = ENFCTRL.
For 8305SB, the function of ENFCTRL is replaced by 3 pins: GxEnFC,
GyEnFC, and P4EnFC.
20
1
1
1
1
1
Rev.1.0
RTL8305SB
6. Register Description
Hardware Reset: pin RESET# = 0 to 1. Reset all then load EEPROM and Pin registers with serial EEPROM and Pins strappings.
Soft Reset: Write bit15 of Reg16 of PHY3 as 1. Reset all except loading EEPROM and Pin Registers with serial EEPROM and Pins.
After updating the EEPROM or Pin registers via SMI, the external device has to do soft reset in order to change the configuration.
Name
Soft Reset
PHY
Register
Register Description
Port0 PHY Reg
No
0
0
Control Register
1
Status Register
4
Auto-Negotiation Advertisement Register
5
Auto-Negotiation Link Partner Ability Register
6
Auto-Negotiation Expansion Registers
Port1 PHY Reg
No
1
0
Control Register
1
Status Register
4
Auto-Negotiation Advertisement Register
5
Auto-Negotiation Link Partner Ability Register
6
Auto-Negotiation Expansion Registers
Port2 PHY Reg
No
2
0
Control Register
1
Status Register
4
Auto-Negotiation Advertisement Register
5
Auto-Negotiation Link Partner Ability Register
6
Auto-Negotiation Expansion Registers
Port3 PHY Reg
No
3
0
Control Register
1
Status Register
4
Auto-Negotiation Advertisement Register
5
Auto-Negotiation Link Partner Ability Register
6
Auto-Negotiation Expansion Registers
Port4 PHY Reg
No
4
0
Control Register
1
Status Register
4
Auto-Negotiation Advertisement Register
5
Auto-Negotiation Link Partner Ability Register
6
Auto-Negotiation Expansion Registers
EEPROM Reg0
EEPROM Reg1
Pin Reg
Pin & EEPROM Reg
Port Control Reg
EEPROM Reg
RO:
RW:
LL:
LH:
SC:
Need
Need
Need
Need
No
Need
0
1
2
2
3
3
16~22
16~31
16
17
16
17~20
Register for EEPROM
Register for EEPROM
Register for some Pins
Register for some Pins and EEPROM
Register for Port Control
Register for EEPROM
Read Only
Read/Write
Latch Low until clear
Latch High until clear
Self Clearing
2002/04/09
21
Rev.1.0
RTL8305SB
6.1 PHY0 to 4: PHY Register of Each Port
6.1.1 Register0: Control Register
Reg.bit
0.15
0.14
Name
Reset
Loopback
(digital loopback)
Description
Mode
Reset: 1: PHY reset. This bit is self-clearing.
RW/SC
Enable Loopback: This pin enables loopback from the MII TXD RW
to the MII RXD and ignores all the activities on the cable media.
Default
0
0
1: Enable loopback
0: Normal operation
This function is usable only when this PHY is 10Based-T full
duplex or 100Base-T full duplex.
0.13
Spd_Sel
The packet is forwarded from other PHY (could be 10Based-T,
or 100TX, or 100FX, both full and half duplex) by switch core
and will loopback to the switch core. It could be forwarded to
the other port or dropped depending on the destination and
source MAC address of the packet.
RW
Speed Select:
From pin
1: 100Mbps
0: 10Mbps
When Nway is enabled, this bit reflects the result of
auto-negotiation. (Read only)
When Nway is disabled, this bit can be set through SMI.
(Read/Write)
0.12
Auto Negotiation
Enable
When 100FX mode is enabled, this bit =1. (Read only)
1: Enable auto-negotiation process
0: Disable auto-negotiation process
RW
From pin
RW
0
RW
0
RW/SC
0
This bit can be set through SMI.(Read/Write)
When 100FX mode is enabled, this bit =0.(Read only)
0.11
Power Down
0.10
Isolate
0.9
Restart Auto
Negotiation
Duplex Mode
0.8
100FX should be force mode. In order to avoid errors, the
RTL8305SB will ignore the action to this bit when writing
Reg0.12 as 1 in 100FX mode.
1: Power down. All functions will be disabled except SMI
function and internal TXC to MAC.
0: Normal operation.
1: Electrically isolate the PHY from internal MII. The PHY is
still able to response to MDC/MDIO.
0: Normal operation
1: Restart Auto-Negotiation process.
0: Normal operation.
Duplex mode:
1: Full duplex operation
0: Half duplex operation
RW
From pin
RO
0
When Nway is enabled (Reg0.12=1), this bit reflects the result
of auto-negotiation. (Read only)
When Nway is disabled (Reg0.12=0, force mode of UTP or
100FX), this bit can be set through SMI*. (Read/Write)
100FX should be force mode. In order to avoid errors, the
RTL8305SB will ignore the action to this bit when writing
Reg0.12 as 1 in 100FX mode.
0.[7:0]
2002/04/09
Reserved
22
Rev.1.0
RTL8305SB
6.1.2 Register1: Status Register
Reg.bit
1.15
1.14
Name
100Base_T4
100Base_TX_FD
1.13
100Base_TX_HD
1.12
10Base_T_FD
1.11
10Base_T_HD
1.[10:7]
1.6
Reserved
MF Preamble
Suppression
Description
0: No 100Base-T4 capability.
1: 100Base-TX full duplex capable.
0: Not 100Base-TX full duplex capable.
1: 100Base-TX half duplex capable.
0: Not 100Base-TX half duplex capable.
1: 10Base-TX full duplex capable.
0: Not 10Base-TX full duplex capable.
1: 10Base-TX half duplex capable.
0: Not 10Base-TX half duplex capable.
Mode
RO
RO
Default
0
1
RO
1
RO
1
RO
1
RO
The RTL8305SB will accept management frames with RO
preamble suppressed.
0
1
The RTL8305SB accepts management frames without
preamble. Minimum of 32 preamble bits are required for the
first SMI read/write transaction after reset. One idle bit is
required between any two management transactions as defined
in IEEE802.3u specs.
1: Auto-negotiation process completed. MII Reg.4,5 are valid RO
if this bit is set.
0: Auto-negotiation process not completed.
1: Remote fault condition detected.
RO/LH
0: No remote fault.
When in 100FX mode, this bit means in-band signal
Far-End-Fault is detected.
1: Nway auto-negotiation capable. (permanently: 1)
RO
1.5
Auto-negotiate
Complete
1.4
Remote Fault
1.3
1.2
Auto-Negotiation
Ability
Link Status
1.1
Jabber Detect
1.0
Note: this function is not necessary for single chip.
Extended Capability 1: Extended register capable. (permanently: 1)
1: Link is established. If link had ever failed, this bit will be 0 RO/LL
until after reading this bit again.
0: Link is failed.
0: No Jabber detected.
RO
RO
0
0
1
0
0
1
6.1.3 Register4: Auto-Negotiation Advertisement Register
Reg.bit
4.15
Name
Next Page
4.14
4.13
Acknowledge
Remote Fault
4.[12:11]
4.10
Reserved
Pause
4.9
4.8
100Base-T4
100Base-TX-FD
4.7
100Base-TX
4.6
10Base-T-FD
4.5
10Base-T
4.[4:0]
Selector Field
2002/04/09
Description
1: Next Page enabled.
0: Next Page disabled. (Permanently: 0)
Permanently: 0
1: Advertises that RTL8305SB has detected a remote fault.
0: No remote fault detected.
1: Advertises that RTL8305SB has flow control capability.
0: Without flow control capability.
Technology not supported. (Permanently =0)
1: 100Base-TX full duplex capable.
0: Not 100Base-TX full duplex capable.
1: 100Base-TX half duplex capable.
0: Not 100Base-TX half duplex capable.
1: 10Base-TX full duplex capable.
0: Not 10Base-TX full duplex capable.
1: 10Base-TX half duplex capable.
0: Not 10Base-TX half duplex capable.
[00001]=IEEE802.3
23
Mode
RO
RO
RW
RO
RW
Default
0
0
0
0
From pin
RO
RW
0
From pin
RW
From pin
RW
From pin
RW
1
RW
00001
Rev.1.0
RTL8305SB
6.1.4 Register5: Auto-Negotiation Link Partner Ability Register
Reg.bit
5.15
Name
Next Page
5.14
Acknowledge
5.13
Remote Fault
5.[12:11]
5.10
Reserved
Pause
5.9
100Base-T4
5.8
100Base-TX-FD
Description
1: Link partner desires Next Page transfer.
0: Link partner does not desire Next Page transfer.
1: Link Partner acknowledges reception of FLP words.
0: Not acknowledged by Link Partner.
1: Remote Fault indicated by Link Partner.
0: No remote fault indicated by Link Partner.
Mode
RO
Default
0
RO
0
RO
0
RO
1: Flow control supported by Link Partner.
RW
0: No flow control supported by Link Partner.
Note: this bit is read only when Reg0.12=1. This bit is
read/write when Reg0.12=0 for future use.
1: 100Base-T4 supported by Link Partner.
RO
0: 100Base-T4 not supported by Link Partner.
1: 100Base-TX full duplex supported by Link Partner.
RO
0: 100Base-TX full duplex not supported by Link Partner.
0
0
0
0
For 100FX mode, this bit is set when Reg.0.8=1 or **Full =1
after link established.
5.7
100Base-TX
When Nway disabled TX mode, this bit is set when
Reg.0.13=1,and Reg.0.8=1 after link established.
1: 100Base-TX half duplex supported by Link Partner.
RO
0: 100Base-TX half duplex not supported by Link Partner.
0
For 100FX mode, this bit is set when Reg.0.8=0 or **Full = 0
after link established.
5.6
10Base-T-FD
5.5
10Base-T
5.[4:0]
Selector Field
When Nway disabled, this bit is set when Reg.0.13=1,and
Reg.0.8=0 after link established.
1: 10Base-TX full duplex supported by Link Partner.
0: 10Base-TX full duplex not supported by Link Partner.
RO
0
When Nway disabled, this bit is set when Reg.0.13=0,and
Reg.0.8=1 after link established.
1: 10Base-TX half duplex supported by Link Partner.
RO
0: 10Base-TX half duplex not supported by Link Partner.
When Nway disabled, this bit is set when Reg.0.13=0,and
0
Reg.0.8=0. after link established
[00001]=IEEE802.3
RO
00001
6.1.5 Register6: Auto-Negotiation Expansion Register
Reg.bit
6.[15:5]
6.4
6.3
6.2
6.1
6.0
Name
Reserved
Parallel Detection
Fault
Link Partner Next
Page Able
Local Next Page
Able
Page Received
Link Partner AutoNegotiation Able
Description
1: A fault has been detected via the Parallel Detection function.
0: A fault has not been detected via the Parallel Detection function.
1: Link Partner is Next Page able.
0: Link Partner is not Next Page able. (permanently=0)
1: RTL8305SB is Next Page able.
0: RTL8305SB is not Next Page able.
1: A New Page has been received.
0: A New Page has not been received.
If Nway is enabled, this bit means:
1: Link Partner is Auto-Negotiation able.
0: Link Partner is not Auto-Negotiation able.
Mode
RO
RO
Default
0
0
RO
0
RO
0
RO
0
RO
0 (Nway)
or
1 (Force)
In 100FX or Nway disabled, this bit always =1.
2002/04/09
24
Rev.1.0
RTL8305SB
6.2 PHY0: EEPROM Register0
6.2.1 Register16: EEPROM Byte0 and 1 Register
Reg.bit
16.15
16.14
Name
Internal
DisLoop
16.13
16.12
16.11
Internal
Internal
EnP4LED
Description
Disable Loop Detection Function.
1: Disable Loop Detection function.
0: Enable Loop Detection function.
Mode
RW
RW
Default
1
1
RW
RW
RW
1
1
1
RO
RO
RO
RW
RW
RW
RW
RW
RW
RW
1: EEPROM does not exist. (pin EnEEPROM=0. Or pin RO
EnEEPROM=1 but no EEPROM)
0: EEPROM exist.(pin EnEEPROM=1 and have EEPROM)
1
1
1
1
1
1
1
1
1
1
Enable Port4 LED.
1: Drive LED pins of port4.
0: Do not drive LED pins of port4 for special application.
In UTP applications, this bit should be 1 to drive LEDs of port
4. This bit is reserved for original RTL8305S users only, and
not used for general applications.
16.10
16.9
16.8
16.7
16.6
16.5
16.4
16.3
16.2
16.1
16.0
Reserved
Reserved
Reserved
Internal
Internal
Internal
Internal
Internal
Internal
Internal
NoEEPROM
6.2.2 Register17: EEPROM Byte2 and 3 Register
Reg.bit
17.15~
17.10
17.9
17.8
17.7~ 17.4
17.3~ 17.0
Name
Reserved
Description
Mode
RO
Internal
Internal
Reserved
Internal
Internal Use Only: Should be 1.
Internal Use Only: Should be 1.
RW
RW
RO
RW
Internal Use Only: Should be 0000.
Default
1
1
1
1111
0000
6.2.3 Register18~20: EEPROM EthernetID Register
For Bytes 4, 5, 6, 7, 8, and 9
Reg.bit
18
Name
EthernetID
Description
Device Ethernet MAC ID: Byte 4, 5 of EEPROM
Mode
RW
19
EthernetID
Device Ethernet MAC ID: Byte 6, 7 of EEPROM
RW
20
EthernetID
Device Ethernet MAC ID: Byte 8, 9 of EEPROM
RW
2002/04/09
25
Default
[7:0]=52
[15:8]=54
[7:0]=4c
[15:8]=83
[7:0]= 05
[15:8]= b0
Rev.1.0
RTL8305SB
6.2.4 Register21: EEPROM Byte10 and 11 Register
Reg.bit
Name
21.15
Reserved
21.14~21.12 P3VLANIndex[2]
P3VLANIndex[1]
P3VLANIndex[0]
21.11
Reserved
21.10~21.8 P2VLANIndex[2]
P2VLANIndex[1]
P2VLANIndex[0]
21.7
Reserved
21.6~21.4 P1VLANIndex[2]
P1VLANIndex[1]
P1VLANIndex[0]
21.3
Reserved
21.2~ 21.0 P0VLANIndex[2]
P0VLANIndex[1]
P0VLANIndex[0]
Description
Port 3 VLAN Index:
P3VLANIndex[2:0]=0b011 means port 3 use the forth VLAN
(VLAN D).
Mode
RO
RW
Default
1
011
RO
RW
1
010
RO
RW
Port 1 VLAN Index:
P1VLANIndex[2:0]=0b001 means port 1 use the second
VLAN (VLAN B).
RO
RW
Port 0 VLAN Index:
P0VLANIndex[2:0] are use to assign the VLAN of port 0. For
example, P0VLANIndex[2:0]=0b000 means port 0 use the first
VLAN (VLAN A).
1
001
Port 2 VLAN Index:
P2VLANIndex[2:0]=0b010 means port 2 use the third VLAN
(VLAN C).
P0VLANIndex[0] is bit0,
P0VLANIndex[2] is bit2.
P0VLANIndex[1]
is
1
000
bit1,
6.2.5 Register22: EEPROM Byte12 and 13 Register
Reg.bit
22.15
22.14
Name
P3IRTag[1]
P3IRTag[0]
22.13
22.12
P2IRTag[1]
P2IRTag[0]
22.11
22.10
P1IRTag[1]
P1IRTag[0]
22.9
22.8
P0IRTag[1]
P0IRTag[0]
22.7
22.6
P4IRTag[1]
P4IRTag[0]
22.5~11.3 Reserved
22.2~ 22.0 P4VLANIndex[2]
P4VLANIndex[1]
P4VLANIndex[0]
2002/04/09
Description
Insert/Remove Priority Tag of Port3.
11: Do not insert/remove Tag from Output High and Low Queue of Port3
10: Insert Tag from Output High and Low Queue of Port3
01: Insert Tag from Output High Queue only of Port3
00: Remove Tag from Output High and Low Queue of Port3
Insert/Remove Priority Tag of Port2.
11: Do not insert/remove Tag from Output High and Low Queue of Port2
10: Insert Tag from Output High and Low Queue of Port2
01: Insert Tag from Output High Queue only of Port2
00: Remove Tag from Output High and Low Queue of Port2
Insert/Remove Priority Tag of Port1.
11: Do not insert/remove Tag from Output High and Low Queue of Port1
10: Insert Tag from Output High and Low Queue of Port1
01: Insert Tag from Output High Queue only of Port1
00: Remove Tag from Output High and Low Queue of Port1
Insert/Remove Priority Tag of Port0.
11: Do not insert/remove Tag from Output High and Low Queue of Port0
10: Insert Tag from Output High and Low Queue of Port0
01: Insert Tag from Output High Queue only of Port0
00: Remove Tag from Output High and Low Queue of Port0
Insert/Remove Priority Tag of Port4.
11: Do not insert/remove Tag from Output High and Low Queue of Port4
10: Insert Tag from Output High and Low Queue of Port4
01: Insert Tag from Output High Queue only of Port4
00: Remove Tag from Output High and Low Queue of Port4
Mode
RW
Default
11
RW
11
RW
11
RW
11
RW
11
RO
RW
Port 4 VLAN Index.
P4VLANIndex[2:0]=0b100 means port 4 use the fifth VLAN
(VLAN E).
1
100
26
Rev.1.0
RTL8305SB
6.3 PHY1: EEPROM Register1
6.3.1 Register16~23: EEPROM (Byte 14~29) Register
Reg.bit
Name
16
Internal
17
Internal
18
Internal
19
Internal
20
Internal
21
Internal
22
Internal
23
Internal
Note: There is no default value.
Description
Internal use only
Internal use only
Internal use only
Internal use only
Internal use only
Internal use only
Internal use only
Internal use only
Mode
RW
RW
RW
RW
RW
RW
RW
RW
Default
Mode
RO
RW
Default
1111
6.3.2 Register24~31: EEPROM VLAN (Byte 30~44) Register
Reg.bit
Name
24.15~24.12 Reserved
24.11~24.0 VIDA[11:0]
Description
VLAN Identifier of VLAN A:
Reg24.11=VIDA[11], Reg24.0=VIDA[0].
There is no default value.
25.7~25.5
25.4~25.0
Reserved
MemberA[4:0]
26.7~26.4
26.3~26.0
25.15~25.8
26.15~26.11
26.12~26.8
Reserved
VIDB[11:0]
Member Set of VLAN A:
MemberA[4:0] determines the VLAN member of VLAN A.
For example, MemberA[4:0]=10001 means port4 and port0 are
the members of VLAN A. MemberA[4:0]=10010 means
port4 and port1 are the members of VLAN A.
RO
RW
111
10001
RO
RW
1111
MemberA[4:0]=11111 means all ports are members of VLAN A.
Reserved
MemberB[4:0]
27.15~27.12 Reserved
27.11~27.0 VIDC[11:0]
28.7~28.5
28.4~28.0
Reserved
MemberC[4:0]
29.7~29.4
29.3~29.0
28.15~28.8
29.15~29.13
29.12~29.8
Reserved
VIDD[11:0]
Reserved
MemberD[4:0]
30.15~30.12 Reserved
30.11~30.0 VIDE[11:0]
31.15~31.5 Reserved
31.4~31.0 MemberE[4:0]
2002/04/09
VLAN Identifier of VLAN B:
There is no default value.
RO
RW
Member Set of VLAN B:
MemberB[4:0]=10010 means port4 and port1 are members of
VLAN B.
RO
RW
VLAN Identifier of VLAN C:
There is no default value.
RO
RW
Member Set of VLAN C:
MemberC[4:0]=10100 means port4 and port2 are members of
VLAN C.
RO
RW
VLAN Identifier of VLAN D:
There is no default value.
RO
RW
Member Set of VLAN D:
MemberD[4:0]=11000 means port4 and port3 are members of
VLAN D.
RO
RW
VLAN Identifier of VLAN E:
There is no default value.
RO
RW
Member Set of VLAN E:
MemberE[4:0]=11111 means all ports are the members of
VLAN E.
27
111
10010
1111
111
10100
1111
111
11000
1111
11111111111
11111
Rev.1.0
RTL8305SB
6.4 PHY2: Pin & EEPROM Register
6.4.1 Register16: Pin Register
The RTL8305SB will load the value from pins upon reset, but can be updated via SMI after reset. This register needs a soft reset.
Reg.bit
Name
Description
Mode
Default
16.15
Internal use only
RW
Internal
1
16.14
Internal use only
RW
Internal
1
16.13
Internal use only
RW
Internal
1
16.12
Internal use only
RW
Internal
1
16.11
Internal use only
RW
Reserved
1
16.10
Internal use only
RW
Reserved
1
Weighted Round Robin Ratio of Priority Queue:
16.9
RW
Qweight[1]
11
16.8
The frame service rate of High-pri queue: Low-pri queue
Qweight[0]
11: 16:1
10: Always high priority queue first
01: 8:1
00: 4:1
16.7
DisFCAutoOff
Pin Register.
Disable Auto Turn Off Function of Flow Control Ability:
1: Disable
0: Enable
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
Enable Auto turn off low priority queue's flow control ability
1~2 sec whenever the port received a high priority frame. The
flow control ability will re-enabled when there is not received
and high priority frame during 1~2 sec.
16.6
DisDSPri
16.5
DisTagPri
16.4
DisPortPri[4]
16.3
DisPortPri[3]
16.2
DisPortPri[2]
16.1
DisPortPri[1]
16.0
DisPortPri[0]
2002/04/09
Pin Register.
Disable Differentiated Service Priority:
1: Disable DS priority
0: Enable DS priority
Pin Register.
Disable 802.1p VLAN Tag Priority Based QoS Function:
1: Disable
0: Enable
Pin Register.
Disable Port Based Priority QoS Function for Port4:
DisPortPri[4]:
1: Disable port 4 priority
0: Enable port 4 priority
Disable Port Based Priority QoS Function for Port3:
DisPortPri[3]:
1: Disable port 3 priority
0: Enable port 3 priority
Disable Port Based Priority QoS Function for Port2:
DisPortPri[2]:
1: Disable port 2 priority
0: Enable port 2 priority
Disable Port Based Priority QoS Function for Port1:
DisPortPri[1]:
1: Disable port 1 priority
0: Enable port 1 priority
Disable Port Based Priority QoS Function for Port0:
DisPortPri[0]:
1: Disable port 0 priority
0: Enable port 0 priority
Pin Register.
28
Rev.1.0
RTL8305SB
6.4.2 Register17: Pin & EEPROM Register for VLAN
Reg.bit
Name
17.15~17.6 Reserved
17.5
DisVLAN
17.4
DisTagAware
17.3
DisMemFilter
17.2
DisTagAdmitCtrl
17.1
DisLeaky
17.0
DisARP
Description
Disable VLAN:
1: Disable VLAN
0: Enable VLAN
Disable Tag Aware:
1: Disable the 802.1Q tagged-VID Aware function. The
RTL8305SB will not check the tagged VID of received frame to
do the VLAN classification. The RTL8305SB will always use
Port Based VLAN mapping.
0: Enable the Member Set Filtering function of VLAN Ingress
Rule. The RTL8305SB will check the tagged VID of received
frame to do the VLAN classification. The RTL8305SB will use
tagged-VID VLAN mapping for tagged frame and will use Port
Based VLAN mapping for untagged and priority-tagged frame.
Disable Member Set Filtering:
1: Disable the Member Set Filtering function of VLAN
Ingress Rule. The RTL8305SB will not discard any frames
associated with a VLAN for which that port is not in the
member set.
0: Enable the Member Set Filtering function of VLAN Ingress
Rule. The RTL8305SB will discard any frames associated with
a VLAN for which that port is not in the member set.
Disable Tag Admit Control: Acceptable Frame Type:
1: Disable Tag Admit Control: Acceptable Frame Type is
“Admit All”. The RTL8305SB will receive all frames.
0: Enable Tag Admit Control: Acceptable Frame Type is
“Admit All Tagged”. The RTL8305SB will receive only the
VLAN-tagged frame and drop all other untagged frames and
priority tagged (VID=0) frame.
Disable Leaky VLAN:
1: Disable to forward unicast frames to other VLAN.
0: Enable to forward unicast frames to other VLAN.
Mode
RW
RW
Default
1111 1111 11
1
RW
1
RW
1
RW
1
RW
1
Broadcast and multicast frames adhere to the VLAN
configuration.
RW
Disable ARP Broadcast to all VLAN:
1: Disable to broadcast the ARP broadcast packet to all
VLANs.
0: Enable to broadcast the ARP broadcast packet to all
VLANs.
1
ARP broadcast frame: DID is all F.
2002/04/09
29
Rev.1.0
RTL8305SB
6.5 PHY3: Port Control Register
6.5.1 Register16: Port Control Register
This register does not need a soft reset.
Reg.bit
Name
Description
16.15
SoftReset
Soft Reset:
1: Soft reset. This bit is self-clearing.
16.14~16.10 Reserved
16.9
DisP4LoopBack
Disable Port4 Loopback:
1: Disable port4 loopback function for normal application
0: Enable port4 loopback function for diagnostic application
16.8
DisP3LoopBack
Disable Port3 Loopback:
1: Disable port3 loopback function for normal application
0: Enable port3 loopback function for diagnostic application
16.7
DisP2LoopBack
Disable Port2 Loopback:
1: Disable port2 loopback function for normal application
0: Enable port2 loopback function for diagnostic application
16.6
DisP1LoopBack
Disable Port1 Loopback:
1: Disable port1 loopback function for normal application
0: Enable port1 loopback function for diagnostic application
16.5
DisP0LoopBack
Disable Port0 Loopback:
1: Disable port0 loopback function for normal application
0: Enable port0 loopback function for diagnostic application
16.4
EnPort4
Enable Link of Port4:
1: Enable Port4’s PHY (UTP or FX) to provide the Link status
to MAC for normal operation
0: Disable Port4’s PHY (UTP or FX) to provide the Link
status to MAC. This port is linked fail for MAC, but PHY still
work normally.
16.3
EnPort3
16.2
EnPort2
16.1
EnPort1
16.0
EnPort0
2002/04/09
The link status of MII MAC/MII PHY/SNI PHY is determined
by P4LNKSTA pin.
Enable Link of Port3:
1: Enable Port3’s PHY (UTP or FX) to provide the Link status
to MAC for normal operation.
0: Disable Port3’s PHY (UTP or FX) to provide the Link
status to MAC. This port is linked fail for MAC, but PHY still
work normally.
Enable Link of Port2:
1: Enable Port2’s PHY (UTP or FX) to provide the Link status
to MAC for normal operation.
0: Disable Port2’s PHY (UTP or FX) to provide the Link
status to MAC. This port is linked fail for MAC, but PHY still
work normally.
Enable Link of Port1:
1: Enable Port1’s PHY (UTP or FX) to provide the Link status
to MAC for normal operation.
0: Disable Port1’s PHY (UTP or FX) to provide the Link
status to MAC. This port is linked fail for MAC, but PHY still
work normally.
Enable Link of Port0:
1: Enable Port0’s PHY (UTP or FX) to provide the Link status
to MAC for normal operation.
0: Disable Port0’s PHY (UTP or FX) to provide the Link
status to MAC. This port is linked fail for MAC, but PHY still
work normally.
30
Mode
RW/SC
Default
0
RO
RW
1
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
Rev.1.0
RTL8305SB
6.5.2 Register17: EEPROM (Byte 46) Register
Reg.bit
17.15~17.7
17.6
17.5~17.3
17.2~17.0
Name
Reserved
Internal
Internal
Internal
Description
Internal use only
Internal use only
Internal use only
Mode
RO
RW
RW
RW
Default
1111 1111 1
1
Mode
RW
RW
RW
Default
6.5.3 Register18~20: EEPROM (Byte 47~52) Register
Reg.bit
18
19
20
2002/04/09
Name
Internal
Internal
Internal
Description
Internal use only
Internal use only
Internal use only
31
Rev.1.0
RTL8305SB
7. Functional Description
7.1 Switch Core Functional Overview
7.1.1 Application
The RTL8305SB is a 5 port Fast Ethernet switch controller, which integrates embedded memory, five MAC, and five physical
layer transceivers for 10Base-T and 100Base-TX into a single chip. All ports also support 100Base-FX, which shares pins with
UTP (TX+-/RX+-) and needs no SD+- pins (this is a Realtek patent technology).
The five ports are separated into 3 groups (GroupX/GourpY/Port4) for flexible port configuration using strapping pins upon
reset. The SetGroup pin is used to select the port numbers for GroupX and GroupY (SetGroup=1: GroupX=Port0;
GroupY=Ports 1, 2, and 3. SetGroup=0: GroupX=Ports 0 and 1; GroupY=Ports 2 and 3). The GxMode/GyMode/P4Mode[1:0]
pins are used to select the operation mode. (UTP / FX for GroupX and GroupY. UTP / FX / PHY mode MII / PHY mode SNI /
MAC mode MII for Port4)
Upon reset: defined as a short time after at the end of a hardware reset. After reset: defined as the time after the specified
"Upon Reset" time.
7.1.2 Port4
Operation mode of port4: Each port has two parts: MAC and PHY. In the UTP and FX mode, Port4 uses both the MAC and
internal PHY parts like the other ports. In the other mode, Port4 uses only the MAC part, which provides an external interface
to connect to the external MAC or PHY. Two pins are used for those operation mode configurations: P4MODE[1:0].
The fifth port (port 4) supports an external MAC interface which can be set to PHY mode MII, PHY mode SNI, or MAC mode
MII to work with an external MAC of a routing engine, PHY of a HomePNA or other physical layer transceiver.
If the MAC part of Port4 connects with an external MAC, such as processor for a router application, it should act as a PHY.
This is PHY mode MII or PHY mode SNI. In PHY mode MII or PHY mode SNI, Port4 uses the MAC part only, and provides
an external MAC interface to connect MAC of external device. In order to connect both MACs, the MII of the switch MAC
should be reversed into PHY mode.
If the MAC part of Port4 connects with an external PHY, such as a PHY for a HomePNA application, Port4 should act as MAC.
This is MAC mode MII. In MAC mode MII, Port4 uses its MAC to connect external PHY and ignores the internal PHY part.
2002/04/09
32
Rev.1.0
RTL8305SB
General System Application
1. General switch application
2. Router application:
3. HomePNA application
4. Other PHY application
RTL8305SB
RTL8305SB
5x Transformer
5x Fiber Interface
SetGroup=1,
GxMode=1,GyMode=1,
P4Mode[1:0]=11
4x Transformer
ADSL/
Cable
SetGroup=1,
Modem
(PHY mode MII): GxMode=1,
GyMode=1, P4Mode[1:0]=01
Or
(PHY mode SNI): GxMode=1,
GyMode=1, P4Mode[1:0]=00
2.1: Router application:
4 port 10/100 UTP
1 port PHY mode MII or SNI (Port4)
SetGroup=1,
GxMode=1,GyMode=1,
P4Mode[1:0]=11
2.2: Router application:
1 port 100 FX (Port0)
3 port 10/100 UTP (Port1,2,3)
1 port PHY mode MII or SNI (Port4)
1x
Fiber
Interface
SetGroup=1,
GxMode=1,GyMode=1,
P4Mode[1:0]=11
4.1: Other PHY application:
4 port 10/100 UTP
1 port MAC mode MII (Port4)
1x
Fiber
Interface
3x
Transformer
ADSL/
Cable
2x
Fiber
Interface
HomePNA
2x
Transformer
HomePNA
2.4: Router application:
1 port 10/100 UTP (Port0)
3 port 100 FX (Port1,2,3)
1 port PHY mode MII or SNI (Port4)
1x
Transformer
2x
Transformer
RTL8305SB
Other
PHY
SetGroup=0,
GxMode=0,GyMode=1,
P4Mode[1:0]=11
SetGroup=1,
GxMode=0,GyMode=1,
P4Mode[1:0]=11
4.2: Other PHY application:
1 port 100 FX (Port0)
3 port 10/100 UTP (Port1,2,3)
1 port MAC mode MII (Port4)
4.3: Other PHY application:
2 port 100 FX (Port0,1)
2 port 10/100 UTP (Port2,3)
1 port MAC mode MII (Port4)
33
HomePNA
3.4: HomePNA application:
1 port 10/100 UTP (Port0)
3 port 100 FX (Port1,2,3)
1 port MAC mode MII (Port4)
RTL8305SB
2x
Fiber
3x
Fiber
Interface
SetGroup=1,
GxMode=1,GyMode=0,
P4Mode[1:0]=11
3.3: HomePNA application:
2 port 100 FX (Port0,1)
2 port 10/100 UTP (Port2,3)
1 port MAC mode MII (Port4)
Interface
ADSL/
Cable
RTL8305SB
SetGroup=0,
GxMode=0,GyMode=1,
P4Mode[1:0]=11
Other
PHY
3x
Fiber
Interface
SetGroup=1,
Modem
(PHY mode MII): GxMode=1,
GyMode=0, P4Mode[1:0]=01
Or
(PHY mode SNI): GxMode=1,
GyMode=0, P4Mode[1:0]=00
RTL8305SB
RTL8305SB
Other
PHY
Router
1x
Transformer
2.3: Router application:
2 port 100 FX (Port0, 1)
2 port 10/100 UTP (Port2,3)
1 port PHY mode MII or SNI (Port4)
3.2: HomePNA application:
1 port 100 FX (Port0)
3 port 10/100 UTP (Port1,2,3)
1 port MAC mode MII (Port4)
RTL8305SB
2002/04/09
3x
Transformer
2x
Transformer
SetGroup=0,
Modem
(PHY mode MII): GxMode=0,
GyMode=1, P4Mode[1:0]=01
Or
(PHY mode SNI): GxMode=0,
GyMode=1, P4Mode[1:0]=00
SetGroup=1,
GxMode=0,GyMode=1,
P4Mode[1:0]=11
3.1: HomePNA application:
4 port 10/100 UTP
1 port MAC mode MII (Port4)
4x Transformer
ADSL/
Cable
RTL8305SB
HomePNA
RTL8305SB
Router
2x
Fiber
Interface
SetGroup=1,
Modem
(PHY mode MII): GxMode=0,
GyMode=1, P4Mode[1:0]=01
Or
(PHY mode SNI): GxMode=0,
GyMode=1, P4Mode[1:0]=00
RTL8305SB
4x Transformer
3x
Transformer
1.3 General switch application:
1 port 100 FX (Port0 or 4)
4 port 10/100 UTP
RTL8305SB
Router
1x
Fiber
Interface
4x Transformer
SetGroup=1,
(Port0=100FX): GxMode=0,
GyMode=1, P4Mode[1:0]=11
Or
(Port4=100FX): GxMode=1,
GyMode=1, P4Mode[1:0]=10
1.2 General switch application:
5 port 100 FX
RTL8305SB
Router
1x Fiber
Interface
SetGroup=1,
GxMode=0,GyMode=0,
P4Mode[1:0]=10
1.1 General switch application:
5 port 10/100 UTP
RTL8305SB
RTL8305SB
1x
Transformer
3x
Fiber
Interface
Other
PHY
SetGroup=1,
GxMode=1,GyMode=0,
P4Mode[1:0]=11
4.4: Other PHY application:
1 port 10/100 UTP (Port0)
3 port 100 FX (Port1,2,3)
1 port MAC mode MII (Port4)
Rev.1.0
RTL8305SB
External MAC interface: In order to act as PHY. When port4 is in PHY mode, some pins of the external MAC interface
should be changed. For example, TXC are input pins for MAC but output pins for PHY. So the pin MTXC/PRXC is input for
MAC mode and output for PHY mode. Please refer to below diagram to check the relationship between RTL8305SB and the
external device. Hint: Connect input of RTL8305SB to output of external device. RTL8305SB has no RXER, TXER, and CRS
pins for MII signaling. Because RTL8305SB does not support pin CRS, it is necessary to connect the MTXEN/PRXDV
(output) of PHY mode to both CRS and RXDV (input) of the external device.
Note: In order to differentiate between MAC and PHY mode, the RTL8305SB change the pin name of PHY mode. For example:
RTL8305SB=MRXD[0]/PTXD[0], RTL8305S=MRXD[0]/MTXD[0].
Port4 status pins: When P4MODE[1:0]=11, Port4 can be either UTP or MAC mode MII. Port4 will automatically detect the
link status of UTP from internal PHY and link status MAC mode MII from both TXC of external PHY and P4LNKSTA#. If
both UTP and MII port are linked OK, UTP has higher priority and RTL8305SB will ignore the signal of MII port.
In UTP and FX mode, the internal PHY will provide the port status (Link/Speed/Duplex/Full Flow Control ability) in real time.
In order to provide the initial configuration of Port4’s PHY (UTP or FX mode), four pins (P4ANEG, P4Full, P4Spd100,
P4EnFC) are used to strap upon reset. Upon reset: defined as a short time after at the end of hardware reset. However, three of
these pins are also used for Port4’s MAC (the other three modes) in real time after reset (P4Spd100 -> P4SpdSta, P4Full ->
P4DupSta, P4EnFC -> P4FLCTRL). After reset: defined as the time after upon reset. Note: These 3 pin are changed as high
active in order to provide dual function. For example: RTL8305SB=P4SpdSta/P4Spd100, RTL8305SB=P4SpdSta#.
In the other three modes, four pins (P4LNKSTA#, P4SpdSta, P4DupSta, P4FLCTRL) are necessary in order to provides the
port status to Port4’s MAC in real time. That means that the external MAC or PHY should be forced to the same port status as
Port4’s MAC.
Related pins: When port4 is in UTP or FX mode, the LEDs of port4 are used to displays PHY status. When port4 is in other
mode, the LEDs of port4 are used to displays MAC status.
Four parallel LEDs corresponding to port 4 can be three-stated (disable LED functions) for MII port application by setting
ENP4LED in EEPROM as 0. In UTP application, this bit should be 1 to drive LEDs of port 4.
Pin SEL_MIIMAC# can be used to indicate MII MAC port active after reset for the sake of UTP/MII auto-detection.
One 25MHz clock output (pin CK25MOUT) can be used as a clock source of the underlying HomePNA/other PHY physical
devices. Note: the output voltage is 2.5V for RTL8305SB but is 3.3V for RTL8305S.
PHY mode MII/PHY mode SNI: In routing application, RTL8305SB cooperates with a routing engine to communicate with
WAN (Wide Area Network) through MII/SNI. In such application, P4LNKSTA# =0 and P4MODE[1] is pulled low upon reset.
P4MODE[0] determines whether MII or SNI mode is selected.
In MII (nibble) mode (P4MODE[0]=1), P4SPDSTA=1 results in MII operating at 100Mbps with MTXC and MRXC runs at
25MHz; however, P4SPDSTA=0 leads to MII operating at 10Mbps with MTXC and MRXC runs at 2.5MHz.
In SNI (serial) mode (P4MODE[0]=0), P4SPDSTA takes no effect and should be pull-down. SNI mode operates at 10Mbps
only, with MTXC and MRXC running at 10MHz. In SNI mode, RTL8305SB does not loopback RXDV signal as response to
TXEN and does not support heart-beat function. (asserting COL signal for each complete of TXEN signal).
2002/04/09
34
Rev.1.0
RTL8305SB
RTL8305SB
x
Floating=High
Pull-down=Link
Note1
Note1
Note1
97 P4Mode[1]
98 P4Mode[0]
49 P4LnkSta#
47 P4SpdSta/P4Spd100
48 P4DupSta/P4Full
46 P4FlCtrl/P4EnFC
25M/2.5MHz
51 MTXC/PRXC
52 MTXEN/PRXDV
4
57-54 MTXD[3:0]/PRXD[3:0]
59 MRXC/PTXC
60 MRXDV/PTXEN
4
67~61 MRXD[3:0]/PTXD[3:0]
58 MCOL/PCOL
RXC
CRS
RXDV
RXD[3:0]
TXC
TXEN
TXD[3:0]
COL
Routing Engine
PHY mode MII
97 P4Mode[1]
98 P4Mode[0]
Pull-down=Link
Pull-Down
Pull-Down
Pull-Down
49 P4LnkSta#
47 P4SpdSta/P4Spd100
48 P4DupSta/P4Full
46 P4FlCtrl/P4EnFC
10MHz
51 MTXC/PRXC
52 MTXEN/PRXDV
1
54 MTXD[0]/PRXD[0]
59 MRXC/PTXC
60 MRXDV/PTXEN
1
61 MRXD[0]/PTXD[0]
58 MCOL/PCOL
Routing Engine
RXC
CRS
RXDV
RXD
TXC
TXEN
TXD
COL
PHY mode SNI
x
x
Floating=High
Floating=High
Pull-down=Link
Pull-Down
Pull-Down
Pull_Down
Used
97 P4Mode[1]
98 P4Mode[0]
49 P4LnkSta#
47 P4SpdSta/P4Spd100
48 P4DupSta/P4Full
46 P4FlCtrl/P4EnFC
59 MRXC/PTXC
60 MRXDV/PTXEN
67~61 MRXD[3:0]/PTXD[3:0]
51 MTXC/PRXC
52 MTXEN/PRXDV
57-54 MTXD[3:0]/ PRXD[3:0]
68 SelMiiMac#/DisDSPri
4
4
58 MCOL/PCOL
RXC
CRS
RXDV
RXD[3:0]
TXC
TXEN
TXD[3:0]
COL
HomePHY
MAC mode MII(HomePNA Application)
x
x
Floating=High
Floating=High
Pull-down=Link
Note1
Note1
Note1
Used
Other PHY
97 P4Mode[1]
98 P4Mode[0]
49 P4LnkSta#
47 P4SpdSta/P4Spd100
48 P4DupSta/P4Full
46 P4FlCtrl/P4EnFC
59 MRXC/PTXC
60 MRXDV/PTXEN
67~61 MRXD[3:0]/PTXD[3:0]
52 MTXEN/PRXDV
57-54 MTXD[3:0]/ PRXD[3:0]
68 SelMiiMac#/DisDSPri
4
51 MTXC/PRXC
58 MCOL/PCOL
4
RXC
CRS
RXDV
RXD[3:0]
TXC
TXEN
TXD[3:0]
COL
MAC mode MII(Other PHY Application)
Note1: Floating or Pull-down, depend on application
Note2: Pin 46,47, and 48 are high active for RTL8305SB, but are low active for RTL8305S.
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MAC mode MII: In HomePNA or other PHY applications, the RTL8305SB provides the MII interface to the underlying
HomePNA or other physical devices so as to communicate with other types of LAN media. In such applications, the
P4MODE[1:0] pins are floating upon reset and the RTL8305SB supports the UTP/MII auto-detection function. When both
UTP and MII are active (link on), the UTP port has a higher priority over MII port.
In HomePNA applications, P4SPDSTA must be pulled down since HomePNA is half-duplex only. P4DUPSTA should be
pulled down as well. P4LNKSTA# must be pulled down instead of being wired to the LINK LED pin of the HomePNA
because of the unstable link state of HomePNA, a characteristic based on the HomePNA 1.0 standard. Because the HomePNA
PHY physical layer is half duplex and can only detect the collision event during AID header interval (the time for transmit
Ethernet preamble), the back pressure flow control algorithm is not suitable for the HomePNA network. So the P4FLCTRL
pin should be pulled down.
For other PHY applications, P4SPDSTA, P4DUPSTA, and P4FLCTRL depend on application.
7.1.3 Port Status Configuration
The RTL8305SB supports flexible port status configuration for PHY by pin (GxANeg/GyANeg/P4ANeg,
GxSpd100/GySpd100/P4Spd100, and GxFull/GyFull/P4Full) on a group basis upon reset or by internal registers (Reg0.12,
Reg0.13, Reg0.8, and Reg4.5/4.6/4.7/4.8) via SMI on a per port basis after reset. Those pins are used to assign the initial value
of MII register 0 and 4 (PHY registers) upon reset. The registers can be updated via SMI on a per port basis after reset. For
example, the initial value of register 0.12 of port4 will be 0 when pin P4Aneg is 1 upon reset. Note: The RTL8305S only
supports UTP with Auto-Negotiation ability. Only one pin, NWAYHalf#, is supported for global configuration of all PHYs. And
does not support these registers for configuration via SMI.
All ports support 100Base-FX, which share pins with UTP (TX+-/RX+-) and need no SD+- pins (Realtek patent). The
100Base-FX can be forced into half or full duplex mode with optional flow control ability. In order to operate correctly, both sides
of the connection should set the same duplex and flow control ability. In 100Base-FX, only duplex and flow control ability can be
set via strapped pins upon reset or via SMI after reset. Note that 100Base-FX does not support Auto-Negotiation according to
IEEE 802.3u. Pins GxANeg/GyANeg/P4Aneg as well as GxSpd100/GySpd100/P4Spd100 are not used for 100Base-FX mode
and can be left floating while in 100Base-FX mode. For example: port4 will be forced into full duplex 100Base-FX with flow
control ability when P4Mode[1:0]=10, P4Full=1, P4EnFC=1 upon reset (regardless of P4Spd100 and P4ANeg).
When Auto-Negotiation ability is enabled in UTP mode, the RTL8305SB supports Auto-Negotiation and parallel detection for
10Base-T/100Base-TX to automatically determine line speed, duplex and flow control ability. The parallel detection process is
used when the other side does not support auto-negotiation. For example: port0 is UTP with all abilities (default for normal
switch application: GxMode=1, GxANeg=1, GxSpd100=1, GxFull=1, GxEnFC=1. The content of MII registers will be
Reg0.12=1, Reg4.5=1, Reg4.6=1, Reg4.7=1, Reg4.8=1, and Reg4.10=1.) If the other side is auto-negotiation, 10Full with
802.3x flow control ability, port0 will enter the auto-negotiation process. The result should be 10Full with 802.3x flow control
ability for both sides. If the other side is 10M without auto-negotiation, port0 will enter the parallel detection process. The
result should be 10Half without 802.3x flow control ability for port0.
Note: Each port can operate at 10Mbps or 100Mbps with full-duplex or half-duplex mode independently to others when
auto-negotiation process is on.
The port status for the PHY on a group basis can easily be set by pin configuration. For example, when group X is 100FX
(GxMode=0), group X can be set as force mode half duplex by setting pin GxFull to 0. Group Y can also be set as UTP mode
NWAY mode 10Full by setting pins GyMode=1, GyANeg=1, GySpd100=0, GyFull=1. Refer to the pin descriptions for details.
7.1.4 Enable Port
The RTL8305SB supports internal registers for individual ports for MAC to mask the current Link status from the PHY. For
example: If register EnPort0=0, MAC of port0 will ignore Link status from the PHY and treat this port as no-link.
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7.1.5 Flow Control
The RTL8305SB supports IEEE 802.3x full duplex flow control, Force mode Full duplex Flow Control, and optional half
duplex back pressure.
IEEE 802.3x full duplex flow control: For UTP with auto-negotiation ability (GxANeg/GyANeg/P4Aneg is 1), the pause
ability (Reg 4.10) of full duplex flow control is enabled by pin GxEnFC/GyEnFC/P4EnFC on a group basis upon reset or
internal registers via SMI in per port basis after reset. For UTP with auto-negotiation ability, the IEEE 802.3x flow control's
ability is auto-negotiated between the remote device and the RTL8305SB. If the result of the 802.3x pause ability
auto-negotiation is enabled (Reg 4.10=1 and Reg5.10=1), the full duplex 802.3x flow control function is enabled. Otherwise,
the full duplex 802.3x flow control function is disabled.
Force mode Full duplex Flow Control: For UTP without auto-negotiation ability (GxANeg/GyANeg/P4Aneg is 0) and
100Base-FX, the IEEE 802.3x flow control's ability can be forced to enabled at the RTL8305SB side by a pin
GxEnFC/GyEnFC/P4EnFC in group basis upon reset or internal registers (Reg5.10) via SMI in per port basis after reset. For
example, port 4 will be forced to 10Full UTP with forced mode full duplex flow control ability, regardless of the other side,
when P4Mode[1:0]=10, P4Aneg=0, P4Spd100=0, P4Full=1, P4EnFC=1. Port 0 will be forced to 100Full FX with forced
mode full duplex flow control ability, regarrdless of the other side when SetGroup=1, GxMode=0, GxFull=1, GxEnFC=1.
Regardless of IEEE 802.3x full duplex flow control or Force mode Full duplex Flow Control, when full duplex flow control is
enabled, the RTL8305SB will only recognize the 802.3x flow control PAUSE ON/OFF frames with DA="0180C2000001",
type="8808", OP-code="01", PAUSE Time = maximum to zero, and with good CRC.
If a PAUSE frame is received from any PAUSE flow control enabled port with DA=0180C2000001, the corresponding port of
the RTL8305SB will stop its packet transmission until the PAUSE timer times out or another PAUSE frame with zero PAUSE
time is received. The RTL8305SB will not forward any 802.3x PAUSE frames received from any port.
Half duplex back pressure: The RTL8305SB adopts optional half duplex back pressure design:
If pin EnDefer is 1, the RTL8305SB will send a preamble to defer the other station’s transmission when there is no packet to send.
Otherwise, if pin EnDefer is 0, the RTL8305SB will force a collision to the other station’s transmission when the buffer is full.
If pin 48pass1 is 0, the RTL8305SB will collide with JAM always (Continuous collision). Otherwise, if pin 48pass1 is 1, the
RTL8305SB will try to forward one packet successfully after 48 force collisions (48pass1), to avoid the connected repeater
being partitioned due to excessive collision.
NWAY (has Auto-Negotiation ability) mode: For UTP with auto-negotiation ability, pin GxEnFC/GyEnFC/P4EnFC is used
for Full duplex. But the result of auto-negotiation may be half duplex. So for UTP with auto-negotiation ability, the half
duplex back pressure flow control is controlled by the EnANEG_BKPRS pin strap upon hardware reset.
Force mode: For UTP without auto-negotiation ability and 100Base-FX, the operation mode can be forced as half duplex. So
the half duplex back pressure flow control can be forced enable at the RTL8305SB side by pin GxEnFC/GyEnFC/P4EnFC in
group basis upon reset.
Note: For the RTL8305SB, the name of the EnBkPrs pin on the RTL8305S is replaced by EnANeg_BkPrs.
Note: For the RTL8305SB, the function of the ENFCTRL on the RTL8305S is replaced by 3 pins: GxEnFC, GyEnFC, P4EnFC.
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7.1.6 Address Search, Learning and Aging
When a packet is received, the RTL8305SB will first use the least 10 bits of the destination MAC address to index the
1024-entry look-up table and at the same time will compare the destination MAC address with the contents of the 16-entry
CAM. If the indexed entry is valid or the CAM comparison is match, this received packet will be forwarded to the
corresponding destination port. Otherwise, the RTL8305SB will broadcast the packet. This is called ‘search’.
The RTL8305SB then extracts the least 10 bits of source MAC address to index the 1024-entry look-up table. If this indexed
entry is empty, it will record the source MAC address and update switching information. If this is an occupied entry with the
same switching information, it will update the entry with new information. This is called ‘learning’. If the indexed location has
been occupied by different MAC address (hash collision), the new source MAC address will be recorded into the 16-entry
CAM. The 16 entry CAM can reduce the address hash collision and will improve the switch network performance.
Address aging function is used to keep the contents of the address table correct in a dynamic network topology. The look-up
engine will update time stamp information of an entry whenever the corresponding source MAC address appears. An entry
will be invalid (aging out) if it’s time stamp information is not refreshed by the address learning process during the aging time
period. Aging time of the RTL8305SB is around 200 to 300 seconds.
7.1.7 Address Direct Mapping Mode
The RTL8305SB uses the least 10 bits of the MAC address to index the 1024-entry look-up table. For example: the index of
MAC address “12 34 56 78 90 ab” will be 0ab.
7.1.8 Half Duplex Operation
In half duplex mode, the CSMA/CD media access method is the means by which two or more stations share a common
transmission medium. To transmit, a station waits (defers) for a quiet period on the medium (that is, no other station is
transmitting) and then sends the intended message in bit-serial form. If, after initiating a transmission, the message collides
with that of another station, then each transmitting station intentionally transmits for an additional predefined period to ensure
propagation of the collision throughout the system. The station remains silent for a random amount of time (backoff) before
attempting to transmit again.
When a transmission attempt has terminated due to a collision, it is retried until it is successful. The scheduling of the
retransmissions is determined by a controlled randomization process called “truncated binary exponential backoff” At the end
of enforcing a collision (jamming), the switch delays before attempting to retransmit the frame. The delay is an integer
multiple of slotTime (512 bit times). The number of slot times to delay before the nth retransmission attempt is chosen as a
uniformly distributed random integer r in the range:
0 ≦ r<2k
where
k =min (n, backoffLimit), The 802.3 defines the backoffLimit as 10.
7.1.9 Inter-Frame Gap
The Inter-Frame Gap is 9.6µs for 10Mbps Ethernet and 960ns for 100Mbps Fast Ethernet.
7.1.10 Illegal Frame
Illegal frames such as CRC error packets, runt packets (length < 64 bytes) and oversize packets (length > maximum length)
will be discarded.
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7.2 Physical Layer Functional Overview
7.2.1 Auto-Negotiation for UTP
The RTL8305SB obtains the states of duplex, speed and flow control ability through the auto-negotiation mechanism defined
in IEEE802.3u specifications for each port in UTP mode. During auto-negotiation, each port advertises its ability to its link
partner and compares ability with those received from its link partner. By default, the RTL8305SB advertises full capabilities
(100Full, 100Half, 10Full, 10Half) together with flow control ability.
7.2.2 10Base-T Transmit Function
The output 10Base-T waveform is Manchester-encoded before it is driven into the network media. The internal filter shapes
the driven signals to reduce EMI emission, eliminating the need for an external filter.
7.2.3 10Base-T Receive Function
The Manchester decoder converts the incoming serial stream to NRZ data when the squelch circuit detects the signal level is
above squelch level.
7.2.4 Link Monitor
The 10Base-T link pulse detection circuit always monitors the RXIP/RXIN pins for the presence of valid link pulses.
Auto-polarity is implemented to correct the detected reverse polarity of RXIP/RXIN signal pairs.
7.2.5 100Base-TX Transmit Function
The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ/NRZI conversion,
and MLT3 encoding. The 5-bit serial data stream after 4B/5B coding is then scrambled as defined by the TP-PMD Stream
Cipher function to flatten the power spectrum energy such that EMI effects can be reduced significantly.
The scrambled seed is unique for each port based on PHY addresses. The bit stream after scrambler is driven into network
media in the form of MLT-3 signaling. The multi-level signaling technology moves the power spectrum energy from high
frequency to low frequency, which also benefits EMI emission.
7.2.6 100Base-TX Receive Function
The receive path includes a receiver composed of adaptive equalizer and DC restoration circuits to compensate for the
incoming distortion MLT-3 signal, MLT-3 to NRZI, NRZI to NRZ converter to convert analog signal to digital bit-stream , and
PLL circuit to clock data bit exactly with minimum bit error rate. De-scrambler, 5B/4B decoder and serial-to-parallel
conversion circuits are followed. Finally, the converted parallel data is fed into the MAC.
7.2.7 100Base-FX
All ports support 100Base-FX, which shares pins with UTP (TX+-/RX+-) and need no SD+- pins (Realtek patent). The
100Base-FX can be forced as half or full duplex with optional flow control ability. Hint: The 100Base-FX does not support
Auto-Negotiation according to IEEE 802.3u. In order to operate correctly, both sides of the connection should set the same
duplex and flow control ability. A scrambler is not needed in 100Base-FX. As compared to common 100Base-FX applications,
the RTL8305SB lacks of a pair of differential SD (signal detect) signals to achieve link monitoring function (Realtek patent),
which significantly reduces the pin count.
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7.2.8 100Base-FX Transmit Function
In 100Base-FX transmit, di-bits of TXD are processed as 100Base-TX except without scrambler before NRZI stage. Instead of
converting to MLT-3 signals as in 100Base-TX, serial data stream is driven out as NRZI PECL signals, which enter the fiber
transceiver in differential-pairs form. The fiber transceiver should be available working in a 3.3V environment. Refer to fiber
application section.
Parameter
PECL Input High Voltage
PECL Input Low Voltage
PECL Output High Voltage
PECL Output Low Voltage
Symbol
Min
Max
Vih
Vdd-1.16
Vdd-0.88
Vil
Vdd-1.81
Vdd-1.47
Voh
Vdd-1.02
Vol
Vdd-1.62
PECL DC characteristics
Unit
V
V
V
V
7.2.9 100Base-FX Receive Function
Signals are received through PECL receiver inputs from fiber transceiver, and directly passed to clock recovery circuit for
data/clock recovery. Scrambler/de-scrambler is bypassed in 100Base-FX.
7.2.10 100Base-FX Far-End-Fault-Indication (FEFI)
MII Reg.1.4 (Remote Fault) is the FEFI bit for ports when 100FX is enabled, which indicates that a FEFI has been detected.
FEFI is an alternative in-band signaling which is composed of 84 consecutive ‘1’ followed by one ‘0’. From the view of the
RTL8305SB, when this pattern has been detected three times, Reg.1.4 is set, which means the transmit path (Remote side’s
receive path) has problems. On the other hand, to send FEFI stream pattern, 1 condition need to be satisfied. The incoming
signal failed in causing link OK will force the RTL8305SB to start sending this pattern, which in turn causes the remote side
detecting Far-End-Fault. This means that the receive path has a problem from the view of the RTL8305SB. The FEFI
mechanism is used only in 100Base-FX.
7.2.11 Reduced Fiber Interface
The RTL8305SB ignores the underlying SD signal of the fiber transceiver to complete link detection and connection. This is
achieved by monitoring RD signals from the fiber transceiver and checking if any link integrity events are met. This
significantly reduces pin-count, especially for high-port PHY devices. This is a Realtek patent-pending technology and
available only with Realtek product solutions.
7.2.12 Power Saving Mode
The RTL8305SB implements power saving mode on per port base. A port automatically enters power saving mode 10 seconds
after the cable is disconnected from it. Once a port enters power saving mode, it transmits normal link pulses only on its
TXOP/TXON pins and continues to monitor the RXIP/RXIN pins to detect any incoming signals, which might be the
100Base-TX MLT-3 idle pattern, 10Base-T link pulses or Auto-Negotiation’s FLP (fast link pulses). After it detects any incoming
signals, it wakes up from the power saving mode and operates in the normal mode according to the result of connection.
7.2.13 Reg0.11 Power Down Mode
The RTL8305SB implements power down mode on a per port basis. Setting MII Reg.0.11 forces the corresponding port
of the RTL8305SB to enter power down mode, which disables all transmit/receive functions, except SMI (MDC/MDIO
management interface).
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7.2.14 Crossover Detection and Auto Correction
During the link setup phase, the RTL8305SB checks if it receives active signals on every port to determine if connection can
be established. In case the receiver data pin pair is connected to receiver pin pair of the peer device and vice versa, the
RTL8305SB will automatically change its configuration to swap receiver data pins with transmitter data pins. In other words,
the RTL8305SB can adapt automatically to a peer device's configuration. If a port is connected to a PC or NIC with MDI-X
interface with a crossover cable, the RTL8305SB will reconfigure the port to provide the MDI-X interface to ensure proper
connection. This will effectively replace the DIP switch commonly used for reconfiguring a port on a hub or switch.
By pulling-up EN_AUTOXOVER, the RTL8305SB can identify the type of connected cable to adjust its port as MDI or
MDIX. When switching to MDI mode, the RTL8305SB uses TXOP/N as transmit pairs; when switching to MDIX mode, the
RTL8305SB uses RXIP/N as transmit pairs. The same for receive pairs. This function is port-based implemented.
Pulling-down EN_AUTOXOVER will disable this function and the RTL8305SB operates in MDI mode, in which TXOP/N
represents transmit pairs and RXIP/N represents receive pairs.
According to the IEEE standard, the forced mode 100M ports with autoxover have link issues with NWAY (Auto-Negotiation)
ports. It is recommended to not to use autoxover for forced 100M.
7.2.15 Polarity Detection and Correction
For better noise immunity and lower interference to ambient devices, the Ethernet electrical signal on a twisted pair cable is
transmitted in differential forms. That is, the signal is transmitted on two wires for each direction with inverse polarities (+/-).
If wiring on the connector is faulty or a faulty transformer is used, the two inputs to a transceiver may carry signals with
opposite but incorrect polarities. As a direct consequence, the transceiver will not work properly.
When the RTL8305SB operates in 10Base-T mode, it automatically reverses the polarity of its two receiver input pins if it
detects that the polarities of the incoming signals on the pins is incorrect. However, this feature is unnecessary when the
RTL8305SB is operating in 100Base-TX mode.
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7.3 Advanced Functional Overview
7.3.1 Reset
The whole or part of the RTL8305SB is initialized depending on the reset type. There are several ways to reset RTL8305SB:
hardware reset for whole chip by pin RESET#, soft reset for all except PHY by register SoftReset, and PHY software reset for
each PHY by register reset.
Hardware Reset: pin RESET# = 0 (asserted at least 1ms) to 1. The RTL8305SB will reset the whole chip then get initial
value from pins and serial EEPROM.
Soft Reset: Write bit15 of Reg16 of PHY3 as 1. The RTL8305SB will reset all except PHY and will not load EEPROM and
Pin Registers with serial EEPROM and Pins. The SoftReset, EEPROM and Pin registers are designed to provide a convenient
way for users who want to use SMI to change the configuration. After changing the EEPROM or Pin registers via SMI, the
external device has to perform a soft reset in order to update the configuration.
PHY software reset: Write bit15 of Reg0 of some PHY as 1. The RTL8305SB will then reset this PHY.
Hardware Reset
Soft Reset : After loading EEPROM completely, user can access
EEPROM/Pin registers via SMI. And have to do Soft Reset to reset all
strap pin upon reset
load EEPROM upon reset
except PHY to update pin/EEPROM configuration.
Some setting values for operation modes are latched from those corresponding mode pins at the end of hardware reset. Upon
reset is defined as a short time after at the end of a hardware reset. Then other advanced configuration parameters may be
latched from serial EEPROM if pin EnEEPROM=1.
7.3.2 Setup and Configuration
The RTL8305SB can be configured easily and flexibly by hardware pins upon reset, optional serial EEPROM upon reset, and
internal registers (including PHY registers for each port and MAC register for global) via SMI (serial management interface:
MDC/MDIO, also known as MII Management Interface). There are three ways to configure: 1) Only hardware pins for normal
switch application; 2) Hardware pins and serial EEPROM for advanced switch application; 3) Hardware pins and internal
registers via SMI for application with processor.
Four types of pins, which all have internal pull-high resistors, are used for configuration: 1) Input pins used for strapping only
upon reset and are of no use after reset; 2) Input pins (P4DUPSTA/P4FULL, P4SPDSTA/P4SPD100, P4FLCTRL/P4EnFC)
used for strapping upon reset and used as input pins after reset. For example, pin P4DUPSTA/P4FULL is used as P4FULL
upon reset for PHY of Port 4 UTP/FX mode and used as P4DUPSTA for MAC of other mode after reset; 3) Input/Output pins
(MTXD[3:2]/PRXD[3:2]/P4IRTag[1:0], MTXD[1:0]/PRXD[1:0]/LEDMode[1:0]) used for strapping upon reset and used as
output pins after reset; 4) Input/Output pins (all LEDs) used for strapping upon reset and used as LED indicator pins after reset.
The LED statuses are represented as active-low or high depending on input strapping, except Bi-color Link/Act in Bi-color
LED mode, whose polarity depends on Spd status.
The Pins with default value=1 are internal pull-high and use I/O pad. So they can be left floating to choose input value as high
but should not be connected to GND without a pull-down resistor.
The serial EEPROM, which shares two pins (SCL_MDC and SDA_MDIO) with SMI, is optional for advanced configuration.
SCL_MDC and SDA_MDIO are tri-state during hardware reset (pin RESET#=0). The RTL8305SB will try to automatically
find the serial EEPROM upon reset only if pin EnEEPROM is 1. Because the pin SDA_MDIO is pulled up by an external
resistor. If and only if the NoEEPROM of serial EEPROM (bit 0 of the first byte) is 0, the RTL8305SB will load all contents
of the serial EEPROM into internal registers. Otherwise, the RTL8305SB will use the default values for the internal.
Internal registers can still be accessed after reset via SMI (pin SCL_MDC and SDA_MDIO). Serial EEPROM signals and SMI
signals should not exist in the same time. In order to use the SMI to change configuration flexibly, internal registers include
content of some pins and all serial EEPROM: Pin register and EEPROM register. Those registers do not work in real time.
Soft Reset is necessary after changing the EEPROM or Pin registers.
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7.3.3 Example of Serial EEPROM: 24LC02
The 24LC02 interface is a 2-wire serial EEPROM interface providing 2K bits storage space. The 24LC02 should be 2.5V
compatible.
7.3.4 24LC02 Device Operation
Clock and Data transitions: The SDA pin is normally pulled high with an external resistor. Data on the SDA pin may change only
during SCL low time periods. Data changes during SCL high periods will indicate a start or stop condition as defined below.
Start condition: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command.
Stop condition: A low-to-high transition of SDA with SCL high is a stop condition.
Acknowledge: All addresses and data are transmitted serially to and from the EEPROM in 8-bit words. The 24LC02 sends a
zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
Random Read: A random read requires a "dummy" byte write sequence to load in the data word address.
Sequential Read: For the RTL8305SB, the sequential reads are initiated by a random address read. After the 24LC02 receives
a data word, it responds with an acknowledgement. As long as the 24LC02 receives an acknowledgement, it will continue to
increment the data word address and clock out sequential data words in serial.
*Start and Stop Definition
SDA
SCL
START
*Output Acknowledge
SCL
STOP
1
8
9
DATA IN
DATA OUT
START
ACKNOWLEDGE
*Random Read
STOP
READ
START
WRITE
START
WORD
DEVICE
DEVICE
ADDRESS
ADDRESS n
ADDRESS
SDA
DATA n
NO ACK
ACK
ACK
ACK
R/w
DUMMY WRITE
*Sequential Read
STOP
ACK
ACK
READ
DEVICE
ADDRESS
SDA
DATA n
DATA n+x
NO ACK
43
…
ACK
ACK
ACK
R/W
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7.3.5 SMI
The SMI (Serial Management Interface) is also known as the MII Management Interface, which consists of two signals
(MDIO and MDC), and allows external devices with SMI master mode (MDC is output) to control the state of the PHY and
internal registers (SMI slave mode: MDC is input). MDC is an input clock for the RTL8305SB to latch MDIO on its rising
edge. The clock can run from DC to 25MHz. MDIO is a bi-directional connection used to write data to, or read data from the
RTL8305SB. The PHY address is from 0 to 4.
SMI Read/Write Cycles
Preamble
(32 bits)
Read
Write
1……..1
1……..1
Start
(2 bits)
OP Code
(2 bits)
PHYAD
(5 bits)
REGAD
(5 bits)
01
01
10
01
AAAAA
AAAAA
RRRRR
RRRRR
Turn
Around
(2 bits)
Z0
10
Data
(16 bits)
Idle
D…….D
D…….D
Z*
Z*
Z*: high-impedance. During idle time, MDIO state is determined by an external 1.5KΩ pull-up resistor.
The RTL8305SB supports Preamble Suppression, which allows the MAC to issue Read/Write Cycles without preamble bits.
However, for the first cycle of MII management after power-on reset, a 32-bit preamble is needed.
To guarantee the first successful SMI transaction after power-on reset, external device should delay at least 1sec to issue the
first SMI Read/Write Cycle relative to the rising edge of reset.
7.3.6 Head-Of-Line Blocking
The RTL8305SB incorporates an advanced mechanism to prevent Head-Of-Line blocking problem when flow control is
disabled. When the flow control function is disabled, the RTL8305SB will first check the destination address of the incoming
packet. If the destined port is congested, the RTL8305SB will discard this packet to avoid the blocking of the next packet,
which is going to a non-congested port.
7.3.7 802.1Q Port Based VLAN
The RTL8305SB supports five VLAN groups: VLAN A, B, C, D, and E. Two association ingress rules are provided to map a
frame to a given VLAN: port based and tagged-VID (VLAN Identifier).
Port based VLAN mapping is the simplest implicit mapping rule. A frame belongs to a VLAN is based on the index of the port
which it came from. P0VLANIndex[2:0], P1VLANIndex[2:0], P2VLANIndex[2:0], P3VLANIndex[2:0], and
P4VLANIndex[2:0] are used for each port as the distinguishing characteristic of a VLAN. Using the default value as an
example, P0VLANIndex[2:0]=0b000 means port 0 belongs to VLAN A. P1VLANIndex[2:0]=0b001 means port 1 belongs to
VLAN B. P2VLANIndex[2:0]=0b010 means port 2 belongs to VLAN C. P3VLANIndex[2:0]=0b011 means port 3 belongs to
VLAN D. P4VLANIndex[2:0]=0b100 means port 4 belongs to VLAN E.
The 12-bit tagged-VID is the explicit indication of the frame’s VLAN association. A total of 4094 values are possible. The
value of all ones (0xFFF) is reserved and currently unused. The value of all zero (0x000) indicates a priority tag. A priority
tagged frame is treated the same as an untagged frame. VIDA[11:0], VIDB[11:0], VIDC[11:0], VIDD[11:0], and VIDE[11:0]
are used as the distinguishing characteristic for each VLAN. For example, VIDA[11:0]=0x001 means frame with
tagged-VID=0x001 belongs to VLAN A. VIDB[11:0]=0x002 means frame with tagged-VID=0x002 belongs to VLAN B. VID
filed have no default values in the register, users must assign them in the serial EEPROM or register via SMI for the
Tagged-VID application.
Byte0~5
DA
Byte6~11
SA
Byte12~13
81-00
Byte14.7~14.5
User-Priority
( 0~3:Low-pri ; 4~7:
High-pri )
Byte14.4
CFI
0
Byte14.3~15.0
VID
Table 1: 802.1Q VLAN tag frame format
For the egress rule, each VLAN has a Member Set field. Member set of a VLAN indicates which ports belong to this VLAN.
Ports in the member set for a given VLAN can be expected to receive and transmit frames belonging to that VLAN; ports not
in the member set should generally not be receiving and/or transmitting frames for that VLAN. For the RTL8305SB, the
member set for a VLAN can be configured by serial EEPROM or register via SMI. Using the default value as an example,
MemberA[4:0]=10001 means port 4 and 0 are members of VLAN A. MemberB[4:0]=10010 means port 4 and 1 are members
of VLAN B. MemberC[4:0]=10100 means port 4 and 2 are members of VLAN C. MemberD[4:0]=11000 means port 4 and 3
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are members of VLAN D. MemberE[4:0]=11111 means all ports are members of VLAN E.
When the serial EEPROM does not exist and pin DisVLAN=1, the RTL8305SB will disable the VLAN function. The SMI can
be used to update the registers then do SoftReset to enable and change the VLAN.
When the serial EEPROM does not exist and pin DisVLAN=0, the RTL8305SB will use the default values for the internal
register to provide a useful Port based VLAN mapping: P0VLANIndex[2:0]=0b000, P1VLANIndex[2:0]=0b001,
P2VLANIndex[2:0]=0b010, P3VLANIndex[2:0]=0b011, and P4VLANIndex[2:0]=0b100; MemberA[4:0]=10001,
MemberB[4:0]=10010, MemberC[4:0]=10100, MemberD[4:0]=11000, MemberE[4:0]=11111. Port 0 to 3 will be set at
different VLAN and share the overlapping port 4. User can use SMI to update the register then do SoftReset to change the
VLAN configuration.
Port 0
Port 1
Port 2
Port 3
Port 4
PortVLANIndex
A
B
C
D
E
Member A
V
Member B
Member C
Member D
V
V
V
V
V
V
V
Member E
V
V
V
V
V
Table 2: 802.1Q VLAN default setup
When an EEPROM is used, the RTL8305SB will ignore the pin and will load the initial value of the internal registers with the
EEPROM values.
When register DisVLAN=1, the RTL8305SB will disable the VLAN function. When register DisVLAN=0, RTL8305SB will
use the values of internal register to determine the VLAN mapping.
If the 802.1Q tagged-VID Aware function is enabled (DisTagAware=0), the RTL8305SB will check the tagged VID of the
received frame to do the VLAN classification. The RTL8305SB will use tagged-VID VLAN mapping for tagged frames and
will use Port Based VLAN mapping for untagged and priority-tagged frames. For example, if a tagged frame with
tagged-VID=0x001 is received from port1, it will be classified as VLAN A when VIDA[11:0]=0x001. If the tagged-VID
Aware function is disabled, the RTL8305SB will always use Port Based VLAN mapping. For example, if a tagged frame with
tagged-VID=0x001 is received from port1, it will be classified as VLAN B when P1VLANIndex[2:0]=0b001.
The Acceptable Frame Type of Ingress Process can be “Admit All” or “Admit All Tagged”. When DisTagAdmitCtrl=1, the
Acceptable Frame Type of Ingress Process will be “Admit All” and the RTL8305SB will receive all frames. When
DisTagAdmitCtrl=0, the Acceptable Frame Type of Ingress Process will be “Admit All Tagged”. The RTL8305SB will receive
only the VLAN-tagged frame and drop all other untagged frames and priority tagged (VID=0) frames.
When DisMemFilter=1, the VLAN Ingress Member set filtering is disabled. The RTL8305SB will not discard any frames
associated with a VLAN for which that port is not in the member set. If the VLAN Ingress Member set filtering is enabled by
setting DisMemFilter=0, RTL8305SB will discard any frame associated with a VLAN for which that port is not in the member
set. For example, RTL8305SB will drop the frame with tagged-VID=0x002 received from port0 when DisVLAN=0,
DisTagAware=0, DisMemFilter=0, VIDB[11:0]=0x002, and MemberB[4:0]=0b10010 (Port4 and 1 belong to the member set
of VLAN B).
Two options can be used for special application. ARP VLAN: If DisARP=0, ARP broadcast frames (the RTL8305SB only
checks frames with DID=all F, Type=0806) will be broadcast to all VLAN. Otherwise, ARP broadcast frames, like other
frames, can only be forwarded to the same VLAN. Leaky VLAN: If DisLeaky=0, unicast frames, not including broadcast and
multicast frames, can traverse VLANs. Otherwise, unicast frames can only be forwarded to the same VLAN, like broadcast
and multicast frames.
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7.3.8 QoS Function
The RTL8305SB can recognize the QoS priority information of the incoming packets to give a different egress service priority.
The RTL8305SB identifies the packets as high priority based on several types of QoS priority information that based on: 1) Port
based priority; 2) 802.1p/Q VLAN priority tag; 3) TCP/IP's TOS/DiffServ (DS) priority field. These types of QoS are selected by
hardware pins DisPortPri[4:0], DisTagPri and DisDSPri respectively upon reset or internal registers via SMI after reset.
There are 2 priority queues, a high-priority queue and a low-priority queue, supported by the RTL8305SB to buffer high and
low priority frames. The queue service rate is based on the Weighted Round Robin algorithm, the packet based service weight
ratio of high-priority queue and low-priority queue can be set as 4:1, 8:1, 16:1 or "Always high priority first" by hardware pins
QWeight[1:0] upon reset or internal register via SMI after reset.
When Port based priority is applied, any packets received from the high priority port, which is set by DisPortPri[4:0], will be
sent to the high priority queue of the destination port.
When 802.1p VLAN tag priority applied, the RTL8305SB can recognize the 802.1Q VLAN tag frames and extract the 3-bit
User_Priority information from the VLAN tag. The RTL8305SB sets the threshold of User_Priority as 3. Therefore, VLAN
tagged frames with User_Priority value = 4~7 will be treat as high priority frames, other User_Priority values (0~3) as low
priority frames (follows 802.1p standard).
When TCP/IP's TOS/DiffServ(DS) based priority is applied, the RTL8305SB can recognize TCP/IP Differentiated Services
Codepoint (DSCP) priority information from the DS-field defined on RFC2474. The DS field byte for the IPv4 is
Type-of-Service (TOS) octet and for IPv6 is Traffic-Class octet. The recommended DiffServ Codepoint is defined in RFC2597
to classify the traffic into different service classes. The RTL8305SB can extract the codepoint value of DS-field from IPv4 and
IPv6 packets, and identify the priority of the incoming IP packet follows the definition as bellow:
High priority: whose DS-field = (EF ,expected forwarding:) 101110;
(AF, Assured Forwarding:) 001010; 010010; 011010; 100010
(Network Control:) 110000 and 111000.
Low priority: whose DS-field = others values.
The VLAN tagged frame and 6-bit DS-field in IPv4 and IPv6 frame format are shown bellow:
6 bytes
DA
6 byte
SA
2 byte
81-00
3 bits
User-Priority
( 0~3:Low-pri ; 4~7: High-pri )
----
Table 3: 802.1Q VLAN tag frame format
6 bytes
DA
6 byte
SA
6 bytes
DA
6 byte
SA
4 byte
802.1Q Tag
(optional)
4 byte
2 byte
08-00
4 bits
Version
IPv4= 0100
4 bits
Version
IPv6= 0110
Table 4: IPv4/6 frame format
802.1Q Tag
(optional)
2 byte
08-00
4 bit
IHL
6 bits
TOS[0:5]
= DS-field
6 bits
Traffic Class [0:5]
=DS-field
----
----
Note: IPv6 refer to rcf2460
The RTL8305SB can automatically turn off 802.3x flow control and Back pressure flow control for 1~2 sec whenever the port
receives VLAN-tag or TOS/DS high priority frames, the flow control is re-enabled when no priority frame is received during a
1~2 sec duration. The hardware pin DisFCAutoOff upon reset or internal register via SMI after reset can enable this auto-turn
off function.
7.3.9 Insert/Remove VLAN Priority Tag
When QoS function is enabled, a tag can be inserted or removed on a per output port basis. The RTL8305SB will insert
VLAN priority-tag (VID=0x000) for untagged frames only, or remove a tag for all types tagged frames. Port 4 can use two
strapping pins upon reset or internal registers via SMI after reset to set Insert/Remove function. Other ports can use a serial
EEPROM upon reset or internal registers via SMI after reset to set this function. For example: When P0IRTag[1:0]=10, the
RTL8305SB will insert priority tag for untagged frame from Output High Queue (user priority field=0b111, CFI=0,
VID=0x000) of Port0 and Low Queue of Port0 (user priority field=0b000, CFI=0, VID=0x000). When P0IRTag[1:0]=01, the
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RTL8305SB will insert priority tag only from Output High Queue of Port0 (user priority field=0b111, CFI=0, VID=0x000).
If the tag removed frame is less than 64 bytes, it should add PAD with a "0x20" pattern at the packet before CRC field to fit
64-byte min packet length of IEEE 802.3 spec. The RTL8305SB will recalculate the FCS if the frame had been changed.
7.3.10 Filtering/Forwarding Reserved Control Frame
The RTL8305SB supports the ability to forward or drop the frames of the 802.1D specified reserved group MAC addresses
(control frames): 01-80-C2-00-00-03 to 01-80-C2-00-00-0F.
Address
Use
01-80-C2-00-00-00
Bridge Group Address
01-80-C2-00-00-01
Pause Control Frame
01-80-C2-00-00-02
01-80-C2-00-00-03 to
Reserved
01-80-C2-00-00-0F
Any other multicast Address
Table 5: EnForward=1: same as RTL8305S
Action
Forward to all ports
Drop Frame
Drop Frame
Forward to all ports
Address
01-80-C2-00-00-00
01-80-C2-00-00-01
01-80-C2-00-00-02
01-80-C2-00-00-03 to
01-80-C2-00-00-0F
Any other multicast Address
Action
Forward to all ports
Drop Frame
Drop Frame
Drop Frame
Forward to all ports
Use
Bridge Group Address
Pause Control Frame
Reserved
Table 6: EnForward=0
Forward to all ports
7.3.11 Broadcast Storm Control
According to the latched value of DISBRDCTRL pin upon reset, the RTL8305SB determines whether or not to proceed with
broadcast storm control. Once enabled (DISBRDCTRL=0), after consecutive 64 broadcast (DID=FFFF-FFFF-FFFF) packets
are received by one port, the incoming consecutive broadcast packets during around 800ms time window of this port will be
discarded. Any non-broadcast packet can reset the time window and broadcast counter such that the scheme restarts. It is per
port based. Note2: Trigger condition: consecutive 64 DID = FFFF-FFFF-FFFF packets. Release condition: receive
non-broadcast packet on or after 800ms.
7.3.12 Broadcast In/Out Drop
If some destination ports are blocking and the buffer is full, broadcast frames should be dropped according to configuration.
Input Drop: do not forward to any port and drop the frame directly. Output Drop: forward only to non-blocking ports
(Broadcast becomes multicast).
1. Broadcast packet from Port0
2. Buffer of Port4 is full, others are not full
Port 0
1
2
3
4
Port 0
Full
1
2
3
4
Full
Rx:
Rx:
Input Drop: same as RTL8305S
Output Drop
Figure 1: Input Drop v.s. Output Drop
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7.3.13 Loop Detection
Loops should be avoided between switch applications. The simplest loop as shown below results in: 1) Unicast frame
duplication; 2) Broadcast frame multiplication; 3) Address table nonconvergence. Frame may be transmitted from Switch1 to
Switch2 via Link1, then return to Switch1 via Link2.
S w itc h
1
L in k 1
S w itc h
L in k 2
2
Figure 2: Example of Loop
When the loop detection function is enabled by setting DisLoop=0 in EEPROM or an internal register, the RTL8305SB
periodically sends out a broadcast 64-byte packet every 3~5 minutes and automatically detect whether if there is a network loop
(or bridge loop) existence. The LoopLED# will be ON (active low or high) to indicate that a loop exits. The LED goes out by
unplugging both of the RTL8305SB ports of the loop. The Loop frame length is 64 bytes and its format as shown below.
Table 7: Loop frame format
FFFF FFFF FFFF SID
8899
0300 000…0000
CRC
In order to achieve loop detection, each switch device needs different SID (Source MAC address Identifier) for detection. So
that, the different EtherID is needed for each device when the loop detection function is enabled. If the EEPROM is not used, a
unique EtherID via SMI should be assigned after reset and the default EtherID (0x5254 4c83 05b0) should not be used.
Ethernet MAC address byte (bit) ordering: For example, MAC address is 52 54 4c 00 01 02. According to 802.3, 0x52 is byte
0, 0x54 is byte 1, 0x02 is byte 5,
Byte 0
Bytes --- 52
Bits
Byte 1
54
--- 0101 0010
Bit7
Byte 2
4c
0101 0100
Bit0 Bit15
Bit8
Byte 3
00
0100 1100
Byte 4
01
0000 0000
0000 0001
…………….
The order of bit transmission is low-order bit first. From bit0 to bit47:
0100 1010
0010 1010 0011 0010 0000 0000 1000 0000
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Byte 5
02
0000 0010
Bit47
Bit40
0010 0000
Rev.1.0
RTL8305SB
7.3.14 MAC Loopback return to External
Each port supports loopback of the MAC (return to external device) function for diagnostic purposes. For example: If the
internal register DisP4LoopBack=0, the RTL8305SB will “forward local and broadcast packets from the input of Port4 to
output of Port4” and “drop unicast packets from the input of Port4”. The other port still can forward broadcast or unicast
packets to port4. Example2: If the internal register DisP3LoopBack=0, the RTL8305SB will “forward local and broadcast
packets from the input of Port3 to output of Port3” and “drop unicast packets from input of Port3”. The other port still can
forward broadcast or unicast packets to port3.
This is especially useful for router applications to perform mass production tests. This function does nothing with PHY type
(GxMode/GyMode/P4Mode[1:0]) and can be done on each mode. Below are two examples: In Example 1, the external device
(CPU) is connected to MII or SNI interface of Port4. In Example 2, the external device (CPU) does not have an MII or SNI
interface, so it can use the PCI interface to connect RTL8139 to the UTP of Port4.
Example 1: LoopBack in external PHY
8305SB
MII/SNI
CPU
Example 2: LoopBack in UTP
8305SB
UTP
8139
PCI
CPU
Figure 3: Port4 Loopback
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7.3.15 Reg0.14 PHY Loopback return to Internal
The loopback mode of the PHY (return to internal MAC) can be enabled on a per port base by setting MII Reg.0.14 as 1. In
Reg0.14 loopback mode, TXD of PHY is transferred directly to RXD of PHY with TXEN changed to CRS_DV and returns to
MAC via internal MII. The data stream coming from the MAC will not egress to the physical medium and incoming data
stream from the network medium will be blocked in this mode. The packets will be looped back in 10Mbps full duplex or
100Mbps at full duplex mode. This function is especially useful for diagnostic purposes. For example, a NIC can be used to
send broadcast frame into port 0 of the RTL8305SB and set Port1 as Reg0.14 Loopback. The frame will be looped back to port
0, so the received packet count can be checked to verify that the switch device is good. In this example, port 0 can be 10M or
100M and full or half duplex.
Reg0.14 Loopback
MAC
Internal MII
PHY
Figure 4: Reg0.14 Loopback
7.3.16 LED
The RTL8305SB supports four parallel LEDs for each port, and two special LEDs (SELMIIMAC# and LOOPLED#). Each
port has four LED indicator pins. Each pin may have different indicator meaning set by pins LEDMode[1:0], refer to the pin
descriptions for details. Upon reset, the RTL8305SB supports diagnostics of chip reset and LED functions by blinking all
LEDs once for 320ms. This function can be disabled by asserting EN_RST_LINK to 0. LED_BLINK_TIME determines LED
blinking period for activity and collision, with 1 = 43ms and 0 = 120ms. The parallel LEDs corresponding to port 4 can be
three-stated (disable LED functions) for MII port application by setting ENP4LED in EEPROM as 0. In UTP application, this
bit should be 1 to drive LEDs of port 4.
All LED pins are dual function pins: input operation for configuration upon reset, and output operation for LED after reset. If
the pin input is floating upon reset, the pin output is active low after reset. Otherwise, if the pin input is pulled down upon reset,
the pin output is active high after reset. Exception: Bi-color Link/Act mode of pin LED_ADD[4:0] when LEDMode[1:0]=10.
Below shows an example circuits for LEDs. The typical values for pull-down resistors are 10K Ω.
Floating
Pull Down
2.5V
LED pin
8305SB
250 ohm
250 ohm
10K ohm
8305SB
LED pin
Figure 5: Floating and Pull-Down of LED pins
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For two pin Bi-color LED mode (LEDMode[1:0]=10), Bi-color Link/Act (pin LED_ADD) and Spd (pin LED_SPD) can be used
for one Bi-color LED package, which is a single LED package with two LEDs connected in parallel with opposite polarity. When
LEDMode[1:0]=10, the active status of LED_ADD is opposite with LED_SPD, does nothing with input upon reset.
Indication
No Link
100M Link
10M Link
100M Act
10M Act
Bi-Color state
Both Off
Green On
Yellow On
Green Flash
Yellow Flash
Spd:Input=Floating, Active Low.
Spd:Input=Pull-down, Active High.
Bi-color Link/Act: the active status of Bi-color Link/Act: the active status of
LED_ADD is opposite with LED_SPD, LED_ADD is opposite with LED_SPD,
does nothing with input upon reset.
does nothing with input upon reset.
Spd
Link/Act
Spd
Link/Act
1
1
0
0
0
1
1
0
1
0
0
1
0
Flash
1
Flash
1
Flash
0
Flash
Table 8: Truth table of Spd and Bi-color Link/Act
Yellow
Link/Act
Spd
Green
Figure 6: Two pin Bi-color LED for SPD floating or Pull-high
Yellow
Spd
Link/Act
Green
Figure 7: Two pin Bi-color LED for SPD Pull-down
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7.3.17 2.5V Power Generation
The RTL8305SB can use a PNP transistor to generate 2.5V from a 3.3V power supply. This 2.5V is used for the digital core
and analog receiver circuits. Do not use one PNP transistor for more than one RTL8305SB chip, even if the rating is enough:
Use one transistor for each RTL8305SB chip.
Do not connect any inductor (bead) directly between the collector of PNP transistor and VDDAL. This will affect the stability
of the 2.5V power significantly if the inductor (bead) exists.
3.3V
RTL8305SB
3.3V
VDDH
VDDH: 3.3V
VDDL: 2.5V
2SB1197K
Ic(max.)
=800mA
VCTRL
VDDL
2.5V
47uF/10uF/0.1uF
Figure 8: Use PNP Transistor to transform 3.3V into 2.5V
Use PNP transistor
Parameter
Symbol to
Collector-base voltage
VCBO
Collector-emitter voltage
VCEO
Emitter-base voltage
VEBO
Collector current
IC
Collector power dissipation
PC
transform
3.3V into
Limits
Unit 2.5V
-40
-32
-5
-0.8
0.2
V
V
V
A(DC)
W
Junction temperature
Tj
150
°C
Storage temperature
Tstg
-55~+150
°C
Table 9: Example of Power Transistor 2SB1197K
Absolute maximum ratings (Ta=25°C)
For more information, refer to http://www.rohm.com
7.3.18 Crystal/Oscillator
• The frequency is 25Mhz. The maximum Frequency Tolerance is +/- 100ppm. The maximum Jitter is 150 ps Peak to Peak.
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8. Serial EEPROM Description
Unused Registers and bits are reserved for future or internal use, and should use the default value.
Name
Internal
Internal
Internal
Internal
Internal
Internal
Internal
NoEEPROM
Reg.bit
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Internal
DisLoop
1.7
1.6
Internal
Internal
EnP4LED
1.5
1.4
1.3
Description
Internal use only
Internal use only
Internal use only
Internal use only
Internal use only
Internal use only
Internal use only
No EEPROM:
1: EEPROM does not exist.
0: EEPROM exist.
Internal use only
Disable Loop Detection Function:
1: Disable Loop Detection function.
0: Enable Loop Detection function.
Internal use only
Internal use only
Enable Port4 LED:
1: Drive LED pins of port4.
0: Do not drive LED pins of port4 for special application.
Default
1
1
1
1
1
1
1
0
1
1
1
1
1
In UTP application, this bit should be 1 to drive the LEDs of port 4.
Reserved for original RTL8305S user only. Not used for general applications.
Reserved
Reserved
Reserved
Reserved
Internal
Reserved
Internal
EthernetID
1.2
1.1
1.0
2.7~2.4
2.3~2.0
3.7~3.2
3.1~3.0
4~9
Reserved
P1VLANIndex[2]
P1VLANIndex[1]
P1VLANIndex[0]
Reserved
P0VLANIndex[2]
P0VLANIndex[1]
P0VLANIndex[0]
10.7
10.6
10.5
10.4
10.3
10.2
10.1
10.0
Reserved
P3VLANIndex[2]
P3VLANIndex[1]
P3VLANIndex[0]
Cont…
11.7
11.6
11.5
11.4
Internal use only
Device Ethernet MAC ID (6 bytes).
Example: for MAC ID = 52 54 4c 83 05 b0.
Byte4 = 0x52 (Byte 1 of MAC ID).
Byte5 = 0x54 (Byte 2 of MAC ID).
Byte6 = 0x4c (Byte 3 of MAC ID).
Byte7 = 0x83 (Byte 4 of MAC ID).
Byte8 = 0x05 (Byte 5 of MAC ID).
Byte9 = 0xb0 (Byte 6 of MAC ID).
Port 1 VLAN Index:
P1VLANIndex[2:0]=001 means port 1 uses the second VLAN (VLAN B).
Port 0 VLAN Index:
P0VLANIndex[2:0] are used to assign the VLAN of port 0. For example,
P0VLANIndex[2:0]=000 means port 0 use the first VLAN (VLAN A).
1
1
1
1
1111
1
11
0x52
0x54
0x4c
0x83
0x05
0xb0
1
001
1
000
P0VLANIndex[0] is bit0, P0VLANIndex[1] is bit1, P0VLANIndex[2] is bit2.
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P3VLANIndex[2:0]=011 means port 3 use the forth VLAN (VLAN D).
53
1
011
Rev.1.0
RTL8305SB
Reserved
P2VLANIndex[2]
P2VLANIndex[1]
P2VLANIndex[0]
Reserved
P4VLANIndex[2]
P4VLANIndex[1]
P4VLANIndex[0]
P3IRTag[1]
P3IRTag[0]
11.3
11.2
11.1
11.0
12.7
12.6
12.5
12.3
12.2~12.0
13.7
13.6
Port 2 VLAN Index:
P2VLANIndex[2:0]=010 means port 2 use the third VLAN (VLAN C).
11111
Port 4 VLAN Index:
P4VLANIndex[2:0]=100 means port 4 use the fifth VLAN (VLAN E).
100
11
Internal
14~17
Insert/Remove Priority Tag of Port3:
11: Do not insert/remove Tag from Output High and Low Queue of Port3.
10: Insert Tag from Output High and Low Queue of Port3.
01: Insert Tag from Output High Queue only of Port3.
00: Remove Tag from Output High and Low Queue of Port3.
Insert/Remove Priority Tag of Port2:
11: Do not insert/remove Tag from Output High and Low Queue of Port2.
10: Insert Tag from Output High and Low Queue of Port2.
01: Insert Tag from Output High Queue only of Port2.
00: Remove Tag from Output High and Low Queue of Port2.
Insert/Remove Priority Tag of Port1:
11: Do not insert/remove Tag from Output High and Low Queue of Port1.
10: Insert Tag from Output High and Low Queue of Port1.
01: Insert Tag from Output High Queue only of Port1.
00: Remove Tag from Output High and Low Queue of Port1.
Insert/Remove Priority Tag of Port0:
11: Do not insert/remove Tag from Output High and Low Queue of Port0.
10: Insert Tag from Output High and Low Queue of Port0.
01: Insert Tag from Output High Queue only of Port0.
00: Remove Tag from Output High and Low Queue of Port0.
Internal use only
Internal
18~21
Internal use only
Internal
22~25
Internal use only
Internal
26~29
Internal use only
P2IRTag[1]
P2IRTag[0]
13.5
13.4
P1IRTag[1]
P1IRTag[0]
13.3
13.2
P0IRTag[1]
P0IRTag[0]
13.1
13.0
VIDA[11:0]
31.3~30.0
Reserved
Reserved
Cont…
31.7~31.4
32.7~32.5
2002/04/09
1
010
VLAN Identifier of VLAN A:
Reg31.3=VIDA[11], Reg30.0=VIDA[0].
11
11
11
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0x001
1111
111
54
Rev.1.0
RTL8305SB
MemberA[4:0]
32.4~32.0
VIDB[11:0]
Reserved
Reserved
MemberB[4:0]
34.3~33.0
34.7~34.4
35.7~35.5
35.4~35.0
VIDC[11:0]
Reserved
Reserved
MemberC[4:0]
37.3~36.0
37.7~37.4
38.7~38.5
38.4~38.0
VIDD[11:0]
Reserved
Reserved
MemberD[4:0]
40.3~39.0
40.7~40.4
41.7~41.5
41.4~41.0
VIDE[11:0]
Reserved
Reserved
MemberE[4:0]
43.3~42.0
43.7~43.4
44.7~44.5
44.4~44.0
Reserved
DisVLAN
DisTagAware
45.7~6
45.5
45.4
Member Set of VLAN A:
MemberA[4:0] determines the VLAN member of VLAN A.
MemberA[4:0]=10001 means port4 and port0 are the members of VLAN
A.
MemberA[4:0]=10010 means port4 and port1 are the members of VLAN
A.
MemberA[4:0]=11111 means all ports are the members of VLAN A.
VLAN Identifier of VLAN B:
Member Set of VLAN B:
MemberB[4:0]=10010 means port4 and port1 are the members of VLAN
B.
VLAN Identifier of VLAN C:
Member Set of VLAN C:
MemberC[4:0]=10100 means port4 and port2 are the members of VLAN
C.
VLAN Identifier of VLAN D:
Member Set of VLAN D:
MemberD[4:0]=11000 means port4 and port3 are the members of VLAN
D.
VLAN Identifier of VLAN E:
Member Set of VLAN E:
MemberE[4:0]=11111 means all ports are the members of VLAN E.
10001
0x002
1111
111
10010
0x003
1111
111
10100
0x004
1111
111
11000
0x005
1111
111
11111
1
1
Disable VLAN:
1: Disable VLAN
0: Enable VLAN
This register has higher priority than pin.
Disable Tag Aware:
1: Disable the 802.1Q tagged-VID Aware function. The RTL8305SB will
not check the tagged VID of a received frame to do the VLAN
classification. The RTL8305SB will always use Port Based VLAN mapping.
0: Enable the Member Set Filtering function of VLAN Ingress Rule. the
RTL8305SB will check the tagged VID of received frame to do the VLAN
classification. The RTL8305SB will use tagged-VID VLAN mapping for
tagged frame and will use Port Based VLAN mapping for untagged and
priority-tagged frame.
1
Cont…
2002/04/09
55
Rev.1.0
RTL8305SB
DisMemFilter
45.3
DisTagAdmitCtrl
45.2
DisLeaky
45.1
Disable Member Set Filtering:
1: Disable the Member Set Filtering function of the VLAN Ingress Rule.
The RTL8305SB will not discard any frames associated with a VLAN for
which that port is not in the member set.
0: Enable the Member Set Filtering function of the VLAN Ingress Rule.
The RTL8305SB will discard any frames associated with a VLAN for which
that port is not in the member set.
Disable Tag Admit Control: Covers acceptable frame type.
1: Disable Tag Admit Control: Acceptable Frame Type is “Admit All”. The
RTL8305SB will receive all frames.
0: Enable Tag Admit Control: Acceptable Frame Type is “Admit All
Tagged”. The RTL8305SB will receive only the VLAN-tagged frame and
drop all other untagged frame and priority tagged (VID=0) frame.
Disable Leaky VLAN:
1: Disable to forward unicast frames to other VLAN.
0: Enable to forward unicast frames to other VLAN.
1
1
1
Broadcast and multicast frames adhere to the VLAN configuration.
DisARP
45.0
This register has higher priority than pin.
Disable ARP broadcast to all VLAN:
1: Disable to broadcast the ARP broadcast packet to all VLANs.
0: Enable to broadcast the ARP broadcast packet to all VLANs.
1
ARP broadcast frame: DID is all F.
This register has higher priority than pin.
Reserved
Internal
Internal
Internal
Internal
2002/04/09
46.7
46.6
46.5~3
46.2~0
47~52
1
1
000
100
0x52
0x54
0x4c
0x83
0x05
0xb1
Internal use only
Internal use only
Internal use only
Internal use only
56
Rev.1.0
RTL8305SB
9. Electrical Characteristics
9.1 Absolute Maximum Ratings:
WARNING: Absolute maximum ratings are limits beyond which may cause permanent damage to the device or affect device
reliability. All voltages are specified reference to GND unless otherwise specified.
Parameter
Storage Temperature
Vcc Supply Referenced to GND
Digital Input Voltage
DC Output Voltage
Min
-55
-0.5
-0.5
-0.5
Max
+150
+4.0
VDD
VDD
Units
°C
V
V
V
Min
0
3.15
2.375
Max
+70
3.45
2.625
Units
°C
V
V
9.2 Operating Range:
Parameter
Ambient Operating Temperature(Ta)
3.3V Vcc Supply Voltage Range(VDDAH)
2.5V Vcc Supply Voltage Range
(VDDAL,VDD)
9.3 DC Characteristics
Parameter
Power Supply Current for
2.5V
Power Supply Current for
3.3V
Total Power Consumption
for all ports
TTL Input High Voltage
TTL Input Low Voltage
TTL Input Current
TTL Input Capacitance
Output High Voltage
Output Low voltage
2002/04/09
SYM
Conditions
Icc 10 Base-T, idle
10 Base-T, Peak continuous 100% utilization
100 Base-TX, idle
100 Base-TX, Peak continuous 100% utilization
Power saving
Power down
Icc 10 Base-T, idle
10 Base-T, Peak continuous 100% utilization
100 Base-TX, idle
100 Base-TX, Peak continuous 100% utilization
Power saving
Power down
PS 10 Base-T, idle
10 Base-T, Peak continuous 100% utilization
100 Base-TX, idle
100 Base-TX, Peak continuous 100% utilization
Power saving
Power down
Vih
Vil
Iin
Cin
Voh
Vol
57
Min
Typical
Max
Units
mA
mA
mW
1.5
1.0
10
-10
3
2.25
0
2.75
0.25
V
V
uA
pF
V
V
Rev.1.0
RTL8305SB
Parameter
SYM
Conditions
Min
Output Three state Leakage |IOZ|
Current
Transmitter, 100Base-TX (1:1 Transformer Ratio)
TX+/- Output Current High IOH
TX+/- Output Current Low IOL
0
Transmitter, 10Base-T(1:1 Transformer Ratio)
TX+/- Output Current High IOH
TX+/- Output Current Low IOL
0
Receiver, 100Base-TX
RX+/- Common-mode
input voltage
RX+/- Differential input
resistance
Receiver, 10BaseT
Differential Input
Resistance
Input Squelch Threshold
Typical
Max
10
Units
uA
20
mA
uA
50
mA
uA
1.6
V
20
kΩ
20
kΩ
340
mV
9.4 AC Characteristics
Parameter
Transmitter, 100Base-TX
Differential Output Voltage,
peak-to-peak
Differential Output Voltage
Symmetry
Differential Output
Overshoot
Rise/Fall time
Rise/Fall time imbalance
Duty Cycle Distortion
SYM
Conditions
VOD 50Ω from each output to Vcc, Best-fit over 14
bit times
VOS 50Ω from each output to Vcc, |Vp+|/ |Vp-|
Percent of Vp+ or VpVOO
tr ,tf 10-90% of Vp+ or Vp|tr - tf|
Deviation from best-fit time-grid, 010101 …
Sequence
Idle pattern
Timing jitter
Transmitter, 10Base-T
Differential Output Voltage, VOD 50Ω from each output to Vcc, all pattern
peak-to-peak
TP_IDL Silence Duration
Period of time from start of TP_IDL to link
pulses or period of time between link pulses
TD Short Circuit Fault
Peak output current on TD short circuit for 10
Tolerance
seconds.
TD Differential Output
Return loss from 5MHz to 10MHz for reference
Impedance (return loss)
resistance of 100 Ω.
TD Common-Mode Output Ecm Terminate each end with 50Ω resistive load.
Voltage
Transmitter Output Jitter
RD Differential Output
Return loss from 5MHz to 10MHz for reference
Impedance (return loss)
resistance of 100 Ω.
Harmonic Content
dB below fundamental, 20 cycles of all ones
data
Start-of-idle Pulse width
TP_IDL width
2002/04/09
58
Min
Typical
Max
Units
V
%
%
ns
ps
ps
ns
V
ms
mA
dB
mV
ns
dB
dB
ns
Rev.1.0
RTL8305SB
9.5 Digital Timing Characteristics
Parameter
SYM
Conditions
100Base-TX Transmit System Timing
Active TX_EN Sampled to
first bit of “J on MDI
output
Inactive TX_EN Sampled
to first bit of “T on MDI
output
TX Propagation Delay
tTXpd From TXD[1:0] to TXOP/N
100Base-TX Receive System Timing
First bit of “J on MDI input
From RXIP/N to CRS_DV
to CRS_DV assert
First bit of “T on MDI
From RXIP/N to CRS_DV
input to CRS_DV de-assert
RX Propagation Delay
tRXpd From RXIP/N to RXD[1:0]
10Base-T Transmit System Timing
TX Propagation Delay
tTXpd From TXD[1:0] to TXOP/N
TXEN to MDI output
From TXEN assert to TXOP/N
10Base-T Receive System Timing
Carrier Sense Turn-on
tCSON Preamble on RXIP/N to CRS_DV asserted
delay
Carrier Sense Turn-off
tCSOF TP_IDL to CRS_DV de-asserted
Delay
F
RX Propagation Delay
tRXpd From RXIP/N to RXD[1:0]
LED timing
LED On Time
tLEDon While LED blinking
LED Off Time
tLEDof While LED blinking
f
SMI timing
MDC
MDC clock rate
MDIO Setup Time
Write cycle
MDIO Hold Time
Write cycle
MDIO output delay relative
Read cycle
to rising edge of MDC
Min
Typical
Max
Units
Bits
Bits
Bits
6
8
Bits
16
18
Bits
15
17
Bits
5
5
6
6
Bits
Bits
12
8
Bits
9
Bits
9
12
Bits
43
43
120
120
ms
ms
25
MHz
ns
ns
ns
10
10
10
9.6 Thermal Data
Parameter
Thermal resistance:
junction to ambient,
0 ft/s airflow
Thermal resistance:
junction to case,
0 ft/s airflow
2002/04/09
SYM
θja
Conditions
4 layers PCB, ambient temperature 25°C
θjc
4 layers PCB, ambient temperature 25°C
59
Min
Typical
Max
Units
°C/W
°C/W
Rev.1.0
RTL8305SB
10. Application Information
10.1 UTP (10Base-T/100Base-TX) Application
In reviewing this material, please be advised that the center-tap in primary side of the transformer should be left floating and
can not be connected to ground through capacitors.
Vendor
Pulse
Magnetic 1
Quad
H1164
ML164
Single
H1102
ML102
Two types of transformers are generally used for the RTL8305SB. One is a Quad (4 port) transformer with one common pin on
both sides for internal connected central tap. Another is a Single (1 port) transformer with two pins on both sides for a separate
central tap.
Connected Central Tap: H1164
Transformer
RXIP
50Ω
1%
RXIN
RJ45
1:1
0.1uF
1
50Ω
1%
2
3
AGND
75Ω
RTL8305SB
4
5
TXOP
TXON
50Ω
1%
1:1
6
0.1uF
7
8
50Ω
1%
AGND
IBREF
75Ω
75Ω
1.96ΚΩ, 1%
0.01uF/1KV
AGND
Chasis GND
RTL8305SB UTP Application for Transformer with Connected Central Tap
2002/04/09
60
Rev.1.0
RTL8305SB
Separate Central Tap: H1102
RXIP
RXIN
Transformer
50Ω
1%
RJ45
1:1
0.1uF
1
75Ω
50Ω
1%
2
3
AGND
4
RTL8305SB
5
TXOP
TXON
1:1
50Ω
1% 0.1uF
6
75Ω
7
8
50Ω
1%
AGND
IBREF
75Ω
75Ω
1.96ΚΩ, 1%
0.01uF/1KV
AGND
Chasis GND
RTL8305SB UTP Application for Transformer with Separated Central Tap
2002/04/09
61
Rev.1.0
RTL8305SB
10.2 100Base-FX Application:
The following is an example for DELTA OPT-155A2H1 (3.3V fiber transceiver, 1*9 SC Duplex FDDI Fast Ethernet Optical
Transceiver Module)
RVDD (3.3V)
100Base-FX
Fiber Transceiver
82Ω
1 GND_RX
RXIP
82Ω
130Ω
AGND
RXIN
TVDD (3.3V)
2 RD+
3 RD-
130Ω
4 SD
AGND
RTL8305SB
RVDD (3.3V)
TVDD (3.3V)
82 Ω
5 VCC_RX
6 VCC_TX
7 TD-
TXON
130 Ω
82 Ω
8 TD+
AGND
TXOP
9 GND_TX
130 Ω
AGND
Chassis GND
RTL8305SB 100Base-FX Application
2002/04/09
62
Rev.1.0
RTL8305SB
11. System Application Diagram
General System Application
1. General switch application
2. Router application:
3. HomePNA application
4. Other PHY application
RTL8305SB
RTL8305SB
5x Transformer
5x Fiber Interface
1.1 General switch application:
5 port 10/100 UTP
RTL8305SB
4x Transformer
ADSL/
Cable
Modem
2.1: Router application:
4 port 10/100 UTP
1 port PHY mode MII or SNI (Port4)
3.1: HomePNA application:
4 port 10/100 UTP
1 port MAC mode MII (Port4)
1x
Fiber
Interface
Other
PHY
1x
Fiber
Interface
3x
Transformer
Router
1x
Transformer
ADSL/
Cable
Modem
2x
Fiber
HomePNA
Interface
2x
Transformer
HomePNA
1x
Transformer
2x
Fiber
4.2: Other PHY application:
1 port 100 FX (Port0)
3 port 10/100 UTP (Port1,2,3)
1 port MAC mode MII (Port4)
2x
Transformer
HomePNA
RTL8305SB
Other
PHY
4.3: Other PHY application:
2 port 100 FX (Port0,1)
2 port 10/100 UTP (Port2,3)
1 port MAC mode MII (Port4)
63
3x
Fiber
Interface
3.4: HomePNA application:
1 port 10/100 UTP (Port0)
3 port 100 FX (Port1,2,3)
1 port MAC mode MII (Port4)
RTL8305SB
Interface
ADSL/
Cable
Modem
RTL8305SB
3.3: HomePNA application:
2 port 100 FX (Port0,1)
2 port 10/100 UTP (Port2,3)
1 port MAC mode MII (Port4)
Other
PHY
3x
Fiber
Interface
2.4: Router application:
1 port 10/100 UTP (Port0)
3 port 100 FX (Port1,2,3)
1 port PHY mode MII or SNI (Port4)
RTL8305SB
RTL8305SB
4.1: Other PHY application:
4 port 10/100 UTP
1 port MAC mode MII (Port4)
2002/04/09
3x
Transformer
2x
Transformer
2.3: Router application:
2 port 100 FX (Port0, 1)
2 port 10/100 UTP (Port2,3)
1 port PHY mode MII or SNI (Port4)
3.2: HomePNA application:
1 port 100 FX (Port0)
3 port 10/100 UTP (Port1,2,3)
1 port MAC mode MII (Port4)
RTL8305SB
4x Transformer
ADSL/
Cable
Modem
RTL8305SB
HomePNA
RTL8305SB
Router
2x
Fiber
Interface
2.2: Router application:
1 port 100 FX (Port0)
3 port 10/100 UTP (Port1,2,3)
1 port PHY mode MII or SNI (Port4)
RTL8305SB
4x Transformer
3x
Transformer
4x Transformer
1.3 General switch application:
1 port 100 FX (Port0 or 4)
4 port 10/100 UTP
RTL8305SB
Router
1x
Fiber
Interface
1x Fiber
Interface
1.2 General switch application:
5 port 100 FX
RTL8305SB
Router
RTL8305SB
1x
Transformer
3x
Fiber
Interface
Other
PHY
4.4: Other PHY application:
1 port 10/100 UTP (Port0)
3 port 100 FX (Port1,2,3)
1 port MAC mode MII (Port4)
Rev.1.0
RTL8305SB
12. Design and Layout Guide
In order to achieve maximum performance using the RTL8305SB, good design attention is required throughout the design and
layout process. The following are some suggestions on recommendations to implement a high performance system.
General Guidelines
• Provide a good power source, minimizing noise from switching power supply circuits (<50mV).
• Verify the qualities of critical components such as clock source and transformer to meet application requirements.
• Keep power and ground noise levels below 50mV.
• Use bulk capacitors (4.7µF-10µF) between the power and ground planes.
• Use 0.1µF de-coupling capacitors to reduce high-frequency noise on the power and ground planes.
• Keep de-coupling capacitors as close as possible to the RTL8305SB chip.
Differential Signal Layout Guidelines
• Keep differential pairs as close as possible and route both traces as identically as possible.
• Avoid vias and layer changes if possible.
• Keep transmit and receive pairs away from each other. Run orthogonal or separate by a ground plane.
Clock Circuit
• Surround the clock by ground trace to minimize the high-frequency emission, if possible.
2.5V Power
• Do not connect a bead directly between the collector of the PNP transistor and VDDAL. This will significantly affect the
stability of the 2.5V power if such a bead is used.
• Use a bulk capacitor (4.7µF-10µF) between the collector of the PNP transistor and the ground plane.
• Do not use one PNP transistor for more than one RTL8305SB chip, even if the rating is enough. Use one transistor for each
RTL8305SB chip.
Power Planes
• Divide the power plane into 2.5V digital, and 3.3V analog.
• Use 0.1µF decoupling capacitors and bulk capacitors between each power plane and the ground plane.
Ground Planes
• Keep the system ground region as one continuous, unbroken plane that extends from the primary side of the transformer to
the rest of the board.
• Place a moat (gap) between the system ground and chassis ground.
• Ensure the chassis ground area is voided at some point such that no ground loop exists on the chassis ground area.
2002/04/09
64
Rev.1.0
RTL8305SB
13. Mechanical Dimensions
Symbol
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
θ
Dimension in inch
Min Typical Max
0.134
0.004 0.010 0.036
0.102 0.112 0.122
0.005 0.009 0.013
0.002 0.006 0.010
0.541 0.551 0.561
0.778 0.787 0.797
0.010 0.020 0.030
0.665 0.677 0.689
0.902 0.913 0.925
0.027 0.035 0.043
0.053 0.063 0.073
0.004
0°
12°
2002/04/09
Dimension in
Min Typical
0.10
0.25
2.60
2.85
0.12
0.22
0.05
0.15
13.75 14.00
19.75 20.00
0.25
0.5
16.90 17.20
22.90 23.20
0.68
0.88
1.35
1.60
0°
-
mm
Max
3.40
0.91
3.10
0.32
0.25
14.25
20.25
0.75
17.50
23.50
1.08
1.85
0.10
12°
65
1. Dimensions D & E do not include interlead flash.
2. Dimension b does not include dambar rotrusion/intrusion.
3. Controlling dimension: Millimeter
4. General appearance spec. should be based on final visual
inspection spec.
TITLE: 128 QFP (14x20 mm ) PACKAGE OUTLINE
-CU L/F, FOOTPRINT 3.2 mm
LEADFRAME MATERIAL:
APPROVE
DOC. NO.
530-ASS-P004
VERSION
1
PAGE
OF
CHECK
DWG NO.
Q128 - 1
DATE
Oct. 08 1998
REALTEK SEMICONDUCTOR CO., LTD
Rev.1.0
RTL8305SB
Realtek Semiconductor Corp.
Headquarters
1F, No. 2, Industry East Road IX, Science-based
Industrial Park, Hsinchu, 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
WWW: www.realtek.com.tw
2002/04/09
66
Rev.1.0