19-2484; Rev 0; 7/02 ECL/PECL Dual Differential 2:1 Multiplexer The MAX9384 fully differential dual 2:1 multiplexer (mux) features extremely low propagation delay (560ps max) and output-to-output skew (40ps max). The device is ideal for clock and data multiplexing applications. The two 2:1 muxes are controlled individually or simultaneously through mux select inputs COM_SEL, SEL0, and SEL1. The mux select inputs are compatible with ECL/PECL logic, and are referenced to on-chip outputs VBB0 and VBB1, nominally VCC - 1.33V. The differential inputs D, D can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip supply output VBB as a reference voltage. All the differential inputs have bias and clamp circuits that force the outputs to a low default when the inputs are left open or at VEE. The single-ended mux select inputs have pulldowns to VEE, providing low default inputs when the select inputs are left open. The device operates with a wide supply range (VCC VEE) of +3.0V to +5.5V for PECL or -3.0V to -5.5V for ECL, and is pin compatible with the MC100LVEL56 and MC100EL56. The MAX9384 is offered in a 20-pin wide SO package, and is specified for operation from -40°C to +85°C. Features ♦ 40psP-P Deterministic Jitter ♦ 440ps Differential Propagation Delay ♦ 12ps Output-to-Output Skew ♦ Individual and Common Select ♦ +3.0V to +5.5V Supplies for Differential LVPECL/PECL ♦ -3.0V to -5.5V Supplies for Differential LVECL/ECL ♦ Outputs Low for Inputs Open or at VEE ♦ >2kV ESD Protection (Human Body Model) ♦ Pin Compatible with MC100LVEL56 and MC100EL56 Ordering Information PART MAX9384EWP Applications TEMP RANGE PIN-PACKAGE -40°C to +85°C 20 Wide SO Pin Configuration High-Speed Telecom, Datacom Applications Central-Office Backplane Clock Distribution Access Multiplexers (DSLAM/DLC) Functional Diagram appears at end of data sheet. TOP VIEW D0a 1 20 VCC DOa 2 19 Q0 VBB0 3 18 Q0 D0b 4 DOb 5 17 SEL0 MAX9384 16 COM_SEL D1a 6 15 SEL1 D1a 7 14 VCC VBB1 8 13 Q1 D1b 9 12 Q1 D1b 10 11 VEE SO ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9384 General Description MAX9384 ECL/PECL Dual Differential 2:1 Multiplexer ABSOLUTE MAXIMUM RATINGS VCC - VEE .................................................................-0.3V to 6.0V Inputs (D_, D_, SEL_, COM_SEL) to VEE....-0.3V to (VCC + 0.3V) D_ to D_ ..............................................................................±3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA VBB Sink/Source Current ...............................................±0.65mA Junction-to-Ambient Thermal Resistance in Still Air 20-Lead Wide SO ....................................................+100°C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow 20-Lead Wide SO ......................................................+58°C/W Junction-to-Case Thermal Resistance 20-Lead Wide SO ......................................................+20°C/W Continuous Power Dissipation (TA = +70°C) 20-Lead Wide SO (derate 10mW/°C above +70°C) ..................................800mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Protection Human Body Model (D_, D_, Q_, Q_, SEL_, COM_SEL) .................................≥ 2kV Soldering Temperature (10s) ...........................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC - VEE = 3.0V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, 3) PARAMETER SYMBOL CONDITIONS -40°C MIN TYP +25°C MAX MIN VCC VCC 1.165 TYP +85°C MAX MIN VCC VCC 1.165 TYP MAX UNITS SINGLE-ENDED INPUT SEL_, COM_SEL Input High Voltage VIH Internally referenced to VBB, Figure 1 VCC 1.165 Input Low Voltage VIL Internally referenced to VBB, Figure 1 VCC 1.810 Input Current IIN VIH, VIL VCC - VCC 1.475 1.810 VCC - VCC 1.475 1.810 VCC V VCC 1.475 V -10 +50 -10 +50 -10 +50 µA VCC VCC 1.165 VCC VCC 1.165 VCC V VCC 1.475 V DIFFERENTIAL INPUT (D_, D_) Single-Ended Input High Voltage VIH VBB connected to the unused input, Figure 1 VCC 1.165 Single-Ended Input Low Voltage VIL VBB connected to the unused input, Figure 1 VCC 1.810 VCC - VCC 1.475 1.810 VCC - VCC 1.475 1.810 High Voltage of Differential Input VIHD Figure 1 VEE + 1.3 VCC VEE + 1.2 VCC VEE + 1.2 VCC V Low Voltage of Differential Input VILD Figure 1 VEE VCC 0.095 VEE VCC 0.095 VEE VCC 0.095 V Differential Input Voltage VIHD VILD Figure 1 0.095 3.0 0.095 3.0 0.095 3.0 V -100 +100 -100 +100 -100 +100 µA Input Current 2 IIN VIH, VIL, VIHD, VILD _______________________________________________________________________________________ ECL/PECL Dual Differential 2:1 Multiplexer (VCC - VEE = 3.0V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, 3) PARAMETER SYMBOL CONDITIONS -40°C MIN TYP +25°C MAX MIN TYP +85°C MAX MIN TYP MAX UNITS OUTPUT (Q_, Q_) Single-Ended Output High Voltage VOH Figure 2 VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC 1.085 0.998 0.880 1.025 0.947 0.880 1.025 0.929 0.880 V Single-Ended Output Low Voltage VOL Figure 2 VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC 1.830 1.707 1.555 1.810 1.685 1.620 1.810 1.690 1.620 V VOH VOL Figure 2 Differential Output Voltage 600 640 660 mV REFERENCE OUTPUT (VBB) Reference Voltage Output VBB IBB = ±0.5mA (Note 4) IEE (Note 5) VCC 1.38 VCC - VCC 1.322 1.26 VCC - VCC - VCC 1.38 1.330 1.26 VCC 1.38 VCC - VCC 1.335 1.26 V SUPPLY Supply Current 15 24 17 24 19 24 mA _______________________________________________________________________________________ 3 MAX9384 DC ELECTRICAL CHARACTERISTICS (continued) MAX9384 ECL/PECL Dual Differential 2:1 Multiplexer AC ELECTRICAL CHARACTERISTICS (VCC - VEE = 3.0V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V, VIHD - VILD = 0.15V to 1V, fIN ≤ 500MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%). Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Note 6) PARAMETER CONDITIONS -40°C MIN TYP +25°C MAX MIN TYP +85°C MAX MIN TYP MAX UNITS Differential Input-to-Output Delay tPLHD, tPHLD Figure 2 340 540 350 550 360 560 ps Single-Ended Input-to-Output Delay tPLH1, tPHL1 Figure 3 (Note 7) 290 540 310 560 330 580 ps SEL_ and COM_SEL to Output Delay tPLH2, tPHL2 Figure 4 (Note 7) 310 730 320 740 330 750 ps Output-to-Output Skew tSKOO (Note 8) 12 40 12 40 12 40 ps Added Random Jitter tRJ fIN = 500MHz (Note 9) 0.3 0.8 0.4 0.8 0.5 0.8 ps(RMS) tDJ 1.0Gbps 223 - 1 PRBS pattern (Note 9) 40 70 40 70 40 70 ps(P-P) Switching Frequency fMAX VOH - VOL ≥ 300mV, Figure 2 1.5 Output Rise and Fall Time (20% to 80%) tR , tF Figure 2 200 Added Deterministic Jitter Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: 4 SYMBOL 1.5 310 440 200 1.5 310 440 200 GHz 310 440 ps Measurements are made with the device in thermal equilibrium. Current into a pin is defined as positive. Current out of a pin is defined as negative. DC parameters production tested at TA = +25°C and guaranteed by design over the full operating temperature range. Use VBB only for inputs that are on the same device as the VBB reference. All pins open except VCC and VEE. Guaranteed by design and characterization. Limits are set at ±6 sigma. Test conditions are VIH = VCC - 1.11V and VIL = VCC - 1.53V. Measured between outputs of the same part at the signal crossing points for a same-edge transition. Differential input signal. Device jitter added to the input signal. Differential input signal. _______________________________________________________________________________________ ECL/PECL Dual Differential 2:1 Multiplexer DIFFERENTIAL OUTPUT EYE PATTERN AT 1Gbps, PRBS 223 - 1, NRZ DATA PATTERN Q_ - Q_ 200mV/div MAX9384 toc03 25.0 22.5 SUPPLY CURRENT (mA) Q_ - Q_ 200mV/div SUPPLY CURRENT (IEE) vs. TEMPERATURE MAX9384 toc02 MAX9384 toc01 DIFFERENTIAL OUTPUT EYE PATTERN AT 500Mbps, PRBS 223 - 1, NRZ DATA PATTERN 20.0 17.5 15.0 12.5 10.0 200ps/div 300ps/div -40 -15 10 35 60 85 TEMPERATURE (°C) 500 325 TRANSITION TIME (ps) 600 tR tF 300 300 200 400 600 800 1000 1200 1400 1600 FREQUENCY (MHz) tPLHD 375 tPHLD 275 250 0 425 325 275 400 475 MAX9384 toc05 700 350 TRANSITION TIME (ps) DIFFERENTIAL OUTPUT VOLTAGE VILD = 0.5V MAX9384 toc04 800 DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE TRANSITION TIME vs. TEMPERATURE MAX9384 toc06 OUTPUT AMPLITUDE (VOH - VOL) vs. FREQUENCY -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX9384 Typical Operating Characteristics (VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, COM_SEL = low, SEL_ = low, outputs loaded with 50Ω ±1% to VCC - 2V, fIN = 500MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.) ECL/PECL Dual Differential 2:1 Multiplexer MAX9384 Pin Description PIN NAME FUNCTION 1 D0a Noninverting Differential Input a for MUX 0. Internal 120kΩ pulldown to VEE. 2 D0a Inverting Differential Input a for MUX 0. Internal 120kΩ pulldown to VEE and 120kΩ pullup to VCC. 3 VBB0 Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a reference for single-ended operation. When used, bypass VBB0 to VCC with a 0.01µF ceramic capacitor. Otherwise leave open. VBB0 is internally connected to VBB1. 4 D0b Noninverting Differential Input b for MUX 0. Internal 120kΩ pulldown to VEE. 5 D0b Inverting Differential Input b for MUX 0. Internal 120kΩ pulldown to VEE and 120kΩ pullup to VCC. 6 D1a Noninverting Differential Input a for MUX 1. Internal 120kΩ pulldown to VEE. 7 D1a Inverting Differential Input a for MUX 1. Internal 120kΩ pulldown to VEE and 120kΩ pullup to VCC. 8 VBB1 Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a reference for single-ended operation. When used, bypass VBB1 to VCC with a 0.01µF ceramic capacitor. Otherwise leave open. VBB1 is internally connected to VBB0. 9 D1b Noninverting Differential Input b for MUX 1. Internal 120kΩ pulldown to VEE. 10 D1b Inverting Differential Input b for MUX 1. Internal 120kΩ pulldown to VEE and 120kΩ pullup to VCC. 11 VEE Negative Supply Voltage 12 Q1 Inverting Output for MUX 1. Typically terminate with 50Ω resistor to VCC - 2V. 13 Q1 Noninverting Output for MUX 1. Typically terminate with 50Ω resistor to VCC - 2V. 14, 20 VCC Positive Supply Voltage. Bypass each VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. SEL1 Select Logic Input for MUX 1. Internal 210kΩ pulldown to VEE. 15 16 COM_SEL Common Select Logic Input. Internal 210kΩ pulldown to VEE. 17 SEL0 Select Logic Input for MUX 0. Internal 210kΩ pulldown to VEE. 18 Q0 Inverting Output for MUX 0. Typically terminate with 50Ω resistor to VCC - 2V. 19 Q0 Noninverting Output for MUX 0. Typically terminate with 50Ω resistor to VCC - 2V. VCC VCC VIHD (MAX) VIHD - VILD VIH VILD (MAX) VBB VIL VIHD (MIN) VIHD - VILD VILD (MIN) VEE VEE DIFFERENTIAL INPUT VOLTAGE DEFINITION SINGLE-ENDED INPUT VOLTAGE DEFINITION Figure 1. Input Definitions 6 _______________________________________________________________________________________ ECL/PECL Dual Differential 2:1 Multiplexer MAX9384 VIHD D_ VIHD - VILD VILD D_ tPLHD tPHLD VOH Q_ VOH - VOL VOL Q_ 80% 80% VOH - VOL 0V (DIFFERENTIAL) DIFFERENTIAL OUTPUT WAVEFORM VOH - VOL 20% 20% Q_ - Q_ tR tF Figure 2. Differential Input-to-Output Propagation Delay Timing Diagram VIH D_ WHEN D_ = VBB VBB OR VBB VIL D_ WHEN D_ = VBB tPLH1 tPHL1 VOH Q_ VOH - VOL VOL Q_ Figure 3. Single-Ended Input-to-Output Propagation Delay Timing Delay _______________________________________________________________________________________ 7 MAX9384 ECL/PECL Dual Differential 2:1 Multiplexer VIHD D_a AND D_b VIHD - VILD VILD D_a AND D_b VIH VBB SEL_ WHEN COM_SEL = LOW OR COM_SEL WHEN SEL_ = LOW VIL tPLH2 tPHL2 VOH Q_ VOH - VOL VOL Q_ Figure 4. Select Inputs (COM_SEL, SEL_) to Output (Q_, Q_) Delay Timing Diagram Detailed Description The MAX9384 dual differential 2:1 multiplexer features extremely low propagation delay (560ps max) and outputto-output skew (40ps max). These features make the device ideal for clock and data multiplexing applications. The two differential muxes are controlled individually or simultaneously through select control inputs, SEL0, SEL1, and COM_SEL (see Table 1). The select control inputs are referenced to VBB (nominally VCC - 1.33V) and are internally pulled down to VEE through 210kΩ resistors. By default, the select inputs are low when left open. The differential inputs D_, D_ can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference voltage VBB. The reference output voltage, pins VBB0 and VBB1, provides the input reference voltage for singleended operation for each mux. A single-ended input of at least VBB_ ±95mV or a differential input of at least 95mV switches the outputs to the VOH and VOL levels Table 1. Input Select Truth Table CONTROL INPUT DATA INPUT COM_SEL SEL_ D_ , D_ L or open b* L or open H a H X a *Default input when COM_SEL and SEL_ are left open. 8 specified in the DC Electrical Characteristics. The maximum magnitude of the differential input from D_ to D_ is ±3.0V. Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously. The device operates over a wide supply range (VCC VEE) of +3.0V to +5.5V for PECL or -3.0V to -5.5V for ECL, and is pin compatible with the MC100LVEL56 and MC100EL56. Single-Ended Operation A single-ended input can be driven to VCC and VEE or by a single-ended LVPECL/LVECL signal. D_, D_ are differential inputs but can be configured to accept single-ended inputs. This is accomplished by connecting the on-chip reference voltage, VBB_, to an unused complementary input as a reference. For example, the differential D0a, D0a input is converted to a noninverting, single-ended input by connecting V BB0 to D0a and connecting the single-ended input to D0a. Similarly, an inverting input is obtained by connecting VBB0 to D0a and connecting the single-ended input to D0a. When using the VBB_ reference output, bypass it with a 0.01µF ceramic capacitor to VCC. If not used, leave it open. The VBB_ reference can source or sink 0.5mA, which is sufficient to drive two inputs. _______________________________________________________________________________________ ECL/PECL Dual Differential 2:1 Multiplexer Output Termination Terminate the outputs through 50Ω to VCC - 2V or use equivalent Thevenin terminations. Terminate each Q_ and Q_ output with identical termination on each for minimal distortion. When a single-ended signal is taken from the differential output, terminate both Q_ and Q_. Ensure that output currents do not exceed the current limits as specified in the Absolute Maximum Ratings table. Under all operating conditions, the device’s total thermal limits should be observed. Supply Bypassing Bypass each VCC to VEE with high-frequency surfacemount ceramic 0.1µF and 0.01µF capacitors. Place the capacitors as close to the device as possible, with the 0.01µF capacitor closest to the device pins. Use multiple vias when connecting the bypass capacitors to ground. When using the VBB0 or VBB1 reference outputs, bypass each one with a 0.01µF ceramic capacitor to VCC. If the VBB0 or VBB1 reference outputs are not used, they can be left open. Traces Circuit board trace layout is very important to maintain the signal integrity of high-speed differential signals. Maintaining integrity is accomplished in part by reducing signal reflections and skew, and increasing common-mode noise immunity. Signal reflections are caused by discontinuities in the 50Ω characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, not using sharp corners or using vias. Maintaining distance between the traces also increases common-mode noise immunity. Reducing signal skew is accomplished by matching the electrical length of the differential traces. Chip Information TRANSISTOR COUNT: 485 PROCESS: Bipolar Functional Diagram VCC 120kΩ D0a D0a Q0 MUX 0 D0b Q0 D0b VCC 120kΩ VEE 120kΩ D1a D1a Q1 MUX 1 D1b Q1 D1b 120kΩ VEE SEL0 COM_SEL SEL1 210kΩ MAX9384 VEE _______________________________________________________________________________________ 9 MAX9384 Applications Information Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) SOICW.EPS MAX9384 ECL/PECL Dual Differential 2:1 Multiplexer Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.