MAXIM MAX9311EGJ

19-2078; Rev 2; 10/02
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
The MAX9311/MAX9313 are low-skew, 1-to-10 differential drivers designed for clock and data distribution.
These devices allow selection between two inputs. The
selected input is reproduced at 10 differential outputs.
The differential inputs can be adapted to accept singleended inputs by connecting the on-chip VBB supply to
one input as a reference voltage.
The MAX9311/MAX9313 feature low part-to-part skew
(30ps) and output-to-output skew (12ps), making them
ideal for clock and data distribution across a backplane
or a board. For interfacing to differential HSTL and
LVPECL signals, these devices operate over a +2.25V
to +3.8V supply range, allowing high-performance clock
or data distribution in systems with a nominal +2.5V or
+3.3V supply. For differential LVECL operation, these
devices operate from a -2.25V to -3.8V supply.
The MAX9311 features an on-chip VBB reference output
of 1.425V below the positive supply voltage. The
MAX9313 offers an on-chip V BB reference output of
1.32V below the positive supply voltage.
Both devices are offered in space-saving, 32-pin 5mm ✕
5mm TQFP, 5mm x 5mm QFN, and industry-standard
32-pin 7mm x 7mm LQFP packages.
Applications
Precision Clock Distribution
Low-Jitter Data Repeater
Features
♦ +2.25V to +3.8V Differential HSTL/LVPECL
Operation
♦ -2.25V to -3.8V LVECL Operation
♦ 30ps (typ) Part-to-Part Skew
♦ 12ps (typ) Output-to-Output Skew
♦ 312ps (typ) Propagation Delay
♦ ≥ 300mV Differential Output at 3GHz
♦ On-Chip Reference for Single-Ended Inputs
♦ Output Low with Open Input
♦ Pin Compatible with MC100LVEP111 (MAX9311)
and MC100EP111 (MAX9313)
♦ Offered in Tiny QFN* Package (70% Smaller
Footprint than LQFP)
Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
MAX9311ECJ
-40°C to +85°C
32 LQFP (7mm ✕ 7mm)
MAX9311EGJ*
-40°C to +85°C
32 QFN (5mm ✕ 5mm)
MAX9311EHJ*
-40°C to +85°C
32 TQFP (5mm ✕ 5mm)
MAX9313ECJ
-40°C to +85°C
32 LQFP (7mm ✕ 7mm)
MAX9313EGJ*
-40°C to +85°C
32 QFN (5mm ✕ 5mm)
MAX9313EHJ*
-40°C to +85°C
32 TQFP (5mm ✕ 5mm)
*Future product—contact factory for availability.
Pin Configuration
TOP VIEW
VCC Q0
Q0
Q1
Q1
Q2
Q2
VCC
32
30
29
28
27
26
25
31
VCC
1
24 Q3
CLKSEL
2
23 Q3
CLK0
3
22 Q4
CLK0
4
VBB
LQFP (7mm × 7mm), TQFP (5mm × 5mm),
QFN (NO LEADS EXTENDING FROM QFN PACKAGE)
MAX9311/MAX9313
21 Q4
MAX9311
MAX9313
5
20 Q5
CLK1
6
19 Q5
CLK1
7
18 Q6
VEE
8
17 Q6
10
11
12
13
14
15
16
VCC Q9
Q9
Q8
Q8
Q7
Q7
VCC
9
CLKSEL
CLK0, CLK0 CLK1, CLK1
0
ON
OFF
1
OFF
ON
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX9311/MAX9313
General Description
MAX9311/MAX9313
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
ABSOLUTE MAXIMUM RATINGS
VCC - VEE...............................................................................4.1V
Inputs (CLK_, CLK_, CLKSEL)..............VEE - 0.3V to VCC + 0.3V
CLK_ to CLK_ ....................................................................±3.0V
Continuous Output Current .................................................50mA
Surge Output Current........................................................100mA
VBB Sink/Source Current ...............................................±0.65mA
Junction-to-Ambient Thermal Resistance in Still Air
7mm x 7mm LQFP .....................................................+90°C/W
Junction-to-Ambient Thermal Resistance with
500 LFPM Airflow
7mm x 7mm LQFP .....................................................+60°C/W
Junction-to-Case Thermal Resistance
7mm x 7mm LQFP .....................................................+12°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (CLKSEL, CLK_, CLK_,
Q_, Q_, VBB).......................................................................2kV
Soldering Temperature (10s) ...........................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = +2.25V to +3.8V, outputs loaded with 50Ω ±1% to VCC - 2V, CLKSEL = high or low, unless otherwise noted.) (Notes 1–4)
PARAMETER
SYMBOL
CONDITIONS
-40°C
+25°C
+85°C
MIN
MAX
MIN
MAX
MIN
MAX
MAX9311
VCC
- 1.23
VCC
VCC
- 1.23
VCC
VCC
- 1.23
VCC
MAX9313
VCC
- 1.165
VCC
VCC
- 1.165
VCC
VCC
- 1.165
VCC
MAX9311
VEE
VCC
- 1.62
VEE
VCC
- 1.62
VEE
VCC
- 1.62
VEE
VCC
- 1.475
VEE
VCC
- 1.475
VEE
VCC
- 1.475
UNITS
SINGLE-ENDED INPUT (CLKSEL)
Input High
Voltage
Input Low
Voltage
VIH
VIL
Input High
Current
IIH
Input Low
Current
IIL
Internal
VBB
threshold
Internal
VBB
threshold
V
MAX9313
150
150
V
150
µA
µA
-10
+10
-10
+10
-10
+10
VCC
- 1.23
VCC
VCC
- 1.23
VCC
VCC
- 1.23
VCC
DIFFERENTIAL INPUTS (CLK_, CLK_)
Single-Ended
Input High
Voltage
2
VIH
VBB
connected MAX9311
to CLK_
(VIL for VBB
connected
MAX9313
to CLK_),
Figure 1
V
VCC
- 1.165
VCC
VCC
- 1.165
VCC
VCC
- 1.165
_______________________________________________________________________________________
VCC
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
MAX9311/MAX9313
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = +2.25V to +3.8V, outputs loaded with 50Ω ±1% to VCC - 2V, CLKSEL = high or low, unless otherwise noted.) (Notes 1–4)
PARAMETER
SYMBOL
CONDITIONS
VIL
VBB
connected MAX9311
to CLK_
(VIH for VBB
connected
MAX9313
to CLK_),
Figure 1
Single-Ended
Input Low
Voltage
-40°C
+25°C
+85°C
MIN
MAX
MIN
MAX
MIN
MAX
VEE
VCC
- 1.62
VEE
VCC
- 1.62
VEE
VCC
-1.62
UNITS
V
VEE
VCC
- 1.475
VEE
VCC
- 1.475
VEE
VCC
-1.475
High Voltage
of Differential
Input
VIHD
VEE +1.2
VCC
VEE + 1.2
VCC
VEE +1.2
VCC
V
Low Voltage
of Differential
Input
VILD
VEE
VCC
- 0.095
VEE
VCC
- 0.095
VEE
VCC
- 0.095
V
Differential
Input Voltage
VIHD VILD
0.095
VCC
- VEE
0.095
VCC
- VEE
0.095
VCC
- VEE
3.0
0.095
3.0
0.095
Input High
Current
For VCC - VEE < 3.0V
For VCC - VEE ≥ 3.0V
0.095
150
IIH
CLK_ Input Low
Current
IILCLK
-10
CLK_ Input Low
Current
IILCLK
-150
+10
150
-10
+10
-150
-10
V
3.0
150
µA
+10
µA
-150
µA
OUTPUTS (Q_, Q_)
Single-Ended
Output High
Voltage
VOH
Figure 1
VCC
- 1.025
VCC
- 0.900
VCC
- 1.025
VCC
- 0.900
VCC
- 1.025
VCC
- 0.900
V
Single-Ended
Output Low
Voltage
VOL
Figure 1
VCC
- 1.93
VCC
- 1.695
VCC
- 1.93
VCC
- 1.695
VCC
- 1.93
VCC
- 1.695
V
VOH VOL
Figure 1
670
950
670
950
670
950
mV
MAX9311
VCC
- 1.525
VCC
- 1.325
VCC
- 1.525
VCC
- 1.325
VCC
- 1.525
VCC
- 1.325
MAX9313
VCC
- 1.38
VCC
- 1.26
VCC
- 1.38
VCC
- 1.26
VCC
- 1.38
VCC
- 1.26
Differential
Output Voltage
REFERENCE (VBB)
Reference
Voltage Output
(Note 5)
VBB
IBB =
±0.5mA
V
POWER SUPPLY
Supply Current
(Note 6)
IEE
75
82
95
mA
_______________________________________________________________________________________
3
MAX9311/MAX9313
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.25V to 3.8V, outputs loaded with 50Ω ±1% to VCC - 2V, input frequency = 1.5GHz, input transition time = 125ps
(20% to 80%), CLKSEL = high or low, VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to the smaller of 3V or
VCC - VEE, unless otherwise noted. Typical values are at VCC - VEE = 3.3V, VIHD = VCC -1V, VILD = VCC -1.5V.) (Note 7)
PARAMETER
SYMBOL CONDITIONS
-40°C
+25°C
+85°C
UNITS
MIN
TYP
MAX
MIN
TYP
MA
MIN
TYP
MAX
220
321
380
220
312
410
260
322
400
ps
Differential
Input-toOutput Delay
tPLHD,
tPHLD
Output-toOutput Skew
(Note 8)
tSKOO
12
46
12
46
10
35
ps
Part-to-Part
Skew (Note 9)
tSKPP
30
160
30
190
30
140
ps
fIN = 1.5GHz,
Clock pattern
1.2
2.5
1.2
2.5
fIN = 3.0GHz,
Clock pattern
1.2
2.6
1.2
2.6
1.2
2.6
3Gbps,
223 -1 PRBS
pattern
80
95
80
95
80
95
Added
Random Jitter
(Note 10)
tRJ
Added
Deterministic
Jitter (Note 10)
tDJ
Switching
Frequency
Output
Rise/Fall Time
(20% to 80%)
Figure 2
VOH - VOL ≥
350mV, Clock
pattern,
Figure 2
fMAX
tR , t F
1.2
2.5
ps
(RMS)
2.0
2.0
3.0
ps
(p-p)
2.0
GHz
VOH - VOL ≥
500mV, Clock
pattern,
Figure 2
1.5
Figure 2
100
1.5
112
140
100
1.5
116
140
100
121
140
ps
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: Single-ended input operation using VBB is limited to VCC - VEE = 3.0V to 3.8V for the MAX9311 and VCC - VEE = 2.7V to 3.8V
for the MAX9313.
Note 4: DC parameters production tested at TA = +25°C. Guaranteed by design and characterization over the full operating temperature range.
Note 5: Use VBB only for inputs that are on the same device as the VBB reference.
Note 6: All pins open except VCC and VEE.
Note 7: Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 8: Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 9: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge
transition.
Note 10:Device jitter added to the input signal.
4
_______________________________________________________________________________________
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
OUTPUT AMPLITUDE (VOH - VOL)
vs. FREQUENCY
70
65
60
MAX9311 toc02
130
0.7
125
TRANSITION TIME (ps)
OUTPUT AMPLITUDE (V)
0.8
75
0.6
0.5
0.4
0.3
tR
120
115
tF
110
0.2
105
55
0.1
50
0
10
35
60
85
100
0
1000
TEMPERATURE (°C)
2000
3000
VIHD - VILD = 150mV
360
340
PROPAGATION DELAY (ps)
tPLHD
310
309
308
307
tPHLD
306
10
35
60
85
PROPAGATION DELAY
vs. TEMPERATURE
313
311
-15
TEMPERATURE (°C)
PROPAGATION DELAY
vs. HIGH VOLTAGE OF
DIFFERENTIAL INPUT (VIHD)
312
-40
FREQUENCY (MHz)
305
MAX9311 toc05
-15
MAX9311 toc04
-40
PROPAGATION DELAY (ps)
SUPPLY CURRENT (mA)
80
TRANSITION TIME vs. TEMPERATURE
0.9
MAX9311 toc01
85
MAX9311 toc03
SUPPLY CURRENT (IEE)
vs. TEMPERATURE
tPLHD
320
300
tPHLD
280
260
VIHD = VCC - 0.95V
VILD = VCC - 1.1V
240
220
304
303
200
1.0
1.4
1.8
2.2
2.6
VIHD (V)
3.0
3.4
3.8
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
5
MAX9311/MAX9313
Typical Operating Characteristics
(VCC = +3.3V, VEE = 0, VIHD = VCC - 0.95V, VILD = VCC - 1.25V, input transition time = 125ps (20% to 80%), fIN = 1.5GHz, outputs
loaded with 50Ω to VCC - 2V, TA = +25°C, unless otherwise noted.)
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
MAX9311/MAX9313
Pin Description
PIN
6
NAME
FUNCTION
1, 9, 16,
25, 32
VCC
Positive Supply Voltage. Bypass from VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
2
CLKSEL
Clock Select Input (Single-Ended). Drive low to select the CLK0, CLK0 input. Drive high to select the
CLK1, CLK1 input. The CLKSEL threshold is VBB. If CLKSEL is not driven by a logic signal, use a 1kΩ
pulldown to VEE to select CLK0, CLK0, or a 1kΩ pullup to VCC to select CLK1, CLK1.
3
CLK0
Noninverting Differential Clock Input 0. Internal 75kΩ pulldown resistor.
4
CLK0
Inverting Differential Clock Input 0. Internal 75kΩ pullup and pulldown resistors.
5
VBB
Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a reference for
single-ended operation. When used, bypass with a 0.01µF ceramic capacitor to VCC; otherwise, leave open.
6
CLK1
Noninverting Differential Clock Input 1. Internal 75kΩ pulldown resistor.
7
CLK1
Inverting Differential Clock Input 1. Internal 75kΩ pullup and pulldown resistors.
8
VEE
10
Q9
Negative Supply Voltage
Inverting Q9 Output. Typically terminate with 50Ω resistor to VCC - 2V.
11
Q9
Noninverting Q9 Output. Typically terminate with 50Ω resistor to VCC - 2V.
12
Q8
Inverting Q8 Output. Typically terminate with 50Ω resistor to VCC - 2V.
13
Q8
Noninverting Q8 Output. Typically terminate with 50Ω resistor to VCC - 2V.
14
Q7
Inverting Q7 Output. Typically terminate with 50Ω resistor to VCC - 2V.
15
Q7
Noninverting Q7 Output. Typically terminate with 50Ω resistor to VCC - 2V.
17
Q6
Inverting Q6 Output. Typically terminate with 50Ω resistor to VCC - 2V.
18
Q6
Noninverting Q6 Output. Typically terminate with 50Ω resistor to VCC - 2V.
19
Q5
Inverting Q5 Output. Typically terminate with 50Ω resistor to VCC - 2V.
20
Q5
Noninverting Q5 Output. Typically terminate with 50Ω resistor to VCC - 2V.
21
Q4
Inverting Q4 Output. Typically terminate with 50Ω resistor to VCC - 2V.
22
Q4
Noninverting Q4 Output. Typically terminate with 50Ω resistor to VCC - 2V.
23
Q3
Inverting Q3 Output. Typically terminate with 50Ω resistor to VCC - 2V.
24
Q3
Noninverting Q3 Output. Typically terminate with 50Ω resistor to VCC - 2V.
26
Q2
Inverting Q2 Output. Typically terminate with 50Ω resistor to VCC - 2V.
27
Q2
Noninverting Q2 Output. Typically terminate with 50Ω resistor to VCC - 2V.
28
Q1
Inverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.
29
Q1
Noninverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.
30
Q0
Inverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.
31
Q0
Noninverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.
_______________________________________________________________________________________
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
The MAX9311/MAX9313 are low skew, 1-to-10 differential drivers designed for clock and data distribution.
A 2:1 mux selects between the two differential inputs,
CLK0, CLK0 and CLK1, CLK1. The 2:1 mux is switched
by the single-ended CLKSEL input. A logic low selects
the CLK0, CLK0 input. A logic high selects the CLK1,
CLK1 input. The logic threshold for CLKSEL is set by an
internal VBB voltage reference. The CLKSEL input can
be driven to VCC and VEE or by a single-ended LVPECL/
LVECL signal. The selected input is reproduced at 10
differential outputs.
For interfacing to differential HSTL and LVPECL signals,
these devices operate over a +2.25V to +3.8V supply
range, allowing high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply.
For differential LVECL operation, these devices operate
from a -2.25V to -3.8V supply.
The differential inputs can be configured to accept single-ended inputs when operating at approximately VCC VEE = +3.0V to +3.8V for the MAX9311 or VCC - VEE =
+2.7V to +3.8V for the MAX9313. This is accomplished
by connecting the on-chip reference voltage, VBB, to an
input as a reference. For example, the differential CLK0,
CLK0 input is converted to a noninverting, single-ended
input by connecting VBB to CLK0 and connecting the
single-ended input to CLK0. Similarly, an inverting input
is obtained by connecting VBB to CLK0 and connecting
the single-ended input to CLK0. With a differential input
configured as single-ended (using V BB), the singleended input can be driven to VCC and VEE or with a single-ended LVPECL/LVECL signal.
When a differential input is configured as a single-ended
input (using VBB), the approximate supply range is VCC VEE = +3.0V to +3.8V for the MAX9311 and VCC - VEE =
+2.7V to +3.8V for the MAX9313. This is because one of
the inputs must be VEE + 1.2V or higher for proper operation of the input stage. VBB must be at least VEE + 1.2V
because it becomes the high-level input when the other
(single-ended) input swings below it. Therefore, minimum VBB = VEE + 1.2V.
The minimum VBB output for the MAX9311 is VCC 1.525V and the minimum VBB output for the MAX9313 is
VCC - 1.38V. Substituting the minimum VBB output for
each device into VBB = VEE + 1.2V results in a minimum
supply of 2.725V for the MAX9311 and 2.58V for the
MAX9313. Rounding up to standard supplies gives the
single-ended operating supply ranges of VCC - VEE =
3.0V to 3.8V for the MAX9311 and VCC - VEE = 2.7V to
3.8V for the MAX9313.
When using the VBB reference output, bypass it with a
0.01µF ceramic capacitor to VCC. If the VBB reference is
not used, it can be left open. The VBB reference can
source or sink 0.5mA, which is sufficient to drive two
inputs. Use VBB only for inputs that are on the same
device as the VBB reference.
The maximum magnitude of the differential input from
CLK_ to CLK_ is 3.0V or VCC - VEE, whichever is less.
This limit also applies to the difference between any reference voltage input and a single-ended input.
The differential inputs have bias resistors that drive the
outputs to a differential low when the inputs are open.
The inverting inputs (CLK0 and CLK1) are biased with a
75kΩ pullup to VCC and a 75kΩ pulldown to VEE. The
noninverting inputs (CLK0 and CLK1) are biased with a
75kΩ pulldown to VEE. The single-ended CLKSEL input
does not have a bias resistor. If not driven, pull CLKSEL
up or down with a 1kHz resistor (see Pin Description).
Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously (VILD cannot be
higher than VIHD).
Output levels are referenced to VCC and are considered
LVPECL or LVECL, depending on the level of the VCC
supply. With VCC connected to a positive supply and
VEE connected to GND, the outputs are LVPECL. The
outputs are LVECL when VCC is connected to GND and
VEE is connected to a negative supply.
A single-ended input of at least VBB ±95mV or a differential input of at least 95mV switches the outputs to the
V OH and V OL levels specified in the DC Electrical
Characteristics table.
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount
ceramic 0.1µF and 0.01µF capacitors in parallel as close
to the device as possible, with the 0.01µF value capacitor closest to the device. Use multiple parallel vias for
low inductance. When using the VBB reference output,
bypass it with a 0.01µF ceramic capacitor to VCC (if the
VBB reference is not used, it can be left open).
Traces
Input and output trace characteristics affect the performance of the MAX9311/MAX9313. Connect each signal
of a differential input or output to a 50Ω characteristic
impedance trace. Minimize the number of vias to prevent
impedance discontinuities. Reduce reflections by maintaining the 50Ω characteristic impedance through connectors and across cables. Reduce skew within a
_______________________________________________________________________________________
7
MAX9311/MAX9313
Detailed Description
MAX9311/MAX9313
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
differential pair by matching the electrical length of the
traces.
Chip Information
TRANSISTOR COUNT: 250
Output Termination
Terminate outputs through 50Ω to VCC - 2V or use an
equivalent Thevenin termination. When a single-ended
signal is taken from a differential output, terminate both
outputs. For example, if Q0 is used as a single-ended
output, terminate both Q0 and Q0.
CLK_
VIH
VBB
CLK_
VIL
(CONNECTED TO CLK_)
VOH
Q_
VOH - VOL
VOL
Q_
Figure 1. Switching with Single-Ended Input
CLK_
VIHD
VIHD - VILD
VILD
CLK_
tPLHD
tPHLD
VOH
Q_
VOH - VOL
Q_
VOL
80%
80%
0 (DIFFERENTIAL)
(Q_) - (Q_)
0 (DIFFERENTIAL)
20%
20%
tR
tF
Figure 2. Differential Transition Time and Propagation Delay Timing Diagram
8
_______________________________________________________________________________________
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
Q0
Q0
VCC
Q1
Q1
75kΩ
Q2
CLK0
Q2
CLK0
Q3
75kΩ
75kΩ
Q3
VEE
Q4
VEE
0
VCC
1
Q4
Q5
Q5
75kΩ
Q6
CLK1
Q6
CLK1
Q7
75kΩ
75kΩ
Q7
VEE
CLKSEL
VEE
Q8
Q8
VBB
Q9
Q9
_______________________________________________________________________________________
9
MAX9311/MAX9313
Functional Diagram
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
32L/48L TQFP EPS
MAX9311/MAX9313
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
10
______________________________________________________________________________________
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
32L TQFP, 5x5x01.0.EPS
______________________________________________________________________________________
11
MAX9311/MAX9313
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
32L QFN.EPS
MAX9311/MAX9313
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.