ETC UPD16708

PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
µ PD16708
300-OUTPUT TFT-LCD GATE DRIVER
DESCRIPTION
The µ PD16708 is a TFT-LCD gate driver equipped with 300-output lines. It can output a high-gate scanning
voltage in response to CMOS level input because it provided with a level-shift circuit inside the IC circuit.
FEATURES
• CMOS level input (2.3 to 3.6 V)
• 300 outputs + 2 pins (Fixed to VEE)
• High-withstanding-voltage output (VDD2 to VEE = amplitude: 40 V MAX.)
• COG mounting possible
ORDERING INFORMATION
Part Number
Package
µ PD16708P
Chip
Remark Purchasing the above chip entails the exchange of documents such as a separate memorandum or product
quality, so please contact one of our sales representatives.
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
Not all products and/or types are availabe in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16071EJ6V0PM00 (6th edition)
Date Published January 2003 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
2002
µ PD16708
★ 1. BLOCK DIAGRAM
VDD2
VDD1
VSS
R,/L
CLK
STVR
SR1
SR2
SR3
300-bit shift resister
STVL
SR298 SR299 SR300
/OE
/AO
PASS
LS2 Note LS2 Note LS2 Note
LS2 Note LS2 Note LS2 Note
VEE
VEE level
O0
VEE level
O1
O2
O3
O298
Note LS2 shifts CMOS level and output level (VDD2 to VEE).
Remark /xxx indicates active low signal.
2
Preliminary Product Information S16071EJ6V0PM
O299
O300
O301
µ PD16708
2. PIN CONFIGURATION (Bump Surface)
1
463
159
Y (+)
Input side
X (+)
Output side
Input side
137
23
• Chip size: (1.14 ± 0.02) x (18.03 ± 0.02) mm (After sawing)
2
• Alignment mark coordinate (mark center, unit: µm)
X
Y
Shape of alignment mark
−8545
−400
Type A
8545
−400
Type B
Refer to the figure below for more detail.
• Alignment mark
Type A
Type B
30 µm 30 µm 30 µm
30 µm 30 µm 30 µm
(−8545, −400)
30 µm
30 µm
30 µm
30 µm
30 µm
30 µm
(8545, −400)
Preliminary Product Information S16071EJ6V0PM
3
µ PD16708
Table 2−
−1. Pad Coordinate (1/5)
PAD No. PAD Name
1
PASS
2
PASS
3
VEE
4
VEE
5
VEE
6
VEE
7
VEE
8
VEE
9
/OE
10
/OE
11
/AO
12
/AO
13
VDD2
14
VDD2
15
VDD1
16
VDD1
17
R,/L
18
R,/L
19
VSS
20
VSS
21
CLK
22
CLK
23
STVL
24
STVL
25
DUMMY
26
DUMMY
27
DUMMY
28
DUMMY
29
DUMMY
30
DUMMY
31
DUMMY
32
DUMMY
33
DUMMY
34
DUMMY
35
DUMMY
36
DUMMY
37
DUMMY
38
DUMMY
39
DUMMY
40
DUMMY
41
DUMMY
42
DUMMY
43
DUMMY
44
DUMMY
45
DUMMY
46
DUMMY
47
DUMMY
48
DUMMY
49
DUMMY
50
DUMMY
4
X[µm]
-8849.0
-8779.0
-8849.0
-8779.0
-8849.0
-8779.0
-8849.0
-8779.0
-8849.0
-8779.0
-8849.0
-8779.0
-8849.0
-8779.0
-8849.0
-8779.0
-8849.0
-8779.0
-8849.0
-8779.0
-8849.0
-8779.0
-8849.0
-8779.0
-8415.0
-7722.0
-7618.0
-7514.0
-7410.0
-7306.0
-7202.0
-7098.0
-6994.0
-6890.0
-6786.0
-6682.0
-6578.0
-6474.0
-6370.0
-6266.0
-6162.0
-6058.0
-5954.0
-5850.0
-5746.0
-5642.0
-5538.0
-5434.0
-5330.0
-5226.0
Y[µm]
409.0
409.0
334.0
334.0
259.0
259.0
184.0
184.0
109.0
109.0
34.0
34.0
-41.0
-41.0
-116.0
-116.0
-191.0
-191.0
-266.0
-266.0
-341.0
-341.0
-416.0
-416.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
Bump Size (X:Y)[µm]
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
PAD No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PAD Name
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
Preliminary Product Information S16071EJ6V0PM
X[µm]
-5122.0
-5018.0
-4914.0
-4810.0
-4706.0
-4602.0
-4498.0
-4394.0
-4290.0
-2106.0
-2002.0
-1898.0
-1794.0
-1690.0
-1586.0
-1482.0
-1378.0
-1274.0
-1170.0
-1066.0
-962.0
-858.0
-754.0
-650.0
-546.0
-442.0
-338.0
-234.0
-130.0
-26.0
78.0
182.0
286.0
390.0
494.0
598.0
702.0
806.0
910.0
1014.0
1118.0
1222.0
1326.0
1430.0
1534.0
1638.0
1742.0
1846.0
1950.0
2054.0
Y[µm]
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
Bump Size (X:Y)[µm]
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
µ PD16708
Table 2−
−1. Pad Coordinate (2/5)
PAD No. PAD Name
101
DUMMY
102
DUMMY
103
DUMMY
104
DUMMY
105
DUMMY
106
DUMMY
107
DUMMY
108
DUMMY
109
DUMMY
110
DUMMY
111
DUMMY
112
DUMMY
113
DUMMY
114
DUMMY
115
DUMMY
116
DUMMY
117
DUMMY
118
DUMMY
119
DUMMY
120
DUMMY
121
DUMMY
122
DUMMY
123
DUMMY
124
DUMMY
125
DUMMY
126
DUMMY
127
DUMMY
128
DUMMY
129
DUMMY
130
DUMMY
131
DUMMY
132
DUMMY
133
DUMMY
134
DUMMY
135
DUMMY
136
STVR
137
STVR
138
CLK
139
CLK
140
VSS
141
VSS
142
R,/L
143
R,/L
144
VDD1
145
VDD1
146
VDD2
147
VDD2
148
/AO
149
/AO
150
/OE
X[µm]
4238.0
4342.0
4446.0
4550.0
4654.0
4758.0
4862.0
4966.0
5070.0
5174.0
5278.0
5382.0
5486.0
5590.0
5694.0
5798.0
5902.0
6006.0
6110.0
6214.0
6318.0
6422.0
6526.0
6630.0
6734.0
6838.0
6942.0
7046.0
7150.0
7254.0
7358.0
7462.0
7566.0
7670.0
8415.0
8770.0
8840.0
8770.0
8840.0
8770.0
8840.0
8770.0
8840.0
8770.0
8840.0
8770.0
8840.0
8770.0
8840.0
8770.0
Y[µm]
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-437.0
-416.0
-416.0
-341.0
-341.0
-266.0
-266.0
-191.0
-191.0
-116.0
-116.0
-41.0
-41.0
34.0
34.0
109.0
Bump Size (X:Y)[µm]
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
60:90
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
PAD No. PAD Name
151
/OE
152
VEE
153
VEE
154
VEE
155
VEE
156
VEE
157
VEE
158
PASS
159
PASS
160
DUMMY
161
O0
162
O1
163
O2
164
O3
165
O4
166
O5
167
O6
168
O7
169
O8
170
O9
171
O10
172
O11
173
O12
174
O13
175
O14
176
O15
177
O16
178
O17
179
O18
180
O19
181
O20
182
O21
183
O22
184
O23
185
O24
186
O25
187
O26
188
O27
189
O28
190
O29
191
O30
192
O31
193
O32
194
O33
195
O34
196
O35
197
O36
198
O37
199
O38
200
O39
Preliminary Product Information S16071EJ6V0PM
X[µm]
8840.0
8770.0
8840.0
8770.0
8840.0
8770.0
8840.0
8770.0
8840.0
7878.0
7826.0
7774.0
7722.0
7670.0
7618.0
7566.0
7514.0
7462.0
7410.0
7358.0
7306.0
7254.0
7202.0
7150.0
7098.0
7046.0
6994.0
6942.0
6890.0
6838.0
6786.0
6734.0
6682.0
6630.0
6578.0
6526.0
6474.0
6422.0
6370.0
6318.0
6266.0
6214.0
6162.0
6110.0
6058.0
6006.0
5954.0
5902.0
5850.0
5798.0
Y[µm]
109.0
184.0
184.0
259.0
259.0
334.0
334.0
409.0
409.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
Bump Size (X:Y)[µm]
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
50:50
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
5
µ PD16708
Table 2−
−1. Pad Coordinate (3/5)
PAD No. PAD Name
201
O40
202
O41
203
O42
204
O43
205
O44
206
O45
207
O46
208
O47
209
O48
210
O49
211
O50
212
O51
213
O52
214
O53
215
O54
216
O55
217
O56
218
O57
219
O58
220
O59
221
O60
222
O61
223
O62
224
O63
225
O64
226
O65
227
O66
228
O67
229
O68
230
O69
231
O70
232
O71
233
O72
234
O73
235
O74
236
O75
237
O76
238
O77
239
O78
240
O79
241
O80
242
O81
243
O82
244
O83
245
O84
246
O85
247
O86
248
O87
249
O88
250
O89
6
X[µm]
5746.0
5694.0
5642.0
5590.0
5538.0
5486.0
5434.0
5382.0
5330.0
5278.0
5226.0
5174.0
5122.0
5070.0
5018.0
4966.0
4914.0
4862.0
4810.0
4758.0
4706.0
4654.0
4602.0
4550.0
4498.0
4446.0
4394.0
4342.0
4290.0
4238.0
4186.0
4134.0
4082.0
4030.0
3978.0
3926.0
3874.0
3822.0
3770.0
3718.0
3666.0
3614.0
3562.0
3510.0
3458.0
3406.0
3354.0
3302.0
3250.0
3198.0
Y[µm]
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
Bump Size (X:Y)[µm]
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
PAD No. PAD Name
252
O90
252
O91
253
O92
254
O93
255
O94
256
O95
257
O96
258
O97
259
O98
260
O99
261
O100
262
O101
263
O102
264
O103
265
O104
266
O105
267
O106
268
O107
269
O108
270
O109
271
O110
272
O111
273
O112
274
O113
275
O114
276
O115
277
O116
278
O117
279
O118
280
O119
281
O120
282
O121
283
O122
284
O123
285
O124
286
O125
287
O126
288
O127
289
O128
290
O129
291
O130
292
O131
293
O132
294
O133
295
O134
296
O135
297
O136
298
O137
299
O138
300
O139
Preliminary Product Information S16071EJ6V0PM
X[µm]
3146.0
3094.0
3042.0
2990.0
2938.0
2886.0
2834.0
2782.0
2730.0
2678.0
2626.0
2574.0
2522.0
2470.0
2418.0
2366.0
2314.0
2262.0
2210.0
2158.0
2106.0
2054.0
2002.0
1950.0
1898.0
1846.0
1794.0
1742.0
1690.0
1638.0
1586.0
1534.0
1482.0
1430.0
1378.0
1326.0
1274.0
1222.0
1170.0
1118.0
1066.0
1014.0
962.0
910.0
858.0
806.0
754.0
702.0
650.0
598.0
Y[µm]
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
Bump Size (X:Y)[µm]
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
µ PD16708
Table 2−
−1. Pad Coordinate (4/5)
PAD No. PAD Name
301
O140
302
O141
303
O142
304
O143
305
O144
306
O145
307
O146
308
O147
309
O148
310
O149
311
O150
312
O151
313
O152
314
O153
315
O154
316
O155
317
O156
318
O157
319
O158
320
O159
321
O160
322
O161
323
O162
324
O163
325
O164
326
O165
327
O166
328
O167
329
O168
330
O169
331
O170
332
O171
333
O172
334
O173
335
O174
336
O175
337
O176
338
O177
339
O178
340
O179
341
O180
342
O181
343
O182
344
O183
345
O184
346
O185
347
O186
348
O187
349
O188
350
O189
X[µm]
546.0
494.0
442.0
390.0
338.0
286.0
234.0
182.0
130.0
78.0
26.0
-26.0
-78.0
-130.0
-182.0
-234.0
-286.0
-338.0
-390.0
-442.0
-494.0
-546.0
-598.0
-650.0
-702.0
-754.0
-806.0
-858.0
-910.0
-962.0
-1014.0
-1066.0
-1118.0
-1170.0
-1222.0
-1274.0
-1326.0
-1378.0
-1430.0
-1482.0
-1534.0
-1586.0
-1638.0
-1690.0
-1742.0
-1794.0
-1846.0
-1898.0
-1950.0
-2002.0
Y[µm]
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
Bump Size (X:Y)[µm]
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
PAD No. PAD Name
351
O190
352
O191
353
O192
354
O193
355
O194
356
O195
357
O196
358
O197
359
O198
360
O199
361
O200
362
O201
363
O202
364
O203
365
O204
366
O205
367
O206
368
O207
369
O208
370
O209
371
O210
372
O211
373
O212
374
O213
375
O214
376
O215
377
O216
378
O217
379
O218
380
O219
381
O220
382
O221
383
O222
384
O223
385
O224
386
O225
387
O226
388
O227
389
O228
390
O229
391
O230
392
O231
393
O232
394
O233
395
O234
396
O235
397
O236
398
O237
399
O238
400
O239
Preliminary Product Information S16071EJ6V0PM
X[µm]
-2054.0
-2106.0
-2158.0
-2210.0
-2262.0
-2314.0
-2366.0
-2418.0
-2470.0
-2522.0
-2574.0
-2626.0
-2678.0
-2730.0
-2782.0
-2834.0
-2886.0
-2938.0
-2990.0
-3042.0
-3094.0
-3146.0
-3198.0
-3250.0
-3302.0
-3354.0
-3406.0
-3458.0
-3510.0
-3562.0
-3614.0
-3666.0
-3718.0
-3770.0
-3822.0
-3874.0
-3926.0
-3978.0
-4030.0
-4082.0
-4134.0
-4186.0
-4238.0
-4290.0
-4342.0
-4394.0
-4446.0
-4498.0
-4550.0
-4602.0
Y[µm]
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
Bump Size (X:Y)[µm]
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
7
µ PD16708
Table 2−
−1. Pad Coordinate (5/5)
PAD No. PAD Name
401
O240
402
O241
403
O242
404
O243
405
O244
406
O245
407
O246
408
O247
409
O248
410
O249
411
O250
412
O251
413
O252
414
O253
415
O254
416
O255
417
O256
418
O257
419
O258
420
O259
421
O260
422
O261
423
O262
424
O263
425
O264
426
O265
427
O266
428
O267
429
O268
430
O269
431
O270
432
O271
433
O272
434
O273
435
O274
436
O275
437
O276
438
O277
439
O278
440
O279
441
O280
442
O281
443
O282
444
O283
445
O284
446
O285
447
O286
448
O287
449
O288
450
O289
8
X[µm]
-4654.0
-4706.0
-4758.0
-4810.0
-4862.0
-4914.0
-4966.0
-5018.0
-5070.0
-5122.0
-5174.0
-5226.0
-5278.0
-5330.0
-5382.0
-5434.0
-5486.0
-5538.0
-5590.0
-5642.0
-5694.0
-5746.0
-5798.0
-5850.0
-5902.0
-5954.0
-6006.0
-6058.0
-6110.0
-6162.0
-6214.0
-6266.0
-6318.0
-6370.0
-6422.0
-6474.0
-6526.0
-6578.0
-6630.0
-6682.0
-6734.0
-6786.0
-6838.0
-6890.0
-6942.0
-6994.0
-7046.0
-7098.0
-7150.0
-7202.0
Y[µm]
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
Bump Size (X:Y)[µm]
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
PAD No. PAD Name
451
O290
452
O291
453
O292
454
O293
455
O294
456
O295
457
O296
458
O297
459
O298
460
O299
461
O300
462
O301
463
DUMMY
Preliminary Product Information S16071EJ6V0PM
X[µm]
-7254.0
-7306.0
-7358.0
-7410.0
-7462.0
-7514.0
-7566.0
-7618.0
-7670.0
-7722.0
-7774.0
-7826.0
-7930.0
Y[µm]
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
364.0
459.0
459.0
Bump Size (X:Y)[µm]
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
60:45
µ PD16708
3. PIN FUNCTIONS
Pin Symbol
O1 to O300
Pin Name
Driver output
Pad No.
162 to 461
I/O
Description
Output These pins output scan signals that drive the vertical direction (gate lines) of
a TFT-LCD. The output signals change in synchronization with the rising
edge of shift clock (CLK). The driver output amplitude is VDD2 to VEE.
O0, O301
LCD panel
161, 462
Output Regardless of shift data, these pins output VEE level.
auxiliary
R,/L
Shift direction 17, 18, 142, 143
Input
control
The shift direction control pin of shift register. The shift directions of the shift
registers are as follows.
R,/L = H (right shift) : STVR → O1 → O300 → STVL
R,/L = L (left shift) : STVL → O300 → O1 → STVR
STVR,
Start pulse
23, 24, 136, 137
I/O
STVL
These refer to the input pins of the internal shift register. The start pulse is
read at the rising edge of CLK, and scan signals are output from the driver
output pins. The input level is VDD1 to VSS (logic level).
CLK
Shift clock
21, 22, 138, 139
Input
This pin inputs a shift clock to the internal shift register.
The shift operation is performed in synchronization with the rising edge of
this input.
/OE
Output enable 9, 10, 150, 151
Input
When these pins go low level, the driver output is fixed to VEE level.
/AO
All-on control
Input
When these pins go low level, all outputs are fixed to VDD2. These pins are
The shift registers are not cleared. Refer to 4. TIMING CHART for details.
11, 12, 148, 149
pulled up to the VDD1 power supply inside the IC.
DUMMY
Dummy
25 to 135, 160, 463
–
No dummy pins are connected with other pins inside the IC.
PASS
Pass line
1, 2, 158, 159
–
Connected together internal.
VDD1
Logic power
15, 16, 144, 145
–
2.3 to 3.6 V
Driver positive 13, 14, 146, 147
–
10 to 30 V
supply
VDD2
power supply
The driver output: High level
VSS
Logic ground
19, 20, 140, 141
–
Connect this pin to the ground of the system.
VEE
Negative
3 to 8, 152 to 157
–
−10 to −3.0 V
power supply
for internal
operation and
driver
Cautions 1. To prevent latch up, turn on power to VDD1, VEE, VDD2 and logic input in this order. Turn off power
in the reverse order. These power up/down sequences must be observed also during transition
period.
2. Insert a capacitor of about 0.1 µF between each power line, as shown below, to secure noise
margin such as VIH and VIL.
VDD2
VDD1
0.1 µ F
0.1 µ F
VSS
0.1 µ F
VEE
Preliminary Product Information S16071EJ6V0PM
9
µ PD16708
4. TIMING CHART
(1) R,/L = H
1
2
3
4
5
6
CLK
/OE
/AO
STVR
O1
O2
O3
O4
O300
STVL
10
Preliminary Product Information S16071EJ6V0PM
300
µ PD16708
(2) R,/L = L
1
2
3
4
5
6
300
CLK
/OE
/AO
STVL
O300
O299
O298
O297
O1
STVR
Preliminary Product Information S16071EJ6V0PM
11
µ PD16708
5. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°°C, VSS = 0 V)
Parameter
Symbol
Rating
Unit
Logic supply voltage
VDD1
−0.3 to +6.0
V
Driver positive supply voltage
VDD2
−0.3 to +32
V
Internal operation negative supply voltage
VEE
−17 to +0.3
V
Power supply voltage
VDD2 to VEE
−0.3 to +41
V
Operating ambient temperature
TA
−20 to +75
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = −20 to +75°C, VSS = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
VEE cascade 100 Ω resistor
2.3
3.0
3.6
V
10
20
30
V
Internal operation negative supply voltage VEE
−10
−6.5
−3.0
V
Power supply voltage
VDD2 to VEE
13
26
40
V
Clock frequency
fCLK
500
kHz
Logic supply voltage
VDD1
Driver positive supply voltage
VDD2
Electrical Characteristics (TA = −20 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 10 to 30 V, VEE = −10 to −3.0 V,
VDD2 to VEE = 13 to 40 V, VSS = 0 V)
Parameter
Symbol
Condition
MAX.
Unit
0.7 VDD1
MIN.
TYP.
VDD1
V
0
0.3 VDD1
V
High-level input voltage
VIH
CLK, STVR (L) , R,/L, /OE, /AO,
Low-level input voltage
VIL
VDD1 = 3.3 V
High-level driver output current
IOH1
O1 to O300, VO = VDD2 − 1.0 V
0.5
mA
Low-level driver output current
IOL1
O1 to O300, VO = VEE + 1.0 V
−0.5
mA
High-level logic output current
IOH2
STVR (L) , VO = VDD1 − 0.5 V
200
µA
Low-level logic output current
IOL2
STVR (L) , VO = 0.5 V
200
Pull-up impedance
RPU
/AO
10
Input leak current
IIL
VI = 0 V or 3.6 V, Except /AO
Static current dissipation
IDD1
VDD1, fCLK = 50 kHz, /OE = H,
µA
52.7
100
kΩ
±1.0
µA
15.34
500
µA
5.47
50
µA
No load, fSTV = 60 Hz
IDD2
VDD2, fCLK = 50 kHz, /OE = H,
No load, fSTV = 60 Hz
IEE
VEE, fCLK = 50 kHz, /OE = H,
−550
No load, fSTV = 60 Hz
12
Preliminary Product Information S16071EJ6V0PM
−20.43
µA
µ PD16708
Switching Characteristics (TA = −20 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 10 to 30 V, VEE = −10 to −3.0 V,
VDD2 to VEE = 13 to 40 V, VSS = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Output rise time
tTLH
CL = 300 pF, 10 to 90%
1400
ns
Output fall time
tTHL
CL = 300 pF, 90 to 10%
1400
ns
STVR (L) delay time
tPHL1
CL = 15 pF,
450
ns
tPLH1
CLK → STVR (L)
450
ns
tPHL2
CL = 800 pF, CLK → On
1.5
µs
1.5
µs
1.5
µs
1.5
µs
1.5
µs
1.5
µs
Driver output delay time
tPLH2
/OE to driver output delay time
tPHL3
CL = 800 pF, /OE → On
tPLH3
/AO to driver output delay time
tPHL4
CL = 800 pF, /AO→ On
tPLH4
Timing Requirements (TA = −20 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 10 to 30 V, VEE = −10 to −3.0 V,
VDD2 to VEE = 13 to 40 V, VSS = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Clock pulse high width
PW CLK(H)
500
ns
Clock pulse low width
PW CLK(L)
STVR (L) setup time
tSETUP
STVR (L) ↑ → CLK ↑
500
200
ns
ns
STVR (L) hold time
tHOLD
CLK ↑ → STVR (L) ↓
300
ns
Output enable pulse width
PW OE
/OE
1.00
µs
Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
Preliminary Product Information S16071EJ6V0PM
13
14
Preliminary Product Information S16071EJ6V0PM
STVL (R)
O300
O3
O2
O1
/OE
/AO
STVR (L)
CLK
10%
tPLH2
50%
tSETUP tHOLD
50%
PWCLK(H)
90%
tPHL2
90%
10%
tTLH
10%
90%
tTHL
50% 1 50% 2 50% 3 50% 4
50%
PWCLK(L)
5
6
7
50%
tPLH4
10%
tPHL4
90%
50%
tPLH1
50%
50%
300
50%
tPHL1
50%
50%
PWOE
10%
tf
50%
10%
90%
90%
tPLH3 tPHL2
50%
10%
90%
tPLH2 tPHL3
50%
tr
µ PD16708
Switching Characteristics Waveform (R,/L= H)
Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
µ PD16708
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Preliminary Product Information S16071EJ6V0PM
15
µ PD16708
Reference Documents
NEC Semiconductor Device Reliability/Quality Control System (C10983E)
Quality Grades On NEC Semiconductor Devices (C11531E)
• The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
• No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.
• NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC Electronics or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative purposes
in semiconductor product operation and application examples. The incorporation of these circuits, software and
information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC
Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of
these circuits, software and information.
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannnot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics
products, customers must incorporate sufficient safety measures in their design, such as redundancy, firecontainment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special", and "Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated
"quality assurance program" for a specific application. The recommended applications of an NEC Electronics
product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC
Electronics products before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and
visual equipment, home electronic appliances, machine tools, personal electronic equipment and
industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life
support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support
systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M5 02. 11-1