DATA SHEET MOS INTEGRATED CIRCUIT µ PD16364 160-BIT HIGH-VOLTAGE CMOS DRIVER DESCRIPTION The µ PD16364 is a high-voltage CMOS driver for EL display. It consists of 4 × 40/8 × 20-bit data latch, 160-bits data latch, 160-bit level shifter, and a high-voltage CMOS driver. The logic circuit operates on 5-V power supply (CMOS level input), so that it can be connected to a micro-controller. The driver block is comprised of 60 V, 25 mA MAX. high-voltage output buffer, and both the logic block and driver block employ a CMOS, allowing operation with low power consumption. FEATURES • High-voltage Full CMOS process • High-voltage output (60 V, 25 mA MAX.) • 4 × 40/8 × 20-bit data latch (4/8-bit data input) • High-speed data transfer (fCLK = 16 MHz: in cascade connection) • Wide operating temperature range (TA = −40 to +85°C) ORDERING INFORMATION Part Number µ PD16364N -××× Package TCP (TAB package) Remark The TCP’s external shape is customized. To order the required shape, please contact one of our sales representatives. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S14000EJ2V0DS00 (2nd edition) Date Published November 2002 NS CP(K) Printed in Japan The mark ★ shows major revised points. 1999 µ PD16364 1. BLOCK DIAGRAM DST SCK EIO1 EIO2 BS Control Circuit L,/R 20/40-bit Latch Selector 20/40 D0 4 X 20/8 X 20-bit Data Latch 4/8 Data MPX 160 D7 REV VDD1 160-bit Data Latch VSS1 160 160-bit Level Shifter 160 VDD2 OC 160-bit HIgh-Voltage CMOS Driver VSS2 OUT OUTOUT OUT 157 158 159 160 OUT1 OUT2 OUT3 OUT4 Remark /xxx indicates active low signal. 2 Data Sheet S14000EJ2V0DS µ PD16364 2. PIN CONFIGURATION (µPD16364N-xxx: Copper foil surface, Face-up) DUMMY DUMMY VSS2 VDD2 VDD2 VSS2 DUMMY DUMMY DUMMY BS DUMMY OUT1 L,/R OUT2 OC OUT3 REV OUT4 DST OUT5 CLK VSS1 EIO1 EIO2 Copper foil suface VDD1 D7 D6 D5 D4 D3 OUT156 OUT157 D2 OUT158 D1 OUT159 D0 OUT160 VSS2 VDD2 VDD2 VSS2 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY Remark This figure does not specify the TCP package. Caution Be sure to use all the VDD1, VDD2, VSS1, and VSS2 pins. Keep the VSS1 and VSS2 pins at the same voltage level. Data Sheet S14000EJ2V0DS 3 µ PD16364 3. PIN FUNCTIONS Pin Symbol ! EIO1 Pin Name Enable I/O1 I/O I/O Description L,/R pin = “L” level: Input L,/R pin = “H” level: Output ! EIO2 Enable I/O2 I/O L,/R pin = “H” level: Input L,/R pin = “L” level: Output SCK Shift Clock Input Input DST Data Strobe Input Input Fall edge operation. Input shift clock for 4 x 40/8 x 20-bit data latch. Fall edge operation. Data are latched to 160-bits data latch and also set outputs of OUT1 to OUT160. D0 to D7 Data Input Input Data input. When BS is low level, D4 to D7 pins should be connected to VSS1 or VDD1. Input Refer to 4.TRUTH TABLE Output Control Input When OC pin is low level, output is normal operation. Invert Input Data Input L,/R Select Left or Right OC REV Shift When OC pin is high level, output become low level. When REV pin is low level, input data D0 to D7 are latched without inversion. When REV pin is high level, input data D0 to D7 are inverted before latching. BS Bus Select Input When BS pin is low level, data bus is4 bits. When BS pin is high level, data bus is 8 bits. OUT1 to High-voltage output Output OUT160 Output level is VSS2 or VDD2. These outputs are changed by falling edge of DST pin. VDD1 Logic power supply – Logic power supply VDD2 Driver power supply – Driver power supply VSS1 Logic ground – Grounding VSS2 Driver ground – Grounding 4 Data Sheet S14000EJ2V0DS µ PD16364 4. TRUTH TABLE Shift Register Block (4 x 40 data latch, BS = L) L,/R SCK 1 2 3 ... 40 L level D3 1 5 9 ... 157 D2 2 6 10 ... 158 D1 3 7 11 ... 159 H level D0 4 8 12 ... 160 D3 160 156 152 ... 4 D2 159 155 151 ... 3 D1 158 154 150 ... 2 D0 157 153 149 ... 1 Shift Register Block (8 x 20 data latch, BS = H) ! L,/R SCK 1 2 3 ... 20 L level D7 1 9 17 ... 153 D6 2 10 18 ... 154 D5 3 11 19 ... 155 D4 4 12 20 ... 156 D3 5 13 21 ... 157 D2 6 14 22 ... 158 D1 7 15 23 ... 159 D0 8 16 24 ... 160 D7 160 152 144 ... 8 D6 159 151 143 ... 7 D5 158 150 142 ... 6 D4 157 149 141 ... 5 D3 156 148 140 ... 4 D2 155 147 139 ... 3 D1 154 146 138 ... 2 D0 153 145 137 ... 1 H level Control Block L,/R EIO1 EIO2 H level Out In L level In Out OC REV Dn L L L L L L H H L H L H L H H L H x x L (All driver outputs are L.) Driver Block Driver Output Data Sheet S14000EJ2V0DS 5 µ PD16364 5. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C, VSS1 = VSS2 = 0 V) Parameter Symbol Rating Unit Logic Part Supply Voltage VDD1 –0.5 to +6.0 V Driver Part Supply Voltage VDD2 –0.5 to +60 V Logic Part Input Voltage VI1 –0.5 to VDD1 + 0.5 V Logic Part Output Voltage VO1 –0.5 to VDD1 + 0.5 V Driver Part Output Voltage VO2 –0.5 to VDD2 + 0.5 V Logic Part Output Current IO1 ±10 mA Driver Part Output Current IO2 ±25 mA Operating Ambient Temperature TA –40 to +85 °C Storage Temperature Tstg –55 to +125 °C Cautions 1. TA ≥ 25°C , load should be alleviated at a rate of –4.5 mW/°C. 2. Product qualify may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = –40 to +85°C, VSS1 = VSS2 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 5.0 5.5 V Logic Part Supply Voltage VDD1 4.5 Driver Part Supply Voltage VDD2 20 55 V High-Level Input Voltage VIH 0.8 VDD1 VDD1 V Low-Level Input Voltage VIL 0 0.2 VDD1 V Driver Part Output Current IOL2 +20 mA IOH2 −20 mA Caution Turn of and off power sequence must be as follows: Turn-on sequence: VDD1 → Input → VDD2 Turn-off sequence: VDD2 → Input →VDD1 6 Data Sheet S14000EJ2V0DS µ PD16364 Electrical Characteristics (TA = –40 to +85°C, VDD1 = 4.5 to 5.5 V, VDD2 = 55 V, VSS1 = VSS2 = 0 V,) Parameter Symbol Conditions MIN. TYP. MAX. Unit VOH1 Logic, IOH1 = −0.4 mA, VDD1 − 0.4 V VOH2 OUT1 to OUT160, IOH2 = −1.0 mA VDD2 − 0.4 V Low-Level Output Voltage VOL1 Logic, IOL1 = 0.4 mA 0.4 VOL2 OUT1 to OUT160, IOL2 = 1.0 mA 0.4 V High-Level Input Current IIH VI = VDD1 5.0 µA Low-Level Input Current IIL VI = 0 V −5.0 µA High-Level Input Voltage VIH Logic Low-Level Input Voltage VIL Logic RON Variance RVAR OUT1 to OUT160 (in one chip High-Level Output Voltage 0.8 VDD1 under constant Tj Logic Part Dynamic Current Note1 V V 0.2 VDD1 V ±30 % ) IDD1 Note2 10 mA IDD2 Note2 10 mA Istandby Note3 500 µA MAX. Unit Consumption Driver Part Dynamic Current Consumption Standby Current Notes 1. Rvar = (1 − Xn/Xavg) x 100 Xn = Impedance of OUTn, Xavg = Impedance of average IOH2 = −1.0 mA, IOL2 = 1.0 mA 2. fSCK = 16 MHz, fDST = 36 kHz, VIN = VDD1 or VSS1, no load 3. VIN = VDD1 or VSS1, no load Switching Characteristics (TA = –40 to +85°C, VDD1 = 4.5 to 5.5 V, VDD2 = 55 V, VSS1 = VSS2 = 0 V) Parameter Symbol Conditions MIN. TYP. Enable Pulse Delay Time tPLH1 DST↓ → EIOn↑, CL = 30 pF 70 ns tPHL2 Last SCK↓ → EIOn↓, CL = 30 pF 40 ns Driver Output Delay Time tPHL3 DST↓ → OUT1 to OUT160, 7 µs tPLH3 CL = 2000 pF 7 µs 20 pF Input Capacitance CI Data Sheet S14000EJ2V0DS 7 µ PD16364 Timing Requirement (TA = –40 to +85°C, VDD1 = 4.5 to 5.5 V, VDD2 = 55 V, VSS1 = VSS2 = 0 V, tr = tf = 13.0 ns) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK Cycle Time tCSCK 62 ns SCK Pulse Width PWCLK 20 ns DST Cycle Time tCDST 1000 ns DST High-Level Pulse Width PWDST 30 ns DST-SCK Time tDST-SCK DST↓ → 1st SCK ↓ 100 ns SCK-DST Time tSCK-DST Last SCK↓ → DST ↓ 30 ns Data Setup Time tSETUP 20 ns Data Hold Time tHOLD 20 ns REV Setup Time tRSETUP 40 ns REV Hold Time tRHOLD 30 ns EIO-SCK Time1 tEIO-SCK1 EIOn↓ → 1st SCK ↓ 22 ns EIO-SCK Time2 tEIO-SCK2 EIOn↑ → 1st SCK ↑ 25 ns 8 Data Sheet S14000EJ2V0DS µ PD16364 Switching Characteristics and Timing Requirements Waveform Timing requirement waveform 0.8 VDD1 Input 0.2 VDD1 0.8 VDD1 or 0.8 VDD2 Output 0.2 VDD1 or 0.2 VDD2 Switching characteristics waveform tCSCK PW CLK PW CLK tr tf LAST SCK tSCK-DST PWDST tr tf tCDST tDST-SCK DST tRSETUP tRHOLD REV tHOLD tSETUP D0 to D7 t PHL3,, tPLH3 OUT (n) 1 SCK 2 40/20 1 tDST-SCK DST tPHL2 t PLH1 EIO (Output) tEIO-SCK2 tEIO-SCK1 EIO (Input) Data Sheet S14000EJ2V0DS 9 10 Data Sheet S14000EJ2V0DS OUT1OUT160 IC11 EIO1 / IC12 EIO2 IC2 EIO1 / IC3 EIO2 IC1 EIO1 / IC1 EIO2 IC1 EIO2 DST D0 to D7 SCK 2 3 IC1 data reading 1 20 2 3 IC2 data reading 1 20 2 3 IC3 data reading 1 20 2 3 IC12 data reading 1 20 1 2 µ PD16364 Timing Example (640 dots x 3/line, BS = H, L,/R = H) µ PD16364 6. RECOMMENDED SOLDERING CONDITIONS The following conditions must be met for soldering conditions of the µ PD16364. For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. µPD16364N-×××: TCP (TAB package) Mounting Condition Mounting Method Condition Thermocompression Soldering Heating tool 300 to 350°C: heating for 2 to 3 seconds: pressure 100g (per solder) ACF (Adhesive Conductive Film) Temporary bonding 70 to 100°C: pressure 3 to 8 kg/cm2: time 3 to 5 seconds. Real bonding 165 to 180°C: pressure 25 to 45 kg/cm2: time 30 to 40 seconds. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd.) Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more packaging methods at a time. Data Sheet S14000EJ2V0DS 11 µ PD16364 [MEMO] 12 Data Sheet S14000EJ2V0DS µ PD16364 [MEMO] Data Sheet S14000EJ2V0DS 13 µ PD16364 [MEMO] 14 Data Sheet S14000EJ2V0DS µ PD16364 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S14000EJ2V0DS 15 µ PD16364 Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Semiconductor Device Mounting Technology (C10535E) • The information in this document is current as of November, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. 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