DATA SHEET MOS INTEGRATED CIRCUIT µPD16705 263/256-OUTPUT TFT-LCD GATE DRIVER DESCRIPTION The µPD16705 is a TFT-LCD gate driver equipped with 263/256-output lines. It can output a high-gate scanning voltage in response to CMOS level input because it provided with a level-shift circuit inside the IC circuit. It can also drive the XGA/SXGA and SXGA+. FEATURES • CMOS level input (3.3 V/2.5 V) • 263/256 outputs • High-output voltage (VDD2-VEE: 40 V MAX.) • Capable of All-on outputting (/AO) Remark /xxx indicates active low signal. ORDERING INFORMATION Part Number Package µPD16705N-xxx TCP (TAB package) Remark The TCP’s external shape is customized. To order the required shape, please contact one of our sales representatives. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S15818EJ1V0DS00 (1st edition) Date Published July 2002 NS CP (K) Printed in Japan © 2001 µPD16705 1. BLOCK DIAGRAM R,/L LS1Note MODE LS1Note CLK LS1Note STVR LS1Note OE1 LS1Note OE2 LS1Note OE3 LS1Note /AO LS1Note 263-bit shift register SR1 SR2 SR3 LS2Note LS2Note LS2Note SR261 SR262 SR263 LS1Note LS2Note LS2Note LS2Note VEE O1 O2 O3 O261 O262 O263 VDD1 VDD2 VSS Note LS1: shifts CMOS level and internal level, LS2: shifts interval level and output level (VDD2-VEE). 2 Data Sheet S15818EJ1V0DS STVL µPD16705 2. PIN CONFIGURATION (µPD16705N-xxx: Copper foil surface, face-up) O1 O2 VDD2 VEE VSS VDD1 STVR VSS R,/L VDD1 CLK Copper /AO Foil OE1 Surface OE2 OE3 STVL VDD1 MODE VSS VEE VDD2 O261 O262 O263 Remark This figure does not specify the TCP package. Data Sheet S15818EJ1V0DS 3 µPD16705 3. PIN FUNCTIONS Pin Symbol O1 to O263 Pin Name Driver output I/O O Description These pins output scan signals that drive the vertical direction (gate lines) of a TFT-LCD. The output signals changes in synchronization with the rising edge of shift clock CLK. The driver output amplitude is VDD2 to VEE. R,/L Shift direction select I The shift direction control pin of shift resister. R,/L = H (right shift): STVR → O1 → O263 → STVL input R,/L = L or Open (left shift): STVL → O263 → O1 → STVR STVR, Start pulse STVL input/output I/O This is the input of the internal shift register. The start pulse is read at the rising edge of shift clock CLK, and scan signals are output from the driver output pins. The input level is a VDD1 to VSS (logic level). When in MODE = H, the start pulse is output at the falling edge of the 263rd clock of shift clock CLK, and is cleared at the falling edge of the 264th clock. The output level is VDD1 to VSS (logic level). CLK Shift clock input I This pin inputs a shift clock to the internal shift register. The shift operation is performed in synchronization with the rising edge of this input. OE1, Output enable input I When this pin goes high level, the driver output is fixed to VEE level. The shift OE2, register is not cleared. CLK is asynchronous in the clock. Note that the output OE3 terminal, which can be controlled by the enable signal changes, refers to 4. RELATIONS OF ENABLE INPUT AND OUTPUT TERMINAL. /AO All-on control I When this pin goes low level, all driver output is fixed to VDD2 level. The shift register is not cleared. This pin has priority over OE1 to OE3. /AO is pulled up to VDD1 inside the IC. CLK is asynchronous in the clock. MODE Selection of number of I MODE = VDD1 or open: 263 outputs MODE = VSS: 256 outputs (driver output pins O129 to O135 are invalid.) outputs Input level is VDD1 to VSS (logic level). MODE is pulled up to VDD1 inside the IC. VDD1 Logic power supply - 2.3 to 3.6 V VDD2 Driver positive power - 15 to 25 V. The driver output: high level supply VSS Logic ground - Connect this pin to the ground of the system. VEE Negative power - –15 to –5 V. The driver output: low level supply for internal operation Cautions 1. To prevent latch-up, turn on power to VDD1, VEE, VDD2, and logic input in this order. Turn off power in the reverse order. These power up/down sequence must be observed also during transition period. 2. Insert a capacitor of about 0.1 µF between each power line, as shown below, to secure noise margin such as VIH and VIL. VDD2 VDD1 0.1 µ F 0.1 µ F VSS 0.1 µ F VEE 4 Data Sheet S15818EJ1V0DS µPD16705 4. RELATIONS OF ENABLE INPUT AND OUTPUT TERMINAL Switching is possible for 263/256 with µPD16705 by the MODE pin. And, the output terminal that can be controlled by the enable signal changes as follows along with this function. 263-output TCP 256-output TCP 263-output mode 256-output mode 263-output mode 256-output mode (MODE = H) (MODE = L) (MODE = H) (MODE = L) O1 (OE1) O1 (OE1) O1 (OE1) O1 (OE1) O2 (OE2) O2 (OE2) O2 (OE2) O2 (OE2) O3 (OE3) O3 (OE3) O3 (OE3) O3 (OE3) O4 (OE1) O4 (OE1) O4 (OE1) O4 (OE1) O5 (OE2) O5 (OE2) O5 (OE2) O5 (OE2) O6 (OE3) O6 (OE3) O6 (OE3) O6 (OE3) ↓ ↓ ↓ ↓ O127 (OE1) O127 (OE1) O127 (OE1) O127 (OE1) O128 (OE2) O128 (OE2) O128 (OE2) O128 (OE2) O129 (OE3) VX = VEE O130 (OE1) VX = VEE O131 (OE2) VX = VEE O132 (OE3) VX = VEE O133 (OE1) VX = VEE O134 (OE2) VX = VEE O135 (OE3) VX = VEE O136 (OE1) O136 (OE3) O136 (OE1) O136 (OE3) O137 (OE2) O137 (OE1) O137 (OE2) O137 (OE1) ↓ ↓ ↓ ↓ O259 (OE1) O259 (OE3) O259 (OE1) O259 (OE3) O260 (OE2) O260 (OE1) O260 (OE2) O260 (OE1) O261 (OE3) O261 (OE2) O261 (OE3) O261 (OE2) O262 (OE1) O262 (OE3) O262 (OE1) O262 (OE3) O263 (OE2) O263 (OE1) O263 (OE2) O263 (OE1) Remark VX is power-supply voltage of output pin O1 to O263. Data Sheet S15818EJ1V0DS 5 µPD16705 5. TIMING CHART (R,/L = H, /AO = H, MODE = H) 1 2 3 262 CLK OE1 OE2 OE3 STVR (STVL) O1 (O263) O2 (O262) O3 (O261) O262 (O2) O263 (O1) STVL (STVR) O1 of next stage (O263 of next stage) O2 of next stage (O262 of next stage) 6 Data Sheet S15818EJ1V0DS 263 264 265 266 µPD16705 6. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°°C, VSS = 0 V) Parameter Symbol Rating Unit Logic Supply Voltage VDD1 −0.5 to +7.0 V Driver Positive Supply Voltage VDD2 −0.5 to +28 V Power Supply Voltage VDD2-VEE −0.5 to +42 V Internal Operation Negative Supply Voltage VEE −16 to +0.5 V Input Voltage VI −0.5 to VDD1 +0.5 V Operating Ambient Temperature TA −20 to +75 °C Storage Temperature Tstg −55 to +125 °C Caution Product qualify may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = −20 to +75°C, VSS = 0 V) Parameter Symbol MIN. TYP. MAX. Unit Logic Supply Voltage VDD1 2.3 3.3 3.6 V Driver Positive Supply Voltage VDD2 15 23 25 V Internal Operation Negative Supply Voltage VEE −15 −10 −5.0 V Power Supply Voltage VDD2-VEE 20 33 40 V Clock Frequency fCLK 500 kHz Data Sheet S15818EJ1V0DS 7 µPD16705 Electrical Characteristics (TA = −20 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 23 V, VEE = −10 V, VSS = 0 V) Parameter Symbol High-level Input Voltage Condition MIN. TYP.Note MAX. Unit 0.8 VDD1 VDD1 V VIH CLK, STVR (STVL), R,/L, Low-level Input Voltage VIL OE1 to OE3 VSS 0.2 VDD1 V High-level Output Voltage VOH STVR (STVL), IOH = −40 µA VDD1 −0.4 VDD1 V Low-level Output Voltage VOL STVR (STVL), IOL = +40 µA VSS VSS +0.4 V LCD Driver Output ON Resistance RON VOUT = VEE +1.0 V, or 0.33 1.0 kΩ 50 100 kΩ ±1.0 µA 390 1000 µA 10 100 µA VDD2 −1.0 V Pull-up Resistance RPU VDD1 = 3.3 V, /AO, MODE Input Leak Current IIL VI = 0 V or 3.6 V, 10 except for /AO, MODE Static Current Dissipation IDD1 VDD1, fCLK = 50 kHz, OE1 = OE2 = OE3 = L, fSTV = 60 Hz, no load IDD2 VDD2, fCLK = 50 kHz, OE1 = OE2 = OE3 = L, fSTV = 60 Hz, no load IEE VEE, fCLK = 50 kHz, −1100 µA −400 OE1 = OE2 = OE3 = L, fSTV = 60 Hz, no load Remark STV: STVR (STVL). Switching Characteristics (TA = −20 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 23 V, VEE = −10 V, VSS = 0 V) Parameter Symbol Cascade Output Delay Time Driver Output Delay Time MAX. Unit tPHL1 CL = 20 pF, Condition MIN. TYP. 800 ns tPLH1 CLK → STVL (STVR) 800 ns tPHL2 CL = 300 pF, CLK → On 500 ns 500 ns 800 ns 800 ns 800 ns tPLH2 tPHL3 CL = 300 pF, OEn → On tPLH3 Output Rise Time tTLH Output Fall Time tTHL Input Capacitance CI CL = 300 pF TA = 25°C 800 ns 15 pF Timing Requirements (TA = −20 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 23 V, VEE = −10 V, VSS = 0 V, tr = tf = 20 ns (10 to 90%)) Parameter Symbol Condition MIN. TYP. MAX. Unit Clock Pulse High Width PW CLK(H) 500 ns Clock Pulse Low Width PW CLK(L) 500 ns Enable Pulse Width PW OE 1000 ns Data Setup Time tSETUP STVR (STVL) ↑ → CLK ↑ 200 ns Data Hold Time tHOLD CLK ↑ → STVR (STVL) ↓ 200 ns Remark Unless otherwise specified, the input level is defined to be VIH = 0.8 VDD1, VIL = 0.2 VDD1. 8 Data Sheet S15818EJ1V0DS µPD16705 Switching Characteristics Waveform (R,/L= H, MODE = H) 90% 50% 263 10% 10% tTLH 90% 90% tPHL2 tPLH2 Data Sheet S15818EJ1V0DS O1-O263 OE1-OE3 STVL O263 O262 • • • O2 O1 50% STVR tSETUP tHOLD 2 1 50% CLK PWCLK(H) 3 PWCLK(L) tTHL 4 5 6 7 260 261 262 50% tPLH1 tPHL1 50% tPHL3 PWOE tPLH3 10% 90% tr 10% tf Unless otherwise specified, the input level is defined to be VIH = 0.8 VDD1, VIL = 0.2 VDD1. 9 µPD16705 7. RECOMMENDED MOUNTING CONDITIONS The following conditions must be met for mounting conditions of the µPD16705. For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. µPD16705N-xxx: TCP (TAB Package) Mounting Condition Thermocompression Mounting Method Soldering Condition Heating tool 300 to 350°C, heating for 2 to 3 seconds, pressure 100g (per solder) ACF Temporary bonding 70 to 100°C, pressure 3 to 8 kg/cm2, time 3 to 5 sec. (Adhesive Real bonding 165 to 180°C, pressure 25 to 45 kg/cm2, time 30 to 40 sec. Conductive Film) (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd). Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time. 10 Data Sheet S15818EJ1V0DS µPD16705 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S15818EJ1V0DS 11 µPD16705 Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades On NEC Semiconductor Devices (C11531E) • The information in this document is current as of July, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. 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