UTRON UT62L12816(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 REVISION HISTORY REVISION Preliminary Rev. 0.5 Preliminary Rev. 0.6 Preliminary Rev. 0.7 Rev. 1.0 Rev. 1.1 DESCRIPTION Original. 1. The symbols CE# and OE# and WE# are revised as. CE and OE and WE . 2. Separate Industrial and Consumer SPEC. 3. Add access time 55ns range. 1. Revised Vcc range： a、 55ns (max.) for Vcc=2.7V~3.6V b、 70/100ns (max.) for Vcc=2.5V~3.6V 2. Revised block diagram 3. Revised DC ELECTRICAL CHARACTERISTICS： c、 Revised standby current ISB1=20/3uA(max.) for TA=0℃~50℃ ISB2=80/10uA(max.) for TA=-40℃~85℃ d、 Revised Icc=35/30/25mA(max.) 4. Revised AC ELECTRICAL CHARACTERISTICS： e、 Revised symbol name tHZB as tBHZ f、 Revised symbol name tLZB as tBLZ g、 Revised symbol name tPWB as tBW 5. Revised waveforms 6. Revised IDR=50/5uA(max.) 1. Revised DC ELECTRICAL CHARACTERISTICS： a、 Revised VIH as 2.2V 2. Revised AC ELECTRICAL CHARACTERISTICS： b、 Revised tBLZ as 10ns (min.) 3. Revised 48-pin TFBGA package outline dimension： c、 Rev. 0.7：ball diameter=0.3mm d、 Rev. 1.0：ball diameter=0.35mm Add order information for lead free product UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 DATE Mar, 2001 Jun 21,2001 Nov 6, 2001 Apr 23,2002 May 09,2003 P80049 UTRON UT62L12816(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 FEATURES GENERAL DESCRIPTION Fast access time : 55ns (max.) for Vcc=2.7V~3.6V 70/100ns (max.) for Vcc=2.5V~3.6V CMOS low power operating Operating current : 35/30/25mA (Icc max.) Standby current : 20uA(max.) L–version,0℃≦TA≦50℃ 3uA(max.) LL-version,0℃≦TA≦50℃ Single 2.5V~3.6V power supply Operating temperature: Industrial : -40℃~85℃ All TTL compatible inputs and outputs Fully static operation Three state outputs Data retention voltage : 1.5V (min.) Data byte control : LB (I/O1~I/O8) UB (I/O9~I/O16) Package : 44-pin 400mil TSOP-Ⅱ 48-pin 6mm × 8mm TFBGA The UT62L12816(I) is a 2,097,152-bit low power CMOS static random access memory organized as 131,072 words by 16 bits. The UT62L12816(I) operates from a wide range of 2.5V~ 3.6V supply voltage and all inputs and outputs are fully TTL compatible. The UT62L12816(I) is designed for low power system applications. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K× 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O Vcc Vss I/O1-I/O8 Lower Byte I/O9-I/O16 Upper Byte CE OE WE LB UB CONTROL CIRCUIT UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 2 P80049 UTRON UT62L12816(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 PIN CONFIGURATION 1 44 A5 43 42 A6 A2 2 3 A1 4 41 OE A0 40 UB CE 5 6 39 LB I/O1 7 8 38 37 I/O16 I/O2 I/O3 9 36 I/O14 I/O4 10 11 35 I/O13 34 Vss 12 Vcc I/O12 I/O11 A4 A3 Vcc Vss A LB OE A0 A1 A2 NC B I/O9 UB A3 A4 CE I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D Vss I/O12 NC A7 I/O4 Vcc E Vcc I/O13 NC A16 I/O5 Vss F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 NC A12 A13 WE I/O8 H NC A8 A9 A10 A11 NC 1 2 3 4 5 6 A7 I/O15 I/O5 13 33 32 I/O6 14 31 I/O7 15 30 I/O10 I/O8 29 I/O9 28 27 NC A8 WE 16 17 A16 18 A15 A14 19 20 26 A9 25 A10 A13 21 A11 A12 22 24 23 NC TFBGA TSOP II PIN DESCRIPTION SYMBOL A0 - A16 I/O1 - I/O16 CE WE OE LB UB VCC VSS NC DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Lower Byte Control Upper Byte Control Power Supply Ground No Connection TRUTH TABLE MODE Standby Output Disable Read Write Note: CE OE WE LB UB H X L L L L L L L L X X H H L L L X X X X X H H H H H L L L X H L X L H L L H L X H X L H L L H L L I/O OPERATION I/O1-I/O8 I/O9-I/O16 High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z DOUT High – Z High – Z DOUT DOUT DOUT DIN High – Z High – Z DIN DIN DIN SUPPLY CURRENT ISB, ISB1, ISB2 ICC,ICC1,ICC2 ICC,ICC1,ICC2 ICC,ICC1,ICC2 H = VIH, L=VIL, X = Don't care. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 3 P80049 UTRON UT62L12816(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to VSS Operating Temperature Industrial Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 secs) SYMBOL VTERM TA TSTG PD IOUT Tsolder RATING -0.3 to Vcc+0.3V -40 to 85 -65 to 150 1 50 260 UNIT V ℃ ℃ W mA ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 2.5V~3.6V, TA = -40℃ to 85℃) PARAMETER Power Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Operating Power Supply Current SYMBOL TEST CONDITION Vcc *1 VIH *2 VIL ILI ILO VOH VOL ICC VSS ≦VIN ≦VCC VSS ≦VI/O ≦VCC; Output Disable IOH= -1mA , (IOH= -0.5mA when Vcc<2.7V) IOL= 2.1mA Cycle time=min, 100%duty 55 I/O=0mA, CE =VIL Icc1 Average Operation Current Icc2 Standby Current (TTL) ISB ISB1 Standby Current (CMOS) 55 70/100 ISB2 100%duty, II/O=0mA CE ≦0.2V, other pins at 0.2V or Vcc-0.2V 70 100 TCycle= 1µs TCycle= 500ns CE =VIH, other pins =VIL or VIH MIN. TYP. 2.7V 3.0V 2.5V 2.2 -0.3 -1 -1 2.2 20 MAX. 3.6V 3.6V VCC+0.3 0.6 1 1 0.4 35 UNIT V V V V µA µA V V mA - 18 15 30 25 mA mA - 4 5 mA - 8 10 mA - 0.3 0.5 mA - - 20 µA µA other pins at 0.2V or Vcc-0.2V -L -LL - - 3 CE =VCC-0.2V, TA = -40℃ to 85℃ -L - - 80 -LL - - 10 CE =VCC-0.2V, TA = 0℃ to 50℃ other pins at 0.2V or Vcc-0.2V Notes: 1. Overshoot : Vcc+3.0v for pulse width less than 10ns. 2. Undershoot : Vss-3.0v for pulse width less than 10ns. 3. Overshoot and Undershoot are sampled, not 100% tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 4 µA µA P80049 UTRON UT62L12816(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 CAPACITANCE (TA=25℃, f=1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX 6 8 - UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 5ns 1.5V CL = 30pF, IOH/ IOL = -1mA/2.1mA AC ELECTRICAL CHARACTERISTICS (TA = -40℃ to 85℃) (1) READ CYCLE PARAMETER SYMBOL UT62L12816(I)-55 UT62L12816(I)-70 UT62L12816(I)-100 VCC =2.7V~3.6V VCC =2.5V~3.6V VCC =2.5V~3.6V UNIT LB , UB Access Time tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA MIN. 55 10 5 10 - MAX. 55 55 30 20 20 55 MIN. 70 10 5 10 - MAX. 70 70 35 25 25 70 MIN. 100 10 5 10 - MAX. 100 100 50 30 30 100 ns ns ns ns ns ns ns ns ns ns LB , UB to High-Z Output tBHZ - 25 - 30 - 40 ns LB , UB to Low-Z Output tBLZ 10 - 10 - 10 - ns Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High Z LB , UB Valid to End of Write SYMBOL tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* tBW UT62L12816(I)-55 UT62L12816(I)-70 UT62L12816(I)-100 VCC =2.7V~3.6V VCC =2.5V~3.6V VCC =2.5V~3.6V MIN. 55 50 50 0 45 0 25 0 5 45 MAX. 30 - MIN. 70 60 60 0 55 0 30 0 5 60 MAX. 30 - MIN. 100 80 80 0 70 0 40 0 5 80 MAX. 40 - UNIT ns ns ns ns ns ns ns ns ns ns ns * These parameters are guaranteed by device characterization, but not production tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 5 P80049 UTRON UT62L12816(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA tOH Dout tOH Previous data valid Data Valid READ CYCLE 2 ( CE and OE Controlled) (1,3,4,5) t RC Address tAA CE tACE tBA LB , UB t BHZ tBLZ OE t CHZ tOE tCLZ tOHZ t OH tOLZ Dout High-Z High-Z Data Valid Notes : 1. WE is high for read cycle. 2.Device is continuously selected OE =low, CE =low, LB or UB =low. 3.Address must be valid prior to or coincident with CE =low, LB or UB =low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL=5pF. Transition is measured±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ, tBHZ is less than tBLZ, tOHZ is less than tOLZ. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 6 P80049 UTRON UT62L12816(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5,6) tW C Address tAW CE t CW t AS tW P tW R WE tBW LB , UB t W HZ t OW High-Z Dout (4) tDW tDH (4) Din Data Valid WRITE CYCLE 2 ( CE Controlled) (1,2,5,6) tW C A ddress tA W CE tW R tA S tC W tW P WE tB W LB , U B tW H Z D out H igh-Z (4) tD W tD H D in D ata V alid UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 7 P80049 UTRON UT62L12816(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 WRITE CYCLE 3 ( LB , UB Controlled) (1,2,5,6) tWC Address tAW CE tAS tCW tWR tWP WE tBW LB , UB tWHZ High-Z Dout tDW Din tDH Data Valid Notes : 1. WE , CE , LB , UB must be high during all address transitions. 2.A write occurs during the overlap of a low CE , low WE , LB or UB =low. 3.During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE , LB , UB low transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 8 P80049 UTRON UT62L12816(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 DATA RETENTION CHARACTERISTICS (TA = -40℃ to 85℃) PARAMETER Vcc for Data Retention SYMBOL VDR Data Retention Current IDR Chip Disable to Data Retention Time Recovery Time tCDR TEST CONDITION CE ≧VCC-0.2V Vcc=1.5V CE ≧VCC-0.2V See Data Retention Waveforms (below) tR -L - LL MIN. 1.5 TYP. - MAX. 3.6 UNIT V 0 - 50 5 - µA µA ms 5 - - ms DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) ( CE controlled) VDR ≧ 1.5V VCC Vcc(min.) Vcc(min.) tCDR CE VIH tR CE ≧ VCC-0.2V VIH Low Vcc Data Retention Waveform (2) ( LB , UB controlled) VDR ≧ 1.5V VCC Vcc(min.) Vcc(min.) tCDR LB,UB VIH tR LB,UB ≧ VCC-0.2V UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 9 VIH P80049 UTRON UT62L12816(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 PACKAGE OUTLINE DIMENSION θ 44-pin 400mil TSOP-Ⅱ Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L 2D y Θ DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.00 1.20 0.05 0.15 0.95 1.00 1.05 0.30 0.35 0.45 0.12 0.21 18.313 18.415 18.517 11.854 11.836 11.838 10.058 10.180 10.282 0.800 0.40 0.50 0.60 0.805 0.00 0.076 o o 5 0 DIMENSIONS IN INCHS MIN. NOM. MAX. 0.039 0.047 0.002 0.006 0.037 0.039 0.041 0.012 0.014 0.018 0.0047 0.083 0.721 0.725 0.728 0.460 0.466 0.470 0.398 0.400 0.404 0.0315 0.0157 0.020 0.0236 0.0317 0.000 0.003 o o 0 5 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 10 P80049 UTRON Rev. 1.1 UT62L12816(I) 128K X 16 BIT LOW POWER CMOS SRAM 48-pin 6mm × 8mm TFBGA Package Outline Dimension UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 11 P80049 UTRON UT62L12816(I) 128K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 ORDERING INFORMATION INDUSTRIAL TEMPERATURE PART NO. UT62L12816MC-55LI UT62L12816MC-55LLI UT62L12816MC-70LI UT62L12816MC-70LLI UT62L12816MC-100LI UT62L12816MC-100LLI UT62L12816BS-55LI UT62L12816BS-55LLI UT62L12816BS-70LI UT62L12816BS-70LLI UT62L12816BS-100LI UT62L12816BS-100LLI STANDBY CURRENT (µA) max. TA = 0℃ to 50℃ 20 3 20 3 20 3 20 3 20 3 20 3 ACCESS TIME (ns) 55 55 70 70 100 100 55 55 70 70 100 100 PACKAGE 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 48 PIN TFBGA 48 PIN TFBGA 48 PIN TFBGA 48 PIN TFBGA 48 PIN TFBGA 48 PIN TFBGA ORDERING INFORMATION (for lead free product) INDUSTRIAL TEMPERATURE PART NO. UT62L12816MCL-55LI UT62L12816MCL-55LLI UT62L12816MCL-70LI UT62L12816MCL-70LLI UT62L12816MCL-100LI UT62L12816MCL-100LLI UT62L12816BSL-55LI UT62L12816BSL-55LLI UT62L12816BSL-70LI UT62L12816BSL-70LLI UT62L12816BSL-100LI UT62L12816BSL-100LLI STANDBY CURRENT (µA) max. TA = 0℃ to 50℃ 20 3 20 3 20 3 20 3 20 3 20 3 ACCESS TIME (ns) 55 55 70 70 100 100 55 55 70 70 100 100 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 12 PACKAGE 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 48 PIN TFBGA 48 PIN TFBGA 48 PIN TFBGA 48 PIN TFBGA 48 PIN TFBGA 48 PIN TFBGA P80049 UTRON Rev. 1.1 UT62L12816(I) 128K X 16 BIT LOW POWER CMOS SRAM This page is left blank intentionally. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 13 P80049