UTRON UT62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.4 REVISION HISTORY REVISION Preliminary Rev. 0.5 Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 DESCRIPTION Original. Released DATE Mar, 2001 Jun 21,2001 1. The symbols CE# and OE# and WE# are revised as. CE and OE and WE . 2. Separate Industrial and Consumer SPEC. 3. Add access time 55ns range. Aug 3,2001 Add STSOP package Mar 25,2002 Add SOP package 1. Revised 36-pin TFBGA package outline dimension： a、 Rev. 1.2 : ball diameter=0.3mm May 3,2002 b、 Rev. 1.3 : ball diameter=0.35mm 2. Revised DC ELECTRICAL CHARACTERISTICS： c、 Revised VIH as 2.2V 1. Revised Operation surrent : -Icc(max) 45/35/25mA 40/30/25mA -Icc(Typ) 30/25/20mA 30/20/16mA 2. Revised Standby current : 20/3uA 20/2uA 3. Revised VOH(Typ) : NA 2.7V May 8,2003 4. Add VIH(max)=VCC+2.0V for pulse width less than 10ns. VIL(min)=VSS-2.0V for pulse width less than 10ns. 5. Revised AC Table tOHZ* characteristics 6. Add order information for lead free product UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 P80051 UTRON UT62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.4 FEATURES GENERAL DESCRIPTION Fast Access time : 55/70/100ns CMOS Low power operating Operating current : 40/30/25mA (Icc max.) Standby current : 20µA (typ.) L-version 2µA (typ.) LL-version Single 2.7V~3.6V power supply Operating Temperature : Commercial : 0℃~70℃ Extended : -20℃~80℃ All inputs and outputs TTL compatible Fully static operation Three state outputs Data retention voltage : 1.5V (min) Package : 32-pin 450 mil SOP 32-pin 8mm × 20mm TSOP-Ⅰ 32-pin 8mm × 13.4mm STSOP 36-pin 6mm × 8mm TFBGA The UT62L5128 is a 4,194,304-bit low power CMOS static random access memory organized as 524,288 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology. The UT62L5128 operates from a wide range 2.7V~3.6V power supply and supports extended operating temperature range. The UT62L5128 is designed for high density and low power memory applications. The device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.5V. FUNCTIONAL BLOCK DIAGRAM A0-A18 DECODER 512K × 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O Vcc Vss I/O1-I/O8 CE OE WE CONTROL CIRCUIT UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 2 P80051 UTRON UT62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.4 PIN CONFIGURATION A18 1 32 Vcc A16 2 31 A15 A14 3 30 A17 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE A0 12 21 I/O8 I/O1 13 20 I/O7 I/O2 14 19 I/O6 I/O3 15 18 I/O5 Vss 16 17 I/O4 A A0 A1 NC A3 A6 A8 B I/O5 A2 WE A4 A7 I/O1 C I/O6 NC A5 D Vss Vcc E Vcc Vss F I/O7 G I/O8 H I/O2 A17 A18 I/O3 OE CE A16 A15 I/O4 A9 A10 A11 A12 A13 A14 1 2 3 4 5 6 SOP TFBGA A11 A9 A8 A13 WE A17 A15 Vcc A18 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O8 PIN DESCRIPTION I/O7 I/O6 SYMBOL A0 - A18 I/O1 - I/O8 I/O5 I/O4 Vss I/O3 I/O2 CE I/O1 WE OE Vcc Vss NC A0 A1 A2 A3 DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Power Supply Ground No Connection TSOP-1 / STSOP UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 3 P80051 UTRON UT62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.4 ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to VSS Commercial Operating Temperature Extended Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 secs) SYMBOL VTERM TA TA TSTG PD IOUT Tsolder RATING -0.5 to 4.6 0 to 70 -20 to 80 -65 to 150 1 50 260 UNIT V ℃ ℃ ℃ W mA ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: WE X H H L CE H L L L I/O OPERATION OE X H L X SUPPLY CURRENT High – Z High – Z DOUT DIN ISB, ISB1 ICC , ICC1 , ICC2 ICC , ICC1 , ICC2 ICC , ICC1 , ICC2 H = VIH, L=VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V, TA =0℃ to 70℃ / -20℃ to 80℃(E)) PARAMETER Power Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Operating Power Supply Current Average Operating Current SYMBOL VCC *1 VIH ＊2 VIL ILI ILO VOH VOL TEST CONDITION VSS ≦VIN ≦VCC VSS ≦VI/O ≦VCC, Output Disable IOH= - 1mA IOL= 2.1mA Cycle time=Min,100% duty ICC II/O =0mA , CE = VIL Icc1 100% duty, II/O=0mA, CE ≦0.2, other pins at 0.2V or Vcc-0.2V Icc2 Standby Current(TTL) ISB1 CE =VIH ,other pins = VIH or VIL Standby Current(CMOS) ISB1 CE ≧VCC-0.2V other pins at 0.2V or Vcc-0.2V 55 70 100 TCycle= 1µs Tcycle= 500ns -L -LL MIN. 2.7 2.2 - 0.2 -1 -1 2.2 - TYP. 3.0 2.7 30 20 16 MAX. UNIT 3.6 V Vcc+0.3 V 0.6 V 1 µA 1 µA V 0.4 V 40 mA 30 mA 25 mA - 4 5 mA - 8 10 mA - 0.3 0.5 mA - 20 80 µA - 2 20 µA Notes: 1. Overshoot : Vcc+2.0v for pulse width less than 10ns. 2. Undershoot : Vss-2.0v for pulse width less than 10ns. 3. Overshoot and Undershoot are sampled, not 100% tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 4 P80051 UTRON UT62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.4 CAPACITANCE (TA=25℃, f=1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 5ns 1.5V CL = 30pF+1TTL, IOH/IOL = -1mA/2.1mA AC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V , TA =0℃ to 70℃ / -20℃ to 80℃(E)) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change SYMBOL tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH UT62L5128-55 MIN. MAX. 55 55 55 30 10 5 20 20 10 - UT62L5128-70 MIN. MAX. 70 70 70 35 10 5 25 25 10 - UT62L5128-100 MIN. MAX. 100 100 100 50 10 5 30 30 10 - UT62L5128-55 MIN. MAX. 55 50 50 0 45 0 25 0 5 30 UT62L5128-70 MIN. MAX. 70 60 60 0 55 0 30 0 5 30 UT62L5128-100 MIN. MAX. 100 80 80 0 70 0 40 0 5 40 UNIT ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High Z SYMBOL tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* UNIT ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 5 P80051 UTRON UT62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.4 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA tOH Dout tOH Previous data valid Data Valid READ CYCLE 2 ( CE and OE Controlled) (1,3,4,5) t RC Address tAA CE tACE OE tCHZ tOE tOHZ tCLZ tOLZ Dout t OH High-Z Data Valid High-Z Notes : 1. WE is high for read cycle. 2.Device is continuously selected OE =low, CE =low. 3.Address must be valid prior to or coincident with CE =low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL=5pF. Transition is measured±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 6 P80051 UTRON UT62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.4 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5,6) tW C Address tAW CE t CW t AS tW P tW R WE t W HZ Dout tOW High-Z (4) (4) tDW Din t DH Data Valid WRITE CYCLE 2 ( CE Controlled) (1,2,5,6) tW C A ddress tA W CE tW R tA S tC W tW P WE tW H Z D out H igh-Z (4) tD W D in tD H D ata V alid UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 7 P80051 UTRON UT62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.4 Notes : 1. WE , CE must be high during all address transitions. 2.A write occurs during the overlap of a low CE , low WE . 3.During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE low transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. DATA RETENTION CHARACTERISTICS (TA = 0℃ to 70℃ / -20℃ to 80℃(E)) PARAMETER Vcc for Data Retention SYMBOL VDR Data Retention Current IDR Chip Disable to Data Retention Time Recovery Time tCDR TEST CONDITION CE ≧ VCC-0.2V Vcc=1.5V CE ≧ VCC-0.2V See Data Retention Waveforms (below) tR -L - LL MIN. 1.5 - TYP. 1 0.5 MAX. 3.6 50 20 UNIT V µA µA 0 - - ms 5 - - ms DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform ( CE controlled) VDR ≧ 1.5V VCC Vcc(min.) Vcc(min.) tCDR CE VIH tR CE ≧ VCC-0.2V UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 8 VIH P80051 UTRON UT62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.4 PACKAGE OUTLINE DIMENSION 32-pin 450 mil SOP Package Outline Dimension UNIT SYMBOL A A1 A2 b D E E1 e L L1 S y Θ INCH(BASE) MM(REF) 0.118 (MAX) 0.004 (MIN) 0.111 (MAX) 0.016 (TYP) 0.817 (MAX) 0.445 ±0.005 0.555 ±0.012 0.050 (TYP) 0.0347 ±0.008 0.055 ±0.008 0.026 (MAX) 0.004 (MAX) o o 0 ~10 2.997 (MAX) 0.102 (MIN) 2.82 (MAX) 0.406 (TYP) 20.75 (MAX) 11.303 ±0.127 14.097 ±0.305 1.270 (TYP) 0.881 ±0.203 1.397 ±0.203 0.660 (MAX) 0.101 (MAX) o o 0 ~10 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 9 P80051 UTRON UT62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.4 32-pin 8mm x 13.4mm STSOP Package Outline Dimension HD cL 32 16 17 b E e 1 "A" Seating Plane D 16 y 17 0.254 A2 A GAUGE PLANE A1 0 SEATING PLANE L1 "A" DATAIL VIEW 1 32 UNIT SYMBOL A A1 A2 b D E e HD L1 y Θ INCH(BASE) MM(REF) 0.047 (MAX) 0.004 ±0.002 0.039 ±0.002 0.008 ±0.001 0.465 ±0.004 0.315 ±0.004 0.020 (TYP) 0.528 ±0.008 0.0315 ±0.004 0.003 (MAX) o o 0 ∼5 1.20 (MAX) 0.10 ±0.05 1.00 ±0.05 0.200 ±0.025 11.800 ±0.100 8.000 ±0.100 0.50 (TYP) 13.40 ±0.20. 0.80 ±0.10 0.076 (MAX) o o 0 ∼5 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 10 P80051 UTRON UT62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.4 32-pin 8mm x 20mm TSOP-Ⅰ Package Outline Dimension HD C L 32 b E e 1 16 17 Seating Plane "A" y D 17 A A2 16 0.254 A1 0 GAUGE PLANE SEATING PLANE 32 1 "A" DETAIL VIEW L1 UNIT SYMBOL A A1 A2 b D E e HD L1 y Θ INCH(BASE) MM(REF) 0.047 (MAX) 0.004 ±0.002 0.039 ±0.002 0.008 + 0.002 - 0.001 0.724 ±0.004 0.315 ±0.004 0.020 (TYP) 0.787 ±0.008 0.0315 ±0.004 0.003 (MAX) o o 0 ∼5 1.20 (MAX) 0.10 ±0.05 1.00 ±0.05 0.20 + 0.05 -0.03 18.40 ±0.10 8.00 ±0.10 0.50 (TYP) 20.00 ±0.20 0.80 ±0.10 0.076 (MAX) o o 0 ∼5 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 11 P80051 UTRON UT62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.4 36-pin 6mm x 8mm TFBGA Package Outline Dimension UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 12 P80051 UTRON UT62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.4 ORDERING INFORMATION COMMERCIAL TEMPERATURE PART NO. UT62L5128SC-55L UT62L5128SC-55LL UT62L5128SC-70L UT62L5128SC-70LL UT62L5128LC-55L UT62L5128LC-55LL UT62L5128LC-70L UT62L5128LC-70LL UT62L5128LS-55L UT62L5128LS-55LL UT62L5128LS-70L UT62L5128LS-70LL UT62L5128BS-55L UT62L5128BS-55LL UT62L5128BS-70L UT62L5128BS-70LL ACCESS TIME (ns) 55 55 70 70 55 55 70 70 55 55 70 70 55 55 70 70 STANDBY CURRENT (µA) typ. 20 2 20 2 20 2 20 2 20 2 20 2 20 2 20 2 ACCESS TIME (ns) 55 55 70 70 55 55 70 70 55 55 70 70 55 55 70 70 STANDBY CURRENT (µA) typ. 20 2 20 2 20 2 20 2 20 2 20 2 20 2 20 2 PACKAGE 32 PIN SOP 32 PIN SOP 32 PIN SOP 32 PIN SOP 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA EXTENDED TEMPERATURE PART NO. UT62L5128SC-55LE UT62L5128SC-55LLE UT62L5128SC-70LE UT62L5128SC-70LLE UT62L5128LC-55LE UT62L5128LC-55LLE UT62L5128LC-70LE UT62L5128LC-70LLE UT62L5128LS-55LE UT62L5128LS-55LLE UT62L5128LS-70LE UT62L5128LS-70LLE UT62L5128BS-55LE UT62L5128BS-55LLE UT62L5128BS-70LE UT62L5128BS-70LLE UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 13 PACKAGE 32 PIN SOP 32 PIN SOP 32 PIN SOP 32 PIN SOP 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA P80051 UTRON UT62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.4 ORDERING INFORMATION (for lead free product) COMMERCIAL TEMPERATURE PART NO. UT62L5128SCL-55L UT62L5128SCL-55LL UT62L5128SCL-70L UT62L5128SCL-70LL UT62L5128LCL-55L UT62L5128LCL-55LL UT62L5128LCL-70L UT62L5128LCL-70LL UT62L5128LSL-55L UT62L5128LSL-55LL UT62L5128LSL-70L UT62L5128LSL-70LL UT62L5128BSL-55L UT62L5128BSL-55LL UT62L5128BSL-70L UT62L5128BSL-70LL ACCESS TIME (ns) 55 55 70 70 55 55 70 70 55 55 70 70 55 55 70 70 STANDBY CURRENT (µA) typ. 20 2 20 2 20 2 20 2 20 2 20 2 20 2 20 2 ACCESS TIME (ns) 55 55 70 70 55 55 70 70 55 55 70 70 55 55 70 70 STANDBY CURRENT (µA) typ. 20 2 20 2 20 2 20 2 20 2 20 2 20 2 20 2 PACKAGE 32 PIN SOP 32 PIN SOP 32 PIN SOP 32 PIN SOP 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA EXTENDED TEMPERATURE PART NO. UT62L5128SCL-55LE UT62L5128SCL-55LLE UT62L5128SCL-70LE UT62L5128SCL-70LLE UT62L5128LCL-55LE UT62L5128LCL-55LLE UT62L5128LCL-70LE UT62L5128LCL-70LLE UT62L5128LSL-55LE UT62L5128LSL-55LLE UT62L5128LSL-70LE UT62L5128LSL-70LLE UT62L5128BSL-55LE UT62L5128BSL-55LLE UT62L5128BSL-70LE UT62L5128BSL-70LLE UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 14 PACKAGE 32 PIN SOP 32 PIN SOP 32 PIN SOP 32 PIN SOP 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN TSOP-Ⅰ 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA P80051 UTRON UT62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.4 This Page Is Left Blank Intentionally. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 15 P80051