W3E32M64S-XSBX 32Mx64 DDR SDRAM Advanced* FEATURES BENEFITS DDR SDRAM rate = 200, 250, 266 Package: • 208 Plastic Ball Grid Array (PBGA), 13 x 22mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (one per byte) DQS edge-aligned with data for READs; center-aligned with data for WRITEs DLL to align DQ and DQS transitions with CLK Four internal banks for concurrent operation Data mask (DM) pins for masking write data (one per byte) Programmable IOL/IOH option Auto precharge option Auto Refresh and Self Refresh Modes Commercial, Industrial and Military TemperatureRanges Organized as 32M x 64 Weight: W3E32M64S-XSBX - 2 grams typical 73% SPACE SAVINGS vs. TSOP -43% Space Savings vs FPBGA Reduced part count 21% I/O reduction vs TSOP -13% I/O reduction vs FPBGA Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Laminate interposer for optimum TCE match Upgradeable to 64M x 64 density (contact factory for information) * Advanced data sheet describes a product that is developmental, non-qualified and is subject to change of cancellation without notice. GENERAL DESCRIPTION The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 4 chips containing 536,870,912 bits. Each chip is internally configured as a quad-bank DRAM. The 256MB DDR SDRAM uses a double data rate ar chi tec ture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256MB DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data tansfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bi-directional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver.strobe transmitted by the DDR SDRAM during READs and by the memory contoller during WRITEs. DQS is edge-aligned with data for READs and centeraligned with data for WRITEs. Each chip has two data strobes, one for the lower byte and one for the upper byte. The 256MB DDR SDRAM operates from a differential clock (CK and CK); the crossing of CK going HIGH and CK going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 January 2004 Rev. 0 1 W3E32M64S-XSBX DENSITY COMPARISONS TSOP Approach (mm) 11.9 22.3 66 TSOP 11.9 11.9 66 TSOP 11.9 66 TSOP Actual Size W3E32M64S-XSBX 66 TSOP S A V I N G S 13 22 Area 4 x 265mm = 1060mm I/O Count 4 x 66 pins = 264 pins 2 2 CSP Approach (mm) 12.5 10.0 10.0 10.0 10.0 60 FBGA 60 FBGA 60 FBGA 60 FBGA 286mm2 73% 208 Balls 21% Actual Size W3E32M64S-XSBX 13 22 Area 4 x 125mm = 500mm I/O Count 4 x 60 balls = 240 balls 2 is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst access. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 2 S A V I N G S 286mm2 43% 208 Balls 13% The pipelined, multibank architecture of DDR SDRAMs al lows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a powersaving power-down mode. FUNCTIONAL DESCRIPTION Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-12 select the row). The address bits registered coincident with the READ or WRITE 2 W3E32M64S-XSBX FIG. 1 PIN CONFIGURATION TOP VIEW 1 A 2 3 4 5 6 7 8 9 10 11 VCC VSS VCCQ VCCQ VSS VCCQ VCCQ VSS VCC VSS B VCCQ VSS CS2 CS0 CKE2 CKE0 CAS2 RAS0 RAS2 VSS VCCQ C VSS CK0 CK2 CK0 CK2 DQML0 DQML2 CAS0 WE0 WE2 VSS D DQMH2 DQMH0 DQSH2 DQSH0 DQ8 DQ40 DQ5 DQ39 DQ7 DQSL2 DQSL0 E DQ41 DQ9 DQ10 DQ42 DQ43 DQ12 DQ3 DQ36 DQ4 DQ38 DQ6 F DQ44 DQ11 DQ13 DQ45 DQ14 DQ33 DQ1 DQ34 DQ2 DQ37 DQ35 G NC NC DQ15 DQ47 DQ46 VSS DQ32 DQ0 NC NC NC H DNU NC NC DNU NC VCC NC NC NC NC NC J VCCQ A12 BA1 A0 VCC VSS VCCQ A7 A9 DNU* VCC K VSS A10 A3 VCCQ VSS VREF VSS VCCQ A4 A11 VSS L VCC A2 BA0 A1 VCCQ VSS VCC A6 A8 A5 VCCQ M NC NC NC NC NC VCC NC NC NC NC DNU N NC NC NC DQ16 DQ48 VSS DQ63 DQ31 DQ62 NC NC P DQ22 DQ52 DQ18 DQ50 DQ17 DQ49 DQ30 DQ61 DQ29 DQ59 DQ27 R DQ23 DQ54 DQ21 DQ19 DQ51 DQ60 DQ28 DQ58 DQ26 DQ57 DQ25 T DQSL1 DQSL3 DQ55 DQ53 DQ20 DQ56 DQ24 DQMH3 DQMH1 DQSH1 DQSH3 U VSS CAS3 WE3 WE1 DQML3 DQML1 CK1 CK3 CK1 CK3 VSS V VCCQ VSS CAS1 RAS3 RAS1 CKE1 CKE3 CS1 CS3 VSS VCCQ W VSS VCC VSS VCCQ VCCQ VSS VCCQ VCCQ VSS VCC VSS * pin J10 is reserved for signal A13 on future upgrades. NOTE: DNU = Do Not Use; to be left unconnected for future upgrades. NC = Not Connected Internally. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 3 W3E32M64S-XSBX FIG. 2 FUNCTIONAL BLOCK DIAGRAM command are used to select the starting column location for the burst access. WE0 RAS 0 CAS 0 WE RAS CAS VREF VREF A0-12 A0-12 BA0-1 CLK0 CLK0 CKE0 CS0 DQML0 DQMH0 BA0-1 CLK CLK CKE CS DQML DQMH DQSL0 DQSH0 DQSL DQSH U0 DQ0 = Y = Y = Y = Y = Y = Y DQ15 DQ0 = Y = Y = Y = Y = Y = Y DQ15 WE1 RAS 1 CAS 1 WE RAS CAS VREF A0-12 CLK1 CLK1 CKE1 CS1 DQML1 DQMH1 BA0-1 CLK CLK CKE CS DQML DQMH DQSL1 DQSH1 DQSL DQSH U1 DQ0 = Y = Y = Y = Y = Y = Y DQ15 DQ16 = Y = Y = Y = Y = Y = Y DQ31 WE2 RAS 2 CAS 2 WE RAS CAS VREF A0-12 CLK2 CLK2 CKE2 CS2 DQML2 DQMH2 DQSL2 DQSH2 BA0-1 CLK CLK CKE CS DQML DQMH DQSL DQSH U2 DQ0 = Y = Y = Y = Y = Y = Y DQ15 DQ32 = Y = Y = Y = Y = Y = Y DQ47 WE3 RAS 3 CAS 3 WE RAS CAS VREF A0-12 CLK3 CLK3 CKE3 CS3 DQML3 DQMH3 DQSL3 DQSH3 BA0-1 CLK CLK CKE CS DQML DQMH DQSL DQSH U3 DQ0 = Y = Y = Y = Y = Y = Y DQ15 DQ48 = Y = Y = Y = Y = Y = Y DQ63 White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. INITIALIZATION DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VCC and VCCQ simultaneously, and then to VREF (and to the system VTT). VTT must be applied after VCCQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied any time after VCCQ but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VCC is applied. After CKE passes through VIH, it will transition to an SSTL_2 signal and remain as such until power is cycled. Maintaining an LVCMOS LOW level on CKE during power-up is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to applying an executable command. Once the 200µs delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE REGISTER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the DLL, followed by another LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hundred clock cycles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed (tRFC must be satisfied.) Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e., to program operating pa ram e ters without resetting the DLL) is 4 W3E32M64S-XSBX required. Following these requirements, the DDR SDRAM is ready for normal operation. REGISTER DEFINITION MODE REGISTER The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure 3. The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. (Except for bit A8 which is self clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The Mode Register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the sub se quent op er a tion. Vi o lat ing either of these requirements will result in unspecified operation. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode. BURST LENGTH Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 3. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two; by A2-Ai White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 when the burst length is set to four (where Ai is the most significant column address for a given configuration); and by A3-Ai when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. BURST TYPE Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1. READ LATENCY The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n+m. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. OPERATING MODE The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A12 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7-A12 are reserved 5 W3E32M64S-XSBX for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. EXTENDED MODE REGISTER The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, and QFC. These functions are controlled via the bits shown in Figure 5. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL. The extended mode register must be loaded when all COMMANDS The Truth Table provides a quick reference of available commands. This is followed by a written description of each command. DESELECT The DESELECT function (CS High) prevents new commands from being executed by the DDR SDRAM. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) TABLE 2 - CAS LATENCY ALLOWABLE OPERATING FREQUENCY (MHz) CAS LATENCY = 2 CAS LATENCY = 2.5 -200 ≤ 75 ≤ 100 -250 ≤ 100 ≤ 125 -266 ≤ 100 ≤ 133 SPEED up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles with CKE high must occur before a READ command can be issued. banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. OUTPUT DRIVE STRENGTH The normal full drive strength for all outputs are specified to be SSTL2, Class II. The DDR SDRAM supports an option for reduced drive. This option is intended for the support of the lighter load and/or point-to-point environments. The selection of the reduced drive strength will alter the DQs and DQSs from SSTL2, Class II drive strength to a reduced drive strength, which is approximately 54 percent of the SSTL2, Class II drive strength. DLL ENABLE/DISABLE When the part is running without the DLL enabled, device functionality may be altered. The DLL must be enabled for normal operation. DLL enable is required during power- White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 The NO OPERATION (NOP) command is used to perform a NOP to the selected DDR SDRAM (CS is LOW while RAS, CAS, and WE are high). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The Mode Registers are loaded via inputs A0-12. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-12 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs 6 W3E32M64S-XSBX TABLE 1 - BURST DEFINITION FIG. 3 MODE REGISTER DEFINITION Burst Starting Column Length Address 2 BA1 A12 A11 A10 A9 BA0 A8 A7 A6 A5 A3 A4 A2 A1 A0 Address Bus 4 Mode Register (Mx) 0* 0* Operating Mode CAS Latency BT Burst Length * M14 and M13 (BA0 and BA1 must be "0, 0" to select the base mode register (vs. the extended mode register). Burst Length M2 M1 M0 M3 = 0 0 0 Reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved Reserved Reserved Burst Type M3 0 Sequential 1 Interleaved M6 M5 M4 8 M3 = 1 0 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 1 1 1 Reserved M12 M11 M10 M9 M8 M7 M6-M0 0 0 0 0 0 0 Valid Normal Operation 0 0 0 0 1 0 Valid Normal Operation/Reset DLL - - - - - - - A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 NOTES: 1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column within the block. 2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column within the block. 3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting column within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. Operating Mode All other states reserved selects the bank, and the address provided on inputs A0-9 selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the READ burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the WRITE burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. Input data WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-9 White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 7 W3E32M64S-XSBX FIG. 5 EXTENDED MODE REGISTER DEFINITION FIG. 4 CAS LATENCY T0 T1 T2 READ NOP NOP T2n T3 T3n BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus CLK CLK COMMAND NOP 01 11 DS Operating Mode DLL Extended Mode Register (Ex) CL = 2 DQS DQ T0 T1 T2 T2n T3 E1 CLK READ NOP NOP DLL 0 Enable 1 T3n CLK COMMAND E0 NOP Disable Drive Strength 0 Normal 1 Reduced CL = 2.5 DQS DQ E8 E7 E6 E5 E4 E3 E2 E1, E0 Operating Mode 0 0 0 0 0 0 0 0 0 0 0 Valid Reserved - - - - - - - - - - - - Reserved E12 E11 E10 E9 Burst Length = 4 in the cases shown Shown with nominal tAC and nominal tDSDQ DATA TRANSITIONING DATA 1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register) 2. The QFC function is not supported. DON'T CARE appearing on the D/Qs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. PRECHARGE AUTO PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the AUTO PRECHARGE is a feature which performs the same individual-bank PRECHARGE function described above, but with out re quir ing an explicit command. This is accomplished by using A10 to enable AUTO PRECHARGE in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. AUTO PRECHARGE is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. The device sup ports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. AUTO PRECHARGE ensures that the precharge is initiated at the earliest valid stage within a burst. This “earliest valid stage” is determined as if an explicit White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 8 W3E32M64S-XSBX TRUTH TABLE - COMMANDS (NOTE 1) NAME (FUNCTION) CS RAS CAS WE DESELECT (NOP) (9) H X X X ADDR X NO OPERATION (NOP) (9) L H H H X ACTIVE (Select bank and activate row) ( 3) L L H H Bank/Row READ (Select bank and column, and start READ burst) (4) L H L H Bank/Col WRITE (Select bank and column, and start WRITE burst) (4) L H L L Bank/Col BURST TERMINATE (8) L H H L X PRECHARGE (Deactivate row in bank or banks) ( 5) L L H L Code AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7) L L L H X LOAD MODE REGISTER (2) L L L L Op-Code TRUTH TABLE - DM OPERATION NAME (FUNCTION) WRITE ENABLE (10) DM L DQs Valid WRITE INHIBIT (10) H X NOTES: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A0-12 define the op-code to be written to the selected Mode Register. BA0, BA1 select either the mode register (0, 0) or the extended mode register (1, 0). 3. A0-12 provide row address, and BA0, BA1 provide bank address. 4. A0-9 provide column address; A10 HIGH enables the auto precharge feature (non persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide bank address. 5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.” 6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 9. DESELECT and NOP are functionally interchangeable. 10. Used to mask write data; provided coincident with the corresponding data. precharge command was issued at the earliest possible time, without violating tRAS (MIN).The user must not issue another command to the same bank until the precharge time (tRP) is completed. controller. This makes the address bits “Don’t Care” during an AUTO RE FRESH command. Each DDR SDRAM requires AUTO REFRESH cycles at an average interval of 7.8125µs (maximum). BURST TERMINATE To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 9 x 7.8125µs (70.3µs). This maximum absolute interval is to allow future support for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles, without allowing excessive drift in tAC between updates. The BURST TERMINATE command is used to truncate READ bursts (with auto precharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated. The open page which the READ burst was terminated from remains open. AUTO REFRESH AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS-BEFORE-RAS (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (High) during The addressing is generated by the internal refresh White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 9 W3E32M64S-XSBX the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends tRFC later. ABSOLUTE MAXIMUM RATINGS Parameter Voltage on VCC, VCCQ Supply relative to Vss -1 to 3.6 Voltage on I/O pins relative to Vss -1 to 3.6 Operating Temperature TA (Mil) -55 to +125 Operating Temperature TA (Ind) -40 to +85 Storage Temperature, Plastic -55 to +150 SELF REFRESH* The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled upon exiting SELF REFRESH (200 clock cycles must then occur before a READ command can be issued). Input signals except CKE are “Don’t Care” during SELF REFRESH. VREF voltage is also required for the full duration of SELF REFRESH. NOTE:Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (NOTE 13) Parameter The procedure for exiting self refresh requires a sequence of commands. First, CK and CK must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR, because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for tXSNR time, then a DLL Reset and NOPs for 200 additional clock cycles before applying any other command. * Self refresh available in commercial and industrial temperatures only. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 Unit V V °C °C °C Symbol Max Unit Input Capacitance: CLK CI1 TBD pF Addresses, BA0-1 Input Capacitance CA TBD pF Input Capacitance: All other input-only pins CI2 TBD pF Input/Output Capacitance: I/Os CIO TBD pF BGA THERMAL RESISTANCE Description Symbol Max Units Notes Junction to Ambient (No Airflow) Theta JA TBD °C/W 1 Junction to Ball Theta JB TBD °C/W 1 Junction to Case (Top) Theta JC TBD °C/W 1 NOTE 1: Refer to "PBGA Thermal Resistance Correlation" (Application Note) at www.whiteedc.com in the application notes section for modeling conditions. 10 W3E32M64S-XSBX DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1, 6) (VCC = +2.5V ±0.2V; TA = -55°C TO +125°C) Parameter/Condition Symbol Supply Voltage I/O Supply Voltage Units VCC Min 2.3 Max 2.7 V VCCQ 2.3 2.7 V Input Leakage Current: Any input 0V ≤ VIN ≤ VCC (All other pins not under test = 0V) II -2 2 µA Input Leakage Address Current (All other pins not under test = 0V) II -8 8 µA Output Leakage Current: I/Os are disabled; 0V ≤ VOUT ≤ VCCQ IOZ -5 5 µA Output Levels: Full drive option High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) IOH IOL -16.8 16.8 - mA mA Output Levels: Reduced drive option High Current (VOUT = VCCQ - 0.763V, minimum VREF, minimum VTT) Low Current (VOUT = 0.763V, maximum VREF, maximum VTT) IOHR IOLR -9 9 - mA mA I/O Reference Voltage VREF 0.49 x VCCQ 0.51 x VCCQ V I/O Termination Voltage VTT VREF - 0.04 VREF + 0.04 V ICC SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14) (VCC = +2.5V ±0.2V; TA = -55°C TO +125°C) MAX 250MHz Parameter/Condition Symbol OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs 266MHz 200MHz Units ICC0 520 460 mA ICC1 640 580 mA ICC2P 20 20 mA ICC2F 180 160 mA ICC3P 140 120 mA ICC3N 200 180 mA ICC4R 660 580 mA ICC4W 620 540 mA tRC = tRC (MIN) (27, 50) ICC5 1,160 1,120 mA tRC = 7.8125µs (27, 50) ICC5A 40 40 mA Standard (11) ICC6 20 20 mA ICC7 1,620 1,400 mA changing once per clock cyle; Address and control inputs changing once every two clock cycles; (22, 48) OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle (22, 48) PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW; (23, 32, 50) IDLE STANDBY CURRENT: CS = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM (51) ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW (23, 32, 50) ACTIVE STANDBY CURRENT: CS = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle (22) OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA (22, 48) OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle (22) AUTO REFRESH CURRENT SELF REFRESH CURRENT: CKE 0.2V OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, tRC =tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ or WRITE commands. (22, 49) White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 11 W3E32M64S-XSBX ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS (NOTES 1-5, 14-17, 33) Parameter 266 MHz CL 2.5 250 MHz CL2.5 200 CL 2 200 MHz CL2 200 MHz CL2.5 150 MHz CL2 Symbol Min Max Min Max Min Max Access window of DQs from CLK/CLK tAC -0.75 +0.75 -0.8 +0.8 -0.8 +0.8 ns CLK high-level width (30) tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK tCK CLK low-level width (30) Units tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK (2.5) 7.5 13 8 13 10 13 ns tCK (2) 10 13 10 13 13 15 ns DQ and DM input hold time relative to DQS (26, 31) tDH 0.5 0.6 0.6 ns DQ and DM input setup time relative to DQS (26, 31) tDS 0.5 0.6 0.6 ns DQ and DM input pulse width (for each input) (31) tDIPW 1.75 2 2 Access window of DQS from CLK/CLK tDQSCK -0.75 DQS input high pulse width tDQSH 0.35 DQS input low pulse width tDQSL 0.35 DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26) tDQSQ Write command to first DQS latching transition tDQSS 0.75 DQS falling edge to CLK rising - setup time tDSS 0.2 0.2 0.2 tCK DQS falling edge from CLK rising - hold time tDSH 0.2 0.2 0.2 tCK Half clock period (34) tHP tCH,tCL tCH,tCL tCH,tCL Data-out high-impedance window from CLK/CLK (18, 42) tHZ Clock cycle time CL = 2.5 (45, 52) CL = 2 (45, 52) +0.75 -0.8 +0.8 0.35 1.25 +0.75 1.25 0.75 +0.8 ns tCK 0.35 0.6 0.75 ns +0.8 0.35 0.35 0.5 -0.8 tCK 0.6 ns 1.25 tCK ns +0.8 ns Data-out low-impedance window from CLK/CLK (18, 43) tLZ -0.75 -0.8 -0.8 ns Address and control input hold time (fast slew rate) (14) tIHF 0.90 1.1 1.1 ns Address and control input setup time (fast slew rate) (14) tISF 0.90 1.1 1.1 ns Address and control input hold time (slow slew rate) (14) tIHS 1 1.1 1.1 ns Address and control input setup time (slow slew rate) (14) tISS 1 1.1 1.1 ns LOAD MODE REGISTER command cycle time tMRD 15 16 16 ns DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26) tQH tHP-tQHS tHP-tQHS tHP-tQHS Data hold skew factor tQHS 0.75 ns 1 1 ns ACTIVE to PRECHARGE command (35) tRAS 40 ACTIVE to READ with Auto precharge command (46) tRAP 20 20 20 ns 120,000 40 120,000 40 120,000 ns ACTIVE to ACTIVE/AUTO REFRESH command period tRC 65 70 70 ns AUTO REFRESH command period (50) tRFC 75 80 80 ns ACTIVE to READ or WRITE delay tRCD 20 20 20 ns PRECHARGE command period tRP 20 20 20 ns DQS read preamble (42) tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK ACTIVE bank a to ACTIVE bank b command tRRD 15 15 15 ns DQS write preamble tWPRE 0.25 0.25 0.25 tCK DQS write preamble setup time (20, 21) tWPRES 0 DQS write postamble (19) tWPST 0.4 Write recovery time tWR 15 15 15 ns Internal WRITE to READ command delay tWTR 1 1 1 tCK Data valid output window (25) na 0 0.6 0 0.4 tQH - tDQSQ 0.6 tQH - tDQSQ ns 0.6 tQH - tDQSQ ns tREFC Average periodic refresh interval (23) tREFI Terminating voltage delay to VDD tVTD 0 0 0 Exit SELF REFRESH to non-READ command tXSNR 75 80 80 ns Exit SELF REFRESH to READ command tXSRD 200 200 200 tCK 12 70.3 tCK REFRESH to REFRESH command interval (23) White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 70.3 0.4 7.8 7.8 70.3 µs 7.8 µs ns W3E32M64S-XSBX NOTES: 1. All voltages referenced to VSS. 2. Tests for AC timing, ICC, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: 15. 16. VTT 17. 50Ω 18. Reference Point 30pF Output (VOUT) 19. 4. AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CLK/CLK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not exceed ±2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. VID is the magnitude of the difference between the input level on CLK and the input level on CK. 9. The value of VIX and VMP are expected to equal VCCQ/2 of the transmitting device and must track variations in the DC level of the same. 10. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time with the outputs open. 11. Enables on-chip refresh and address counters. 12. ICC specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 13. This parameter is not tested but guaranteed by design. tA = 25°C, F= 1 MHz 14. For slew rates less than 1V/ns and greater than or equal to 0.5 V.ns. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50 ps per 20. 21. 22. 23. 24. 25. 26. FIG. A PULL-DOWN CHARACTERISTICS each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other than CK/CK is VREF. Inputs are not recognized as valid until VREF stabilizes once initialized, including SELF REFRESH mode, VREF must be powered within specified range. Exception: during the period before VREF stabilizes, CKE < 0.3 x VCCQ is recognized as LOW. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). The intent of the Don't Care state after completion of the postamble is the DQSdriven signal should either be high, low, or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high (above VIHDC(MIN) then it must not transition low (below VIHDC) prior to tDQSH(MIN). This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. MIN (tRC or tRFC) for ICC measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for ICC measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. The refresh period 64ms. This equates to an average refresh rate of 7.8125µs. However, an AUTO REFRESH command must be asserted at least once every 70.3µs ; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. Referenced to each output group: LDQS with DQ0-DQ7; and UDQS with DQ8DQ15 of each chip. FIG. B PULL-UP CHARACTERISTICS 0 160 -20 Maximum 140 Minimum -40 120 Nominal high IOUT (mA) 100 IOUT (mA) Nominal low -60 80 Nominal low 60 Minimum -80 -100 Nominal high -120 -140 40 -160 20 -180 Maximum -200 0 0.0 0.5 1.0 1.5 2.0 0.0 2.5 1.0 1.5 VCCQ - VOUT (V) VOUT (V) White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 0.5 13 2.0 2.5 W3E32M64S-XSBX a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure C. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure C. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure D. d) The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure D. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 V, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 V. 39. The voltage levels used are derived from a minimum VCC level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 40. VIH overshoot: VIH(MAX) = VCCQ+1.5V for a pulse width < 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width < 3ns and the pulse width cannot be greater than 1/3 of the cycle rate. 41. VCC and VCCQ must track each other. 42. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition. 43. tRPST end point and tRPRE bigin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). 44. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are 0 volts, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin. 45. The current part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or LOW. 47. Random addressing changing 50% of data changing at every transfer. 48. Random addressing changing 50% of data changing at every transfer. 49. Random addressing changing 100% of data changing at every transfer. 50. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tRFC has been satisfied. 27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 28. To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b) Reach at least the target AC level. c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). 29. The Input capacitance per pin group will not differ by more than this maximum amount for any given device. 30. CK and CK input slew rate must be > 1V/ns (>2V/ns differentially). 31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. 32. VCC must not vary more than 4% if CKE is not active while any bank is active. 33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. 34. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK inputs, collectively during bank active. 35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfied prior to the internal precharge command being issued. 36. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9 volts, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is more positive. The average cannot be below the 2.5V minimum. 37. Normal Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure A. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure A. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure B. d) The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 Volt, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 Volt. 38. Reduced Output Drive Curves: FIG. D PULL-UP CHARACTERISTICS FIG. C PULL-DOWN CHARACTERISTICS 0 80 Maximum -10 70 60 Nominal high 40 IOUT (mA) IOUT (mA) 50 Nominal low 30 -20 Minimum -30 Nominal low -40 -50 Minimum Nominal high 20 -60 10 -70 0 -80 Maximum 0.0 0.5 1.0 1.5 2.0 0.0 2.5 White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 0.5 1.0 1.5 VCCQ - VOUT (V) VOUT (V) 14 2.0 2.5 W3E32M64S-XSBX 51. ICC2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. ICC2Q is similar to ICC2F except ICC2Q specifies the address and control inputs to remain stable. Although ICC2F, ICC2N, and ICC2Q are similar, ICC2F is “worst case.” 52. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles before any READ command. 52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20 MHz. Any noise above 20 MHz at the DRAM generated from any source other than that of the DRAM itself may not exceed the DC coltage range of 2.6V + 100mV. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 15 W3E32M64S-XSBX PACKAGE DIMENSION: 208 PLASTIC BALL GRID ARRAY (PBGA) BOTTOM VIEW 208 x Ø 0.6 (0.024) NOM 11 10 9 8 7 6 5 4 3 2 1 A B C D E 18.0 (0.709) NOM H J K L M 1.0 (0.039) NOM 22.15 (0.872) MAX F G N P R T U V W 1.0 (0.039)NOM 0.5 (0.020) 10.0 (0.394) NOM 2.11 (0.083) MAX 13.15 (0.518) MAX ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES ORDERING INFORMATION W 3E 32M 64 S - XXX SB X WHITE ELECTRONIC DESIGNS CORP. DDR SDRAM CONFIGURATION, 32M x 64 2.5V Power Supply DATA RATE (MHz) 200 = 200MHz 250 = 250MHz 266 = 266MHz PACKAGE: SB = 208 Plastic Ball Grid Array (PBGA) DEVICE GRADE: M = Military I = Industrial C = Commercial -55°C to +125°C -40°C to +85°C 0°C to +70°C White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 16 W3E32M64S-XSBX Document Title 32M x 64 DDR SDRAM Multi-Chip Package Revision History Rev # History Release Date Status Rev 0 Initial Release January 2004 Advanced White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 17