MICRON MT9VDDT1672A

128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
DDR SDRAM
DIMM
MT9VDDT1672A - 128MB
MT9VDDT3272A - 256MB
For the latest data sheet, please refer to the Micronâ Web
site: www.micron.com/moduleds
Features
Figure 1: 184-Pin DIMM (MO-206)
• JEDEC-standard 184-pin dual in-line memory
module (DIMM)
• Fast data transfer rates PC1600, PC2100, or PC2700
• Utilizes 200 MT/s, 266 MT/s, and 333MT/s DDR
SDRAM components
• ECC-optimized pinout 128MB (16 Meg x 72), 256MB
(32 Meg x 72)
• VDD= VDDQ= +2.5V
• VDDSPD = +2.3V to +3.6V
• +2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs (CK and CK#)
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.6µs (128MB), 7.8125µs (256MB) maximum
average periodic refresh interval
• Serial Presence-Detect (SPD) with EEPROM
• Programmable READ CAS latency
OPTIONS
MARKING
• Package
Unbuffered
184-pin DIMM (Gold)
184-pin DIMM (Lead-Free)
• Frequency/CAS Latency
6ns, 333 MT/s (167 MHz), CL = 2.5
7.5ns, 266 MT/s (133 MHz ), CL = 2
7.5ns, 266 MT/s (133 MHz ), CL = 2
7.5ns, 266 MT/s (133 MHz ), CL = 2.5
10ns, 200 MT/s (100 MHz ), CL = 2
• Self Refresh
Standard
Low Power
Table 1:
A
G
Y
-335
-262
-26A
-265
-202
None
L
Address Table
128MB
256MB
4K
Refresh Count
4K (A0–A11)
Row Addressing
Device Bank Addressing 4 (BA0, BA1)
16 Meg x 8
Device Configuration
1K (A0–A9)
Column Addressing
1 (S0#)
Module Rank Addressing
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
1
8K
8K (A0–A12)
4 (BA0, BA1)
32 Meg x 8
1K (A0–A9)
1 (S0#)
©2003 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Table 2:
Part Numbers and Timing Parameters
PART NUMBER
MT9VDDT1672A(L)G-335__
MT9VDDT1672A(L)Y-335__
MT9VDDT1672A(L)G-262__
MT9VDDT1672A(L)Y-262__
MT9VDDT1672A(L)G-26A__
MT9VDDT1672A(L)Y-26A__
MT9VDDT1672A(L)G-265__
MT9VDDT1672A(L)Y-265__
MT9VDDT1672A(L)G-202__
MT9VDDT1672A(L)Y-202__
MT9VDDT3272A(L)G-335__
MT9VDDT3272A(L)Y335__
MT9VDDT3272A(L)G-262__
MT9VDDT3272A(L)Y-262__
MT9VDDT3272A(L)G-26A__
MT9VDDT3272A(L)Y-26A__
MT9VDDT3272A(L)G-265__
MT9VDDT3272A(L)Y-265__
MT9VDDT3272A(L)G-202__
MT9VDDT3272A(L)Y-202__
MODULE
DENSITY
CONFIGURATION
MODULE
BANDWIDTH
MEMORY CLOCK/
DATA RATE
LATENCY
(CL - tRCD - tRP)
128MB
128MB
128MB
128MB
128MB
128MB
128MB
128MB
128MB
128MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
6ns/333 MT/s
6ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
6ns/333 MT/s
6ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT9VDDT3272AG-265A1
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Table 3:
Pin Assignment
(184-Pin DIMM Front)
Table 4:
Pin Assignment
(184-Pin DIMM Back)
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
93
VSS
94
DQ4
95
DQ5
96
VDD
97
DQS9
98
DQ6
99
DQ7
100
VSS
101
NC
102
NC
103
NC
104
VDD
105 DQ12
106 DQ13
107 DQS10
108
VDD
109 DQ14
110 DQ15
111
NC
112
VDD
113
NC
114 DQ20
115 NC/A12
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDD
CK1
CK1#
VSS
DQ10
DQ11
CKE0
VDD
DQ16
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
DQ17
DQS2
VSS
A9
DQ18
A7
VDD
DQ19
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VDD
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
DQS8
A0
CB2
VSS
CB3
BA1
DQ32
VDD
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
VDD
WE#
DQ41
CAS#
VSS
DQS5
DQ42
DQ43
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDD
NC
DQ48
DQ49
VSS
CK2#
CK2
VDD
DQS6
DQ50
DQ51
VSS
NC
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
VSS
DQ21
A11
DQS11
VDD
DQ22
A8
DQ23
VSS
A6
DQ28
DQ29
VDD
DQS12
A3
DQ30
VSS
DQ31
CB4
CB5
VDD
CK0
CK0#
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
VSS
DQS17
A10
CB6
VDD
CB7
VSS
DQ36
DQ37
VDD
DQS13
DQ38
DQ39
VSS
DQ44
RAS#
DQ45
VDD
S0#
NC
DQS14
VSS
DQ46
162 DQ47
163
NC
164
VDD
165 DQ52
166 DQ53
167
NC
168
VDD
169 DQS15
170 DQ54
171 DQ55
172
VDD
173
NC
174 DQ60
175 DQ61
176
VSS
177 DQS16
178 DQ62
179 DQ63
180
VDD
181
SA0
182
SA1
183
SA2
184 VDDSPD
NOTE:
Pin 115 is No Connect (128MB), and A12 (256MB).
Figure 2: 184-Pin DIMM Pinouts
FRONT VIEW
U10
U1
U2
U3
U4
U5
U6
PIN 52
PIN 1
U7
PIN 53
Indicates a VDD pin
U8
U9
PIN 92
Indicates a VSS pin
BACK VIEW
No Components This Side
PIN 184
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
PIN 145
PIN 144
3
PIN 93
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Table 5:
Pin Descriptions
Refer to Pin Assignment Tables on page 3 for pin number and symbol information
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
1
63, 65, 154
VREF
WE#, CAS#, RAS#
Input
Input
16, 17, 75, 76, 137, 138
CK0, CK0#, CK1,
CK1#, CK2, CK2#
Input
21
CKE0
Input
157
S0#
Input
52, 59
BA0, BA1
Input
27, 29, 32, 37, 41, 43, 48,
115 (256MB), 118, 122, 125,
130, 141
A0-A11 (128MB)
A0-A12 (256MB)
Input
92
SCL
Input
181, 182, 183
SA0-SA2
Input
91
SDA
Input/Output
44, 45, 49, 51, 134, 135,
142, 144
5, 14, 25, 36, 47, 56, 67, 78,
86, 97, 107, 119, 129, 140,
149, 159, 169, 177
CB0-CB7
Input/Output
DQS0-DQS17
Input/Output
SSTL_2 reference voltage.
Command Inputs: WE#, RAS#, and CAS# (along with S#)
define the command being entered.
Clocks: CK and CK# are differential clock inputs. All
address and control input signals are sampled on the
crossing of the positive edge of CK and negative edge of
CK#. Output data (DQs and DQS) is referenced to the
crossings of CK and CK#.
Clock Enable: CKE activates (HIGH) and deactivates (LOW)
internal clock signals, device input buffers, and output
drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device
banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any
device bank). CKE0 is synchronous for all functions except
for disabling outputs, which is achieved asynchronously.
CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE)
are disabled during POWERDOWN. Input buffers
(excluding CKE) are disabled during SELF REFRESH. CKE is
an SSTL_2 input but will detect an LVCMOS LOW level
after VDD is applied.
Chip Select: S# enables (registered LOW) and disable
(registered HIGH) the command decoder. All commands
are masked when S# is registered HIGH. S# is considered
part of the command code.
Bank Addresses: BA0 and BA1 define to which device
bank an ACTIVE, READ, WRITE or PRECHARGE command
is being applied.
Address Inputs: Sampled during the ACTIVE command
(row-address) and READ/WRITE command (columnaddress, with A10 defining auto precharge) to select one
location out of the memory array in the respective device
device bank. A10 is sampled during a PRECHARGE
command to determine whether the PRECHARGE applies
to one device bank (A10 LOW) or all device banks (A10
HIGH). The address inputs also provide the op-code
during a MODE REGISTER SET command.
Serial Clock for Presence-Detect: SCL is used to
synchronize the presence-detect data transfer to and
from the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Serial Presence-Detect Data: SDA is a bidirectional pin
used to transfer addresses and data into and out of the
presence- detect portion of the module.
Data I/Os: Check bits. ECC, one-bit error detection and
correction.
Data Strobes: Output with read data, input with write
data. Edge- aligned with read data, centered in write
data. Used to capture write data.
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Table 5:
Pin Descriptions (Continued)
Refer to Pin Assignment Tables on page 3 for pin number and symbol information
2, 4, 6, 8, 12, 13, 19, 20, 23,
24, 28, 31, 33, 35, 39, 40,
53, 55, 57, 60, 61, 64, 68,
69, 72, 73, 79, 80, 83, 84,
87, 88, 94, 95, 98, 99, 105,
106, 109, 110, 117, 121,
131, 133, 146, 147, 150,
151, 153, 155, 161, 162,
165, 166, 170, 171, 174,
175, 178, 179
7, 15, 22, 30, 38, 46, 54, 62,
70, 77, 85, 96, 104, 108,
112, 120, 128, 136, 143,
148, 156, 164, 168, 172, 180
3, 11, 18, 26, 34, 42, 50, 58,
66, 74, 81, 89, 93, 100, 116,
124, 132, 139, 145, 152,
160, 176
184
DQ0-DQ63
Input/Output
VDD
Supply
Power Supply: +2.5V +0.2V.
(Please see note 50 on page 21.)
VSS
Supply
Ground.
VDDSPD
Supply
9, 10, 71, 82, 90, 101, 102,
103, 111, 113, 115 (128MB),
158, 163, 167, 173
NC
–
Serial EEPROM positive power supply: +2.3V to +3.6V.
This supply is isolated from the VDD/VDDQ supply.
No Connects.
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
5
Data I/Os: Data bus.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Figure 3: Functional Block Diagram
-26A, -265, -202 Speed Optimized
S0#
DQS0
DQS4
DQS9
DQS13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ
DQ
DQ
DQ U1
DQ
DQ
DQ
DQ
DQS1
DQS5
DQS10
DQS14
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM CS# DQS
DQ
DQ
DQ
U2
DQ
DQ
DQ
DQ
DQ
DQS2
DQS6
DQS11
DQS15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM CS# DQS
DQ
DQ
DQ
DQ U3
DQ
DQ
DQ
DQ
DQS3
DQS7
DQS12
DQS16
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS# DQS
DQ
DQ
DQ
DQ U4
DQ
DQ
DQ
DQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM CS# DQS
DQ
DQ
DQ
U5
DQ
DQ
DQ
DQ
DQ
DQS8
DM CS# DQS
DQ
DQ
DQ
U6
DQ
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS# DQS
DQ
DQ
DQ
DQ U7
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM CS# DQS
DQ
DQ
DQ
U8
DQ
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS# DQS
DQ
DQ
DQ
U9
DQ
DQ
DQ
DQ
DQ
120
DQS17
BA0, BA1
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
BA0, BA1: SDRAMs
A0-A11 (128MB)
A0-A11: SDRAMs
A0-A12 (256MB)
A0-A12: SDRAMs
RAS#
CAS#
RAS#: SDRAMs
WE#
WE#: SDRAMs
CKE0
CKE0: SDRAMs
120
CK0
CK0#
SDRAM
X3
4.5pF
CK1
CK1#
SDRAM
X3
4.5pF
120
SDRAM
X3
CK2
CK2#
4.5pF
VDDSPD
VDDQ
VDD
SPD/EEPROM
SDRAMs
SDRAMs
VREF
VSS
SDRAMs
SDRAMs
SERIAL PD
CAS#: SDRAMs
SCL
WP
U10
A0
A1
A2
SDA
SA0 SA1 SA2
NOTE:
1.
2.
All resistor values are 22W unless otherwise specified.
Per industry standard, Micron modules utilize various component speed grades, as
referenced in the module part number guide at www.micron.com/numberguide.
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
6
U1 - U9 = MT46V16M8TG DDR SDRAMs 128MB Module
U1 - U9 = MT46V32M8TG DDR SDRAMs 256MB Module
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Figure 4: Functional Block Diagram
-335 Speed Optimized
S0#
DQS0
DQS4
DQS9
DQS13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ
DQ
DQ
DQ U1
DQ
DQ
DQ
DQ
DQS1
DQS5
DQS10
DQS14
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM CS# DQS
DQ
DQ
DQ
U2
DQ
DQ
DQ
DQ
DQ
DQS2
DQS6
DQS11
DQS15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM CS# DQS
DQ
DQ
DQ
DQ U3
DQ
DQ
DQ
DQ
DQS3
DQS7
DQS12
DQS16
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS# DQS
DQ
DQ
DQ
DQ U4
DQ
DQ
DQ
DQ
DQS8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
BA0, BA1
A0-A12 (256MB)
RAS#
CAS#
WE#
CKE0
5.1
5.1
5.1
5.1
5.1
5.1
DM CS# DQS
DQ
DQ
DQ
U5
DQ
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS# DQS
DQ
DQ
DQ
DQ U6
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM CS# DQS
DQ
DQ
DQ
U7
DQ
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS# DQS
DQ
DQ
DQ
U8
DQ
DQ
DQ
DQ
DQ
120
DQS17
A0-A11 (128MB)
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
120
CK0
CK0#
DM CS# DQS
DQ
DQ
DQ
U9
DQ
DQ
DQ
DQ
DQ
CK1
CK1#
SDRAM
X3
3pF
SDRAM
X3
3pF
120
CK2
CK2#
SDRAM
X3
3pF
VDDSPD
VDDQ
VDD
BA0, BA1: SDRAMs
SPD/EEPROM
SDRAMs
SDRAMs
VREF
VSS
A0-A11: SDRAMs
A0-A12: SDRAMs
RAS#: SDRAMs
SDRAMs
SDRAMs
SERIAL PD
CAS#: SDRAMs
SCL
WP
WE#: SDRAMs
U10
A0
A1
A2
SDA
CKE0: SDRAMs
SA0 SA1 SA2
NOTE:
1.
2.
All resistor values are 22W unless otherwise specified.
Per industry standard, Micron modules utilize various component speed grades, as
referenced in the module part number guide at www.micron.com/numberguide.
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
7
U1 - U9 = MT46V16M8TG DDR SDRAMs 128MB Module
U1 - U9 = MT46V32M8TG DDR SDRAMs 256MB Module
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
General Description
allows for concurrent operation, thereby providing
high effective bandwidth by hiding row precharge and
activation time.
An auto refresh mode is provided, along with a powersaving power-down mode. All inputs are compatible
with the JEDEC Standard for SSTL_2. All outputs are
SSTL_2, Class II compatible. For more information
regarding DDR SDRAM operation, refer to the 128Mb
and 256Mb DDR SDRAM component data sheet.
The MT9VDDT1672A and MT9VDDT3272A are
high-speed CMOS, dynamic random-access, 128MB
and 256MB memory modules organized in a x72 (ECC)
configuration. These modules use internally configured quad-bank DDR SDRAM devices.
These DDR SDRAM modules use a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2nprefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins.
A single read or write access for the DDR SDRAM module effectively consists of a single 2n-bit wide, oneclock-cycle data transfer at the internal DRAM core
and two corresponding n-bit wide, one-half-clockcycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.
These DDR SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going
HIGH and CK# going LOW will be referred to as the
positive edge of CK. Commands (address and control
signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as
to both edges of CK.
Read and write accesses to the DDR SDRAM modules are burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which is
then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE
command are used to select the device bank and row
to be accessed (BA0, BA1 select device bank; A0–A11
select device row for the 128MB module, A0–A12 select
device row for the 256MB module). The address bits
registered coincident with the READ or WRITE command are used to select the device bank and the starting device column location for the burst access.
These DDR SDRAM modules provide for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at
the end of the burst access.
As with standard SDR SDRAM modules, the pipelined, multibank architecture of DDR SDRAM modules
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
Serial Presence-Detect Operation
These DDR SDRAM modules incorporate serial
presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile
storage device contains 256 bytes. The first 128 bytes
can be programmed by Micron to identify the module
type and various SDRAM organizations and timing
parameters. The remaining 128 bytes of storage are
available for use by the customer. System READ/
WRITE operations between the master (system logic)
and the slave EEPROM device (DIMM) occur via a
standard I2C bus using the DIMM’s SCL (clock) and
SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write
protect (WP) is tied to ground on the module, permanently disabling hardware write protect.
Mode Register Definition
The mode register is used to define the specific
mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency and an operating mode, as shown in Figure 5, Mode Register Definition Diagram, on page 9.
The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and
will retain the stored information until it is programmed again or the device loses power (except for
bit A8, which is self-clearing).
Reprogramming the mode register will not alter the
contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating the subsequent operation. Violating either of these requirements will result in
unspecified operation.
Mode register bits A0–A2 specify the burst length,
A3 specifies the type of burst (sequential or interleaved), A4–A6 specify the CAS latency, and A7–A11
(for the 128MB module) or A7–A12 (for the 256MB
module) specify the operating mode.
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Burst Length
Figure 5: Mode Register Definition
Diagram
Read and write accesses to the DDR SDRAM are
burst oriented, with the burst length being programmable, as shown in Figure 5, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-A9 when the burst length is set to two,
by A2–A9 when the burst length is set to four and by
A3–A9 when the burst length is set to eight (where A9 is
the most significant column address bit for a given
configuration).
The remaining (least significant)
address bit(s) is (are) used to select the starting location within the block. The programmed burst length
applies to both read and write bursts.
128MB Module
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
13 12
0* 0*
8
6
5
4
1 0
11 10 9
7
3
2
Operating Mode
CAS Latency BT Burst Length
Mode Register (Mx)
* M13 and M12 (BA0 and BA1)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
256MB Module
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
14 13 12 11 10 9
8
Operating Mode
0* 0*
7
6
5
4
1 0
3
2
CAS Latency BT Burst Length
* M14 and M13 (BA0 and BA1)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
Mode Register (Mx)
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
Reserved
Reserved
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Reserved
Reserved
Burst Type
M3
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst
Definition Table, on page 10.
0
Sequential
1
Interleaved
CAS Latency
M6 M5 M4
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
2.5
1
1
1
Reserved
M12 M11 M10 M9 M8 M7
Read Latency
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 6, CAS
Latency Diagram, on page 10.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 7,
CAS Latency (CL) Table, on page 10, indicates the
operating frequencies at which each CAS latency setting can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
Address Bus
Burst Length
Burst Type
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
Address Bus
M6-M0
Operating Mode
0
0
0
0
0
0
Valid
Normal Operation
0
0
0
0
1
0
Valid
Normal Operation/Reset DLL
-
-
-
-
-
-
-
All other states reserved
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7–A11
(128MB), or A7–A12 (256MB) each set to zero, and bits
A0–A6 set to the desired values. A DLL reset is initiated
by issuing a MODE REGISTER SET command with bits
A7 and A9–A11 (128MB), or A7 and A9–A12 (256MB)
each set to zero, bit A8 set to one, and bits A0–A6 set to
the desired values. Although not required by the
Micron device, JEDEC specifications recommend
when a LOAD MODE REGISTER command is issued to
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Figure 6: CAS Latency Diagram
reset the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operating mode.
All other combinations of values for A7–A11, or A7–
A12 are reserved for future use and/or test modes. Test
modes and reserved states should not be used because
unknown operation or incompatibility with future versions may result.
T0
T1
T2
READ
NOP
NOP
T2n
T3
T3n
CK#
CK
COMMAND
NOP
CL = 2
DQS
Table 6:
STARTING
BURST
COLUMN
LENGTH ADDRESS
2
4
8
DQ
Burst Definition Table
A0
0
1
A1 A0
0
0
0
1
1
0
1
1
A2 A1 A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
ORDER OF ACCESSES WITHIN A
BURST
TYPE =
SEQUENTIAL
CK#
T1
T2
READ
NOP
NOP
T2n
T3
T3n
CK
TYPE =
INTERLEAVED
COMMAND
NOP
CL = 2.5
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
DQS
DQ
Burst Length = 4 in the cases shown
Shown with nominal tAC, tDQSCK, and tDQSQ
TRANSITIONING DATA
Table 7:
DON’T CARE
CAS Latency (CL) Table
ALLOWABLE OPERATING
FREQUENCY (MHZ)
NOTE:
1. For a burst length of two, A1–Ai select the twodata-element block; A0 selects the first access
within the block.
2. or a burst length of four, A2–Ai select the fourdata-element block; A0–A1 select the first access
within the block.
3. For a burst length of eight, A3–Ai select the eightdata-element block; A0–A2 select the first access
within the block.
4. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
5. i = 11 for 128MB module,
i = 12 for 256MB module
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
T0
SPEED
CL = 2
CL = 2.5
-335
-26A
-265
-202
N/A
75 £ f £ 133
75 £ f £ 100
75 £ f £ 100
75 £ f £ 167
75 £ f £ 133
75 £ f £ 133
75 £ f £125
Extended Mode Register
The extended mode register controls functions
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and output drive strength. These functions are controlled via
the bits shown in Figure 7, Extended Mode Register
Definition Diagram, on page 11. The extended mode
register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power. The
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Figure 7: Extended Mode Register
Definition Diagram
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode register (BA0/BA1 both low) to reset the DLL.
The extended mode register must be loaded when
all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified operation.
128MB Module
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
13 12 11 10
01 11
DLL Enable/Disable
9
8 7 6
5 4
Operating Mode
3
22
1
0
Address Bus
Extended Mode
Register (Ex)
DS DLL
256MB Module
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The DLL must be enabled for normal operation.
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is
enabled, 200 clock cycles must occur before a READ
command can be issued.
8 7 6
5
14 13 12 11 10 9
Operating Mode
01 11
E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E22
4
3
22
1
0
Extended Mode
Register (Ex)
DS DLL
E1, E0
Address Bus
E0
DLL
0
Enable
1
Disable
E1
Drive Strength
0
Normal
Operating Mode
0
0
0
0
0
0
0
0
0
0
0
Valid
Reserved
–
–
–
–
–
–
–
–
–
–
–
–
Reserved
NOTE:
1. E13 and E12 (128MB module), or E14 and E13
(256MB Module) (BA1 and BA0) must be “0, 1” to
select the Extended Mode Register (vs. the base
Mode Register).
2. The QFC# option is not supported.
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Commands
The Truth Tables below provides a general reference
of available commands. For a more detailed descrip-
Table 8:
tion of commands and operations, refer to the 128Mb
and 256Mb DDR SDRAM component data sheets.
Truth Table – Commands
Notes: 1
NAME (FUNCTION)
CS#
H
L
L
L
L
L
L
L
L
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
RAS# CAS#
X
H
L
H
H
H
L
L
L
X
H
H
L
L
H
H
L
L
WE#
ADDR
NOTES
X
H
H
H
L
L
L
H
L
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
Op-Code
2
2
3
4
4
5
6
7, 8
9
NOTE:
1.
2.
3.
4.
5.
6.
7.
8.
9.
CKE is HIGH for all commands shown except SELF REFRESH.
DESELECT and NOP are functionally interchangeable.
BA0–BA1 provide device bank address and A0–A11 (128MB) or A0–A12 (256MB) provide device row address.
BA0–BA1 provide device bank address; A0–A9 provide device column address; A10 HIGH enables the auto precharge
feature (nonpersistent), and A10 LOW disables the auto precharge feature.
Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for
read bursts with auto precharge enabled and for write bursts.
A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and
BA0–BA1 are “Don’t Care.”
This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
Internal refresh counter controls device row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;
BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (for 128MB
module) or A0–A12 (for 256MB module) provide the op-code to be written to the selected mode register.
Table 9:
Truth Table – DM Operation
Used to mask write data; provided coincident with the corresponding data
NAME (FUNCTION)
WRITE Enable
WRITE Inhibit
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
12
DM
DQS
L
H
Valid
X
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Voltage on VDD Supply
Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on VDDQ Supply
Relative to VsSS . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on VREF and Inputs
Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on I/O Pins
Relative to VSS . . . . . . . . . . . . -0.5V to VDDQ +0.5V
Operating Temperature,
TA (ambient) . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C
Storage Temperature (plastic) . . . . . . -55°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9W
Short Circuit Output Current. . . . . . . . . . . . . . . . 50mA
Table 10: DC Electrical Characteristics and Operating Conditions
Notes: 1–5, 14, 50; notes appear on pages 18–21; 0°C £ TA £ +70°C
PARAMETER/CONDITION
Supply Voltage
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
INPUT LEAKAGE CURRENT: Any input 0V £
VIN £ VDD, VREF pin 0V £ VIN £ 1.35V (All
other pins not under test = 0V)
SYMBOL
Command/Address,
RAS#, CAS#, WE#,
CKE, S#
CK, CK#
DM
DQ, DQS
VDDQ
VDDQ
VREF
VTT
VIH(DC)
VIL(AC)
IL
OUTPUT LEAKAGE CURRENT:
(DQs are disabled; 0V £ VOUT £ VDDQ)
OUTPUT LEVELS:
High Current (VOUT = VDDQ - 0.373V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)
MIN
MAX
2.3
2.7
2.3
2.7
0.49 x VDDQ 0.51 x VDDQ
VREF - 0.04 VREF + 0.04
VREF + 0.15
VDD + 0.3
-0.3
VREF - 0.15
-18
18
IL
IL
UNITS
NOTES
V
V
V
V
V
V
µA
32, 36
32, 36, 39
6, 39
7, 39
25
25
49
IOZ
-6
-2
-5
6
2
5
µA
µA
µA
49
49
49
IOH
IOL
-16.8
16.8
–
–
mA
mA
33, 36
34
Table 11: AC Input Operating Conditions
Notes: 1–5, 12, 14, 50; notes appear on pages 18–21; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V +0.2V
PARAMETER/CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
I/O Reference Voltage
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
SYMBOL
MIN
MAX
UNITS
NOTES
VIH(AC)
VIL(AC)
VREF(AC)
VREF + 0.310
–
0.49 x VDDQ
–
VREF - 0.310
0.51 x VDDQ
V
V
V
25, 35
25, 35
6
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Table 12: IDD Specifications and Conditions (128MB)
DRAM components only
Notes: 1–5, 8, 10, 12, 50; notes appear on pages 18–21; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V +0.2V
MAX
PARAMETER/CONDITION
SYMBOL
-335
-262
-26A/
-265
-202
UNITS
NOTES
OPERATING CURRENT: One device bank; Active-Precharge;
t
RC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing once per clock cycle; Address and control inputs
changing once every two clock cycles;
OPERATING CURRENT: One device bank; Active-ReadPrecharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT =
0mA; Address and control inputs changing once per clock
cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device
banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
t
CK = tCK (MIN); CKE = HIGH; Address and other control
inputs changing once per clock cycle. VIN = VREF for DQ, DQS,
and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode; tCK = tCK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One
device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK
(MIN); DQ, DM, and DQS inputs changing twice per clock
cycle; Address and other control inputs changing once per
clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One device bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One device bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle
t
AUTO REFRESH CURRENT
RC = tRFC (MIN)
IDD0
TBD
TBD
945
900
mA
20, 43
IDD1
TBD
TBD
1,080
990
mA
20, 43
IDD2P
TBD
TBD
27
27
mA
21, 28, 45
IDD2F
TBD
TBD
405
315
mA
46
IDD3P
TBD
TBD
180
180
mA
21, 28, 45
IDD3N
TBD
TBD
405
315
mA
40
IDD4R
TBD
TBD
1,125
945
mA
20, 43,
24, 45
IDD4W
TBD
TBD
1,035
945
mA
20
IDD5
TBD
TBD
1,890
1,845
mA
24, 45
IDD5A
TBD
TBD
45
45
mA
24, 45
IDD6
TBD
TBD
TBD
TBD
TBD
TBD
18
9
2,925
18
9
2,475
mA
mA
mA
9
t
RC = 15.625µs
Standard
Low Power
OPERATING CURRENT: Four device bank interleaving READs
(BL=4) with auto precharge, tRC =tRC (MIN); tCK = tCK (MIN);
Address and control inputs change only during Active, READ,
or WRITE commands.
SELF REFRESH CURRENT: CKE £ 0.2V
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
14
IDD6A
IDD7
20, 44
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Table 13: IDD Specifications and Conditions (256MB)
DRAM components only
Notes: 1–5, 8, 10, 12, 50; notes appear on pages 18–21; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V +0.2V
MAX
PARAMETER/CONDITION
SYMBOL
-335
-262
-26A/
-265
-202
UNIT
S
NOTES
OPERATING CURRENT: One device bank; Active-Precharge;
t
RC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing once per clock cycle; Address and control inputs
changing once every two clock cycles;
OPERATING CURRENT: One device bank; Active-ReadPrecharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT =
0mA; Address and control inputs changing once per clock
cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device
banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
t
CK = tCK (MIN); CKE = HIGH; Address and other control
inputs changing once per clock cycle. VIN = VREF for DQ,
DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode; tCK = tCK (MIN); CKE =
LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One
device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK
(MIN); DQ, DM, and DQS inputs changing twice per clock
cycle; Address and other control inputs changing once per
clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One device bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One device bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and
DQS inputs changing twice per clock cycle
t
AUTO REFRESH CURRENT
RC = tRFC
(MIN)
IDD0
1,125
1,125
945
1,080
mA
20, 43
IDD1
1,530
1,440
1,305
1,395
mA
20, 43
IDD2P
36
36
36
36
mA
21, 28,
45
IDD2F
450
405
405
405
mA
46
IDD3P
270
225
225
270
mA
21, 28,
45
IDD3N
540
450
450
450
mA
42
IDD4R
1,575
1,350
1,350
1,575
mA
20, 43,
24, 45
IDD4W
1,395
1,215
1,215
1,710
mA
20
IDD5
2,295
2,115
2,115
2,205
mA
24, 45
IDD6
54
54
54
54
mA
24, 45
IDD7
IDD7A
IDD8
36
18
3,645
36
18
3,150
36
18
3,285
36
18
3,285
mA
mA
mA
9
t
RC = 7.8125µs
SELF REFRESH CURRENT: CKE £ 0.2V
Standard
Low Power
OPERATING CURRENT: Four device bank interleaving READs
(BL=4) with auto precharge, tRC =tRC (MIN); tCK = tCK (MIN);
Address and control inputs change only during Active,
READ, or WRITE commands.
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
15
20, 44
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Table 14: Capacitance (All Modules)
Note: 11; notes appear on pages 18–21
PARAMETER
SYMBOL
MIN
MAX
UNITS
CIO
CI 1
CI 2
CI 2
CI 2
CI 3
4.0
2.0
12.0
9
10.5
18.0
5.0
3.0
15.0
12.0
13.5
27.0
pF
pF
pF
pF
pF
pF
Input/Output Capacitance: DQs, DQSs
Input Capacitance: Command and Address, S0#
Input Capacitance: CK0, CK0# (-26A, -265, -202)
Input Capacitance: CK0, CK0# (-335)
Input Capacitance: CK1, CK1#, CK2, CK2# (-26A, -265, -202)
Input Capacitance: CKE
Table 15: Electrical Characteristics and Recommended AC Operating Conditions
Notes: 1–5, 8, 12–15, 29, 31, 50; notes appear on pages 18–21; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V
AC CHARACTERISTICS
-335
PARAMETER
SYMBOL
-26A/265
-202
MIN
MAX MIN MAX
MIN
MAX UNITS NOTES
Access window of DQ from CK/CK#
t
-0.7
+0.7
-0.75 +0.75
-0.8
+0.8
CK high-level width
t
CH
0.45
0.55
0.45
0.55
0.45
0.55
t
t
CL
0.45
0.55
0.45
0.55
0.45
0.55
t
CK (2.5)
6
13
7.5
13
8
7.5
13
7.5
13
10
AC
CK low-level width
Clock cycle time
CL = 2.5
CL = 2
t
t
CK (2)
ns
CK
26
26
13
CK
ns
13
ns
40, 47,
48
40, 47
DQ and DM input hold time relative to DQS
t
DH
0.45
0.5
0.6
ns
23, 27
DQ and DM input setup time relative to DQS
t
DS
0.45
0.5
0.6
ns
23, 27
DIPW
1.75
1.75
2
ns
27
DQSCK
-0.60
+0.60 -0.75 +0.75
-0.8
DQS input high pulse width
t
DQSH
0.35
0.35
0.35
t
DQS input low pulse width
t
0.35
0.35
0.35
t
DQS-DQ skew, DQS to last DQ valid, per group, per
access
Write command to first DQS latching transition
t
t
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
t
DQSL
0.45
DQSQ
t
DQSS
0.75
1.25
+0.8
0.5
0.75
1.25
0.6
0.75
1.25
ns
CK
ns
t
CK
CK
DQS falling edge to CK rising - setup time
t
DSS
0.2
0.2
0.2
t
DQS falling edge from CK rising - hold time
t
DSH
0.2
0.2
0.2
t
30
ns
16, 37
-0.8
ns
16, 38
0.90
1.1
ns
12
0.75
0.90
1.1
ns
12
IHS
0.80
1
1.1
ns
12
t
ISS
0.80
1
1.1
ns
12
MRD
12
t
t
t
HP
Data-out high-impedance window from CK/CK#
t
HZ
Data-out low-impedance window from CK/CK#
t
LZ
-0.70
-0.75
Address and control input hold time (fast slew rate)
t
IHF
0.75
Address and control input setup time (fast slew rate)
t
ISF
Address and control input hold time (slow slew rate)
t
Address and control input setup time (slow slew rate)
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
Data hold skew factor
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
22, 25
CK
ns
Half clock period
LOAD MODE REGISTER command cycle time
CK
t
t
t
CH, CL
+0.70
t
QH
HP - QHS
QHS
16
t
CH, CL
+0.75
15
t
0.55
t
t
t
t
CH, CL
+0.8
16
t
HP - QHS
0.75
t
ns
t
HP- QHS
1
ns
22, 23
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Table 15: Electrical Characteristics and Recommended AC Operating Conditions
(Continued)
AC CHARACTERISTICS
-335
PARAMETER
SYMBOL
MIN
70,000
40
-202
MIN
120,000
ns
31
RAS(MIN) - (burst length) *
t
CK/2)
ns
40
t
ns
60
RAS(MIN) - (burst length) *
t
CK/2)
65
70
ns
ACTIVE to READ with Auto precharge
command
128MB
RAP
ACTIVE to READ with Auto precharge
command
256MB
t
RAP
18
t
RC
120,000
40
MAX UNITS NOTES
t
t
t
ACTIVE to ACTIVE/AUTO REFRESH command period
MAX MIN MAX
42
ACTIVE to PRECHARGE command
RAS
-26A/265
AUTO REFRESH command period
t
RFC
72
75
80
ns
ACTIVE to READ or WRITE delay
t
RCD
18
20
20
ns
t
20
20
RP
18
DQS read preamble
t
RPRE
0.9
1.1
0.9
1.1
0.9
1.1
t
DQS read postamble
t
RPST
0.4
0.6
0.4
0.6
0.4
0.6
t
ACTIVE bank a to ACTIVE bank b command
t
RRD
12
15
15
WPRE
0.25
0.25
0.25
WPRES
0
0
0
PRECHARGE command period
t
DQS write preamble
DQS write preamble setup time
t
t
DQS write postamble
WPST
0.4
t
WR
15
15
15
WTR
na
1
1
1
Write recovery time
Internal WRITE to READ command delay
t
Data valid output window
t
0.6
t
QH - DQSQ
140.6
0.4
t
0.6
t
QH - DQSQ
140.6
45
ns
CK
37
CK
ns
t
CK
ns
0.4
0.6
t
CK
ns
18, 19
17
t
QH - DQSQ
140.6
CK
ns
22
µs
21
t
t
REFRESH to REFRESH command interval
128MB
t
REFRESH to REFRESH command interval
256MB
t
REFC
70.3
140.6
140.6
µs
21
Average periodic refresh interval
128MB
t
REFI
15.6
15.6
15.6
µs
21
256MB
t
REFI
7.8
7.8
µs
21
Average periodic refresh interval
Terminating voltage delay to VDD
REFC
Exit SELF REFRESH to non-READ command
t
Exit SELF REFRESH to READ command
t
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
0
0
ns
XSNR
75
75
ns
XSRD
200
200
tVTD
17
t
CK
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Notes
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC
characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for
the full voltage range specified.
3. Outputs measured with equivalent load:
12.
VTT
Output
(VOUT)
50Ω
Reference
Point
30pF
13.
4. AC timing and IDD tests may use a VIL-to-VIH
swing of up to 1.5V in the test environment, but
input timing is still referenced to VREF (or to the
crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The minimum slew rate for the input signals used to test
the device is 1V/ns in the range between VIL(AC)
and VIH(AC).
5. The AC and DC input level specifications are as
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on VREF may not exceed ±2 percent of the
DC value. Thus, from VDDQ/2, VREF is allowed
±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest VREF by-pass capacitor.
7. VTT is not applied directly to the device. VTT is a
system supply for signal termination resistors, is
expected to be set equal to VREF and must track
variations in the DC level of VREF.
8. IDD is dependent on output loading and cycle
rates. Specified values are obtained with minimum cycle time at CL = 2 for -262, -26A, and -202,
CL = 2.5 for -265 and -335 with the outputs open.
9. Enables on-chip refresh and address counters.
10. IDD specifications are tested after the device is
properly initialized, and is averaged at the defined
cycle rate.
11. This parameter is sampled. VDD = +2.5V ±0.2V,
VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, TA =
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
14.
15.
16.
17.
18.
19.
20.
21.
18
25°C, VOUT (DC) = VDDQ/2, VOUT (peak to peak) =
0.2V. DM input is grouped with I/O pins, reflecting
the fact that they are matched in loading.
Command/Address input slew rate = 0.5V/ns. For
-335 and -262, -26A, and -265 with slew rates 1V/
ns and faster, tIS and tIH are reduced to 900ps. If
the slew rate is less than 0.5V/ns, timing must be
derated: tIS has an additional 50ps per each
100mV/ns reduction in slew rate from the 500mV/
ns. tIH has 0ps added, that is, it remains constant.
If the slew rate exceeds 4.5V/ns, functionality is
uncertain.
The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is VREF.
Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF
stabilizes, CKE £ 0.3 x VDDQ is recognized as LOW.
The output timing reference level, as measured at the
timing reference point indicated in Note 3, is VTT.
t
HZ and tLZ transitions occur in the same access
time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).
The maximum limit for this parameter is not a
device limit. The device will operate with a greater
value for this parameter, but system performance
(bus turnaround) will degrade accordingly.
This is not a device limit. The device will operate
with a negative value, but system performance
could be degraded due to bus turnaround.
It is recommended that DQS be valid (HIGH or
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on tDQSS.
MIN (tRC or tRFC) for IDD measurements is the
smallest multiple of tCK that meets the minimum
absolute value for the respective parameter. tRAS
(MAX) for Idd measurements is the largest multiple of tCK that meets the maximum absolute
value for tRAS.
The refresh period 64ms. This equates to an average refresh rate of 15.625µs (128MB module)
7.8125µs (256MB module). However, an AUTO
REFRESH command must be asserted at least
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
22.
23.
24.
25.
once every 140.6µs (128MB module) or 70.3µs
(256MB module); burst refreshing or posting by
the DRAM controller greater than eight refresh
cycles is not allowed.
The valid data window is derived by achieving
other specifications - tHP (tCK/2), tDQSQ, and
t
QH (tQH = tHP - tQHS). The data valid window
derates directly porportional with the clock duty
cycle and a practical data valid window can be
derived. The clock is allowed a maximum duty
cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. Figure
8, Derating Data Valid Window (tQH - tDQSQ),
shows the derating curves for duty cycles ranging
between 50/50 and 45/55.
Each byte lane has a separate DQS, with DQ0–
DQ7.
This limit is actually a nominal value and does not
result in a fail value. CKE is HIGH during
REFRESH command period (tRFC [MIN]) else
CKE is LOW (i.e., during standby).
To maintain a valid level, the transitioning edge of
the input must:
a)Sustain a constant slew rate from the current AC
26.
27.
28.
29.
30.
level through to the target AC level, VIL(AC) or
VIH(AC).
b)Reach at least the target AC level.
c)After the AC target level is reached, continue to
maintain at least the target DC level, VIL(DC) or
VIH(DC).
CK and CK# input slew rate must be ³ 1V/ns (³
2V/ns if measured differentially).
DQ and DM input slew rates must not deviate
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to tDS and
t
DH for each 100mv/ns reduction in slew rate. If
slew rate exceeds 4V/ns, functionality is uncertain.
VDD must not vary more than 4 percent if CKE is
not active while any device bank is active.
The clock is allowed up to ±150ps of jitter. Each
timing parameter is allowed to vary by the same
amount.
t
HP (MIN) is the lesser of tCL minimum and tCH
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
Figure 8: Derating Data Valid Window
(tQH - tDQSQ)
3.8
3.750
3.700
3.6
3.400
3.4
3.350
3.650
3.600
3.550
3.500
3.300
3.450
3.400
3.250
3.200
3.2
3.100
-26A/-265 @ tCK = 10ns
-202 @ tCK = 10ns
-26A/-265 @ tCK = 7.5ns
-202 @ tCK = 8ns
TBD -335 @ tCK = 6ns
ns
3.0
2.8
2.6
3.150
2.500
2.463
2.425
3.350
2.388
2.350
2.313
2.275
3.250
3.050
3.000
2.4
3.300
2.238
2.200
2.950
2.163
2.2
2.900
2.125
2.0
1.8
50/50
49.5/50.5
49/51
48.5/52.5
48/52
47.5/53.5
47/53
46.5/54.5
46/54
45.5/55.5
45/55
Clock Duty Cycle
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
31. READs and WRITEs with auto precharge are not
allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command
being issued.
32. Any positive glitch must be less than 1/3 of the
clock cycle and not more than +400mV or 2.9V,
whichever is less. Any negative glitch must be less
than 1/3 of the clock cycle and not exceed either 300mV or 2.2V, whichever is more positive. The
DC average cannot go below 2.3V minimum.
33. Normal Output Drive Curves:
a)The full variation in driver pull-down current
from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 9, Pull-Down
Characteristics.
b)The variation in driver pull-down current
within nominal limits of voltage and temperature is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I curve
of Figure 9, Pull-Down Characteristics.
c)The full variation in driver pull-up current from
minimum to maximum process, temperature and
voltage will lie within the outer bounding lines of
the V-I curve of Figure 10, Pull-Up Characteristics.
d)The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure 10,
Pull-Up Characteristics.
e)The full variation in the ratio of the maximum to
minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
f ) The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source voltages
from 0.1V to 1.0V.
The voltage levels used are derived from a minimum VDD level and the refernced test load. In
practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values.
VIH overshoot: VIH (MAX) = VDDQ+1.5V for a pulse
width £ 3ns and the pulse width can not be greater
than 1/3 of the cycle rate. VIL undershoot: VIL (MIN)
= -1.5V for a pulse width £ 3ns and the pulse width
can not be greater than 1/3 of the cycle rate.
VDD and VDDQ must track each other.
This maximum value is derived from the referenced test load. In practice, the values obtained
in a typical terminated design may reflect up to
310ps less for tHZ (MAX) and the last DVW. tHZ
(MAX) will prevail over tDQSCK (MAX) + tRPST
(MAX) condition. tLZ (MIN) will prevail over
t
DQSCK (MIN) + tRPRE (MAX) condition.
For slew rates of greater than 1V/ns the (LZ) transition will start about 310ps earlier.
During initialzation, VDDQ, VTT, and VREF must be
equal to or less than VDD + 0.3V. Alternatively, VTT
may be 1.35V maximum during power up, even if
VDD/VDDQ are 0.0V, provided a minimum of 42
ohms of series resistance is used between the VTT
supply and the input pin.
34.
35.
36.
37.
38.
39.
Figure 9: Pull-Down Characteristics
Figure 10: Pull-Up Characteristics
0
160
-20
um
140
Maxim
Maximum
-40
120
IOUT (mA)
IOUT (mA)
80
Nominal low
60
-80
-100
Nom
-120
inal
-140
Minimum
40
Nominal high
-60
high
Nominal
100
Min
imu
-160
20
low
m
-180
-200
0
0.0
0.5
1.0
1.5
2.0
0.0
2.5
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
0.5
1.0
1.5
2.0
2.5
VDDQ - VOUT (V)
VOUT (V)
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
46. IDD2N specifies the DQ, DQS and DM to be driven
to a valid high or low logic level. IDD2Q is similar
to IDD2F except IDD2Q specifies the address and
control inputs to remain stable. Although IDD2F,
IDD2N, and IDD2Q are similar, IDD2F is “worst
case.”
47. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
48. Min tCK value at CL=2.5 in the SPD for and -26A
speeds is 0.7ns, to facilitate proper system operation.
49. Leakage number reflects the worst case leakage
possible through the module pin, not what each
memory device contributes.
50. The -335 module speed grade, using the -6R speed
device, has VDD (MIN) = 2.4V.
40. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
41. tRAP ³ tRCD.
42. For -335, -262, -26A, and -265 speed grades, IDD3N
is specified to be 35mA x (# of DDR SDRAM
devices) at 100 MHz.
43. Random addressing changing and 50 percent of
data changing at every transfer.
44. Random addressing changing and 100 percent of
data changing at every transfer.
45. CKE must be active (high) during the entire time a
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
REF later.
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
SPD Clock and Data Conventions
SPD Acknowledge
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (as
shown in Figure 11, Data Validity, and Figure 12, Definition of Start and Stop).
Acknowledge is a software convention used to indicate successful data transfers. The transmitting device,
either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Figure 12, Definition of Start and Stop).
The SPD device will always respond with an
acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will terminate further data transmissions and await the stop
condition to return to standby power mode.
SPD Start Condition
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
SPD Stop Condition
All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.
Figure 11: Data Validity
Figure 12: Definition of Start and Stop
SCL
SCL
SDA
SDA
DATA STABLE
DATA
CHANGE
DATA STABLE
START
BIT
STOP
BIT
Figure 13: Acknowledge Response from Receiver
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Table 16: EEPROM Device Select Code
Most significant bit (b7) is sent first
DEVICE TYPE IDENTIFIER
SELECT CODE
Memory Area Select Code (two arrays)
Protection Register Select Code
CHIP ENABLE
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
0
1
1
1
0
0
SA2
SA2
SA1
SA1
SA0
SA0
RW
RW
Table 17: EEPROM Operating Modes
MODE
Current Address Read
Random Address Read
Sequential Read
Byte Write
Page Write
RW BIT
WC
BYTES
1
0
1
1
0
0
VIH or VIL
VIH or VIL
VIH or VIL
VIH or VIL
VIL
VIL
1
1
1
³1
1
£ 16
INITIAL SEQUENCE
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
Figure 14: SPD EEPROM Timing Diagram
tF
t HIGH
tR
t LOW
SCL
t SU:STA
t HD:STA
t SU:DAT
t HD:DAT
t SU:STO
SDA IN
t DH
t AA
t BUF
SDA OUT
UNDEFINED
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Table 18: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION
SYMBOL
VDD
VIH
VIL
VOL
ILI
ILO
ISB
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: IOUT = 3mA
INPUT LEAKAGE CURRENT: VIN = GND to VDD
OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD
STANDBY CURRENT:
SCL = SDA = VDD - 0.3V; All other inputs = VSS or VREF
POWER SUPPLY CURRENT:
SCL clock frequency = 100 KHz
MIN
MAX
3
3.6
VDD x 0.7 VDD + 0.5
-1
VDD x 0.3
–
0.4
–
10
–
10
–
30
–
ICC
2
UNITS
V
V
V
V
µA
µA
µA
mA
Table 19: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
3.5
µs
SCL LOW to SDA data-out valid
t
AA
0.3
Time the bus must be free before a new transition can start
t
BUF
4.7
Data-out hold time
t
300
DH
t
SDA and SCL fall time
µs
ns
300
F
ns
Data-in hold time
t
HD:DAT
0
µs
Start condition hold time
t
HD:STA
4
µs
t
4
µs
Clock HIGH period
HIGH
100
t
Noise suppression time constant at SCL, SDA inputs
I
Clock LOW period
t
LOW
4.7
µs
1
µs
SCL
100
KHz
SDA and SCL rise time
t
SCL clock frequency
ns
R
t
Data-in setup time
t
SU:DAT
250
ns
Start condition setup time
t
SU:STA
4.7
µs
Stop condition setup time
t
SU:STO
4.7
µs
WRITE cycle time
t
WRC
NOTES
10
ms
1
NOTE:
1. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Table 20: Serial Presence-Detect Matrix
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes at end of SPD Matrix
BYTE
0
1
2
3
4
5
6
7
8
9
DESCRIPTION
Number of Bytes Used by Micron
Total Number of SPD Memory Bytes
Memory Type
Number of Row Addresses
Number of Column Addresses
Number of Ranks
Module Data Width
Module Data Width (Continued)
Module Voltage Interface Levels
SDRAM Cycle Time, tCK, (CAS Latency = 2.5)
(See note 1)
10
SDRAM Access From Clock, tAC
(CAS Latency = 2.5)
11
12
13
14
15
16
17
18
19
20
21
22
Module Configuration Type
Refresh Rate/Type
SDRAM Width (Primary SDRAM)
Error-Checking SDRAM Data Width
Minimum Clock Delay, Back -to- Back
Random Column Access
Burst Lengths Supported
Number of Banks on SDRAM Device
CAS Latencies Supported
CS Latency
WE Latency
SDRAM Module Attributes
SDRAM Device Attributes: General
23
SDRAM Cycle Time, tCK (CAS Latency = 2)
24
SDRAM Cycle Time, tCK (CAS Latency = 2)
(See note 1)
25
SDRAM Cycle Time, tCK (CAS Latency = 1)
SDRAM Access From CK , (CAS latency = 1)
26
27
t
Minimum Row Precharge Time, RP
28
Minimum Row Active To Row Active, tRRD
29
Minimum RAS# to CAS# Delay, tRCD
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
ENTRY (VERSION)
MT9VDDT1672A
MT9VDDT3272A
128
256
SDRAM DDR
12 or 13
10
1
72
0
SSTL 2.5V
6ns (-335)
7ns (-262/-26A)
7.5ns (-265)
8ns (-202)
0.7ns (-335)
0.75ns (-262/-265/-26A)
0.8ns (-202)
ECC
15.6 or 7.81µs/SELF
8
8
1
80
08
07
0C
0A
01
48
00
04
60
70
75
80
70
75
80
02
80
08
08
01
80
08
07
0D
0A
01
48
00
04
60
70
75
80
70
75
80
02
82
08
08
01
2, 4, 8
4
2, 2.5
0
1
Unbuffered, Diff CLK
Fast/concurrent auto
precharge
7.5ns (-335/-262/-26A)
10ns (-202/-265)
0.7ns (-335)
0.75ns (-262/-265/-26A)
0.8ns (-202)
–
0E
04
0C
01
02
20
00/C0
(See note 2)
75
A0
70
75
80
00
0E
04
0C
01
02
20
C0
75
A0
70
75
80
00
–
18ns (-335)
20ns (-262)
20ns (-202/-265/-26A)
12ns (-335)
15ns (-202/-265/-26A)/-262
18ns (-335)
20ns (-262)
20ns (-202/-265/-26A)
00
48
3C
50
30
3C
48
3C
50
00
48
3C
50
30
3C
48
3C
50
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Table 20: Serial Presence-Detect Matrix (Continued)
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes at end of SPD Matrix
BYTE
30
31
32
33
34
35
36-40
41
42
43
44
45
46-61
62
63
64
65-71
72
73-90
91
92
93
DESCRIPTION
ENTRY (VERSION)
42ns (-335)
45ns (-262/-265/-26A)
40ns (-202)
128MB or 256MB
0.8ns (-335)
1.0ns (-262/-265/-26A)
1.1ns (-202)
0.8ns (-335)
1.0ns (-262/-265/-26A)
1.1ns (-202)
0.45ns (-335
0.5ns (-262/-265/-26A)
0.6ns (-202)
0.45ns (-335
0.5ns (-262/-265/-26A)
0.6ns (-202)
MT9VDDT1672A
2A
2D
28
20
Module Rank Density
80
Address and Command Setup Time, tIS
A0
(See note 3)
B0
t
80
Address and Command Hold Time, IH
A0
(See note 3)
B0
45
Data/Data Mask Input Setup Time, tDS
50
60
t
45
Data/Data Mask Input Hold Time, DH
50
60
00
Reserved
t
60ns (-335/-262)
3C
Minimum Active/Auto Refresh Time, ( RC)
65ns (-265/-26A)
41
70ns (-202)
46
72ns (-335)
48
Minimum Auto Refresh to Active/ Auto
75ns (-262/-265/-26A)
4B
Refresh Command Period, (tRFC)
80ns (-202)
50
t
30
12ns
(-335)
Maximum Cycle Time, ( CK (MAX))
13ns (-202/-265/-26A/-262)
34
t
0.45ns
(-335)
2D
Maximum DQS-DQ Skew Time, ( DQSQ)
0.5ns (-262-265/-26A)
32
0.6ns (-202)
3C
0.6ns (-335)
60
Maximum Read Data Hold Skew Factor, (tQHS)
0.75ns (-262/-265/-26A)
75
1ns (-202)
A0
00
Reserved
Release 0.0
00
SPD Revision
-335
na/10 (See note 2)
Checksum for Bytes 0–62
-262
94
-26A
05/C5 (See note 2)
-265
35/F5 (See note 2)
-202
D0/90 (See note 2)
MICRON
2C
Manufacturer’s JEDEC ID Code
00
Manufacturer’s JEDEC ID Code (Continued)
01–11
01–0B
Manufacturing Location
Variable Data
Module Part Number (ASCII)
1–9
01–09
PCB Identification Code
0
00
Identification Code (Continued)
Variable Data
Year of Manufacture in BCD
Minimum RAS# Pulse Width, tRAS
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
26
MT9VDDT3272A
2A
2D
28
40
80
A0
B0
80
A0
B0
45
50
60
45
50
60
00
3C
41
46
48
4B
50
30
34
2D
32
3C
60
75
A0
00
00
33
B7
E8
18
B3
2C
00
01–0B
Variable Data
01–09
00
Variable Data
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Table 20: Serial Presence-Detect Matrix (Continued)
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes at end of SPD Matrix
BYTE
94
95-98
99-127
DESCRIPTION
ENTRY (VERSION)
Week of Manufacture in BCD
Module Serial Number
Manufacturer-Specific Data (RSVD)
MT9VDDT1672A
MT9VDDT3272A
Variable Data
Variable Data
–
Variable Data
Variable Data
–
NOTE:
1. The value of tCK for -26A modules is set at 7.0ns. Component spec. value is 7.5ns.
2. Supports Fast/Concurrent Auto Precharge. Values are listed in the form “without Concurrent Auto Precharge” /
“with Concurrent Auto Precharge.” Contact Factory for additonal information regarding this option.
3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate)
value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the
faster minimum slew rate is met.
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Figure 15: 184-Pin DIMM Dimensions
0.125 (3.18)
MAX
FRONT VIEW
5.256 (133.50)
5.244 (133.20)
0.079 (2.00) R
(4X)
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
1.255 (31.88)
1.245 (31.62)
0.700 (17.78)
TYP.
0.098 (2.50) D
(2X)
0.091 (2.30) TYP.
0.035 (0.90) R
PIN 1
0.091 (2.30)
TYP.
PIN 92
0.250 (6.35) TYP.
0.050 (1.27)
TYP.
0.054 (1.37)
0.046 (1.17)
0.040 (1.02)
TYP.
4.750 (120.65)
BACK VIEW
NO COMPONENTS THIS SIDE
PIN 184
PIN 93
0.150 (3.80)
1.95 (49.53)
2.55 (64.77)
0.150 (3.80) 0.394 (10.00)
TYP.
TYP.
NOTE:
All dimensions in inches (millimeters)
MAX
or typical where noted.
MIN
Data Sheet Designation
Released (No Mark): This data sheet contains minimum and maximum limits specified over the complete
power supply and temperature range for production
devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
28
Micron Technology, Inc., reserves the right to change products or specifications without notice..
©2003 Micron Technology, Inc
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
Revision History
Rev. B, Released, 2/03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/03
• Added Low Power option
• Added -335 and -262 speed grades
• Updated Idd, Capacitance, DC Electrical values
• Added Pf-free option
• Updated format
Rev. A, Released, 01/02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 01/02
• New data sheet
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.