19-4932; 11/09
DS2482-800
Eight-Channel 1-Wire Master
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS2482-800 is an I²C to 1-Wire bridge device
that interfaces directly to standard (100kHz max) or
fast (400kHz max) I²C masters to perform bidirectional protocol conversion between the I²C
master and any downstream 1-Wire slave devices.
Relative to any attached 1-Wire slave device, the
DS2482-800 is a 1-Wire master. Internal factorytrimmed timers relieve the system host processor
from generating time-critical 1-Wire waveforms,
supporting both standard and Overdrive 1-Wire
communication speeds. To optimize 1-Wire
waveform generation, the DS2482-800 performs
slew-rate control on rising and falling 1-Wire edges
and has a programmable feature to mask the fast
presence pulse edge that some 1-Wire slave devices
can generate. Programmable strong pullup features
support 1-Wire power delivery to 1-Wire devices such
as EEPROMs and sensors. The DS2482-800
combines these features with eight independent 1Wire I/O channels. The I²C slave address assignment
is controlled by three binary address inputs, resolving
potential conflicts with other I²C slave devices in the
system.
ORDERING INFORMATION
PART
DS2482S-800+
DS2482S-800+T&R
APPLICATIONS
I²C Host Interface, Supports 100kHz and 400kHz
I²C Communication Speeds
1-Wire Master I/O with Selectable Active or
Passive 1-Wire Pullup
Provides Reset/Presence, 8-Bit, Single-Bit, and
Three-Bit 1-Wire I/O Sequences
Eight Channels of Independently Operated
1-Wire I/O
Standard and Overdrive 1-Wire Communication
Speeds
Slew Controlled 1-Wire Edges
Supports Low-Impedance 1-Wire Strong Pullup
for EEPROMs, Temp Sensors, or Other 1-Wire
Slaves That Have Momentary High Current
Modes
Three Address Inputs for I²C Address
Assignment
Wide Operating Range: 2.9V to 5.5V, -40°C to
+85°C
16-Pin SO Package (150 mil)
TEMP RANGE
-40 to +85C
-40 to +85C
PIN-PACKAGE
16 SO (150 mil )
16 SO (150 mil )
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
Wireless Base Stations
Central Office Switches
PBXs
Rack-Based Servers
Medical Clinical Diagnostic Equipment
PIN CONFIGURATION
TYPICAL OPERATING CIRCUIT
IO3
1
16
IO2
SCL
2
15
IO1
SDA
3
14
IO0
VCC
4
13
GND
NC
5
12
IO4
AD2
6
11
IO5
AD1
7
10
IO6
AD0
8
9
IO7
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 of 23
DS2482-800: Eight-Channel 1-Wire Master
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground
Maximum Current Into Any Pin
Operating Temperature Range
Junction Temperature
Storage Temperature Range
Soldering Temperature
-0.5V, +6V
20mA
-40°C to +85°C
+150°C
-55°C to +125°C
See IPC/JEDEC J-STD-020A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
ELECTRICAL CHARACTERISTICS
(VCC = 2.9V to 5.5V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
Supply Voltage
VCC
Operating Current
ICC
1-Wire Input High
VIH1
1-Wire Input Low
VIL1
CONDITIONS
PDSRC
5V Pulldown Slew Rate
(Note 6)
PDSRC
3.3V Pullup Slew Rate (Note 6)
PUSRC
5V Pullup Slew Rate (Note 6)
PUSRC
Power-On Reset Trip Point
3.7
5.5
0.75
2.3
0.4
0.4
2.7
0.6
At 4mA load
Standard (Notes 4, 16)
Overdrive (Notes 4, 16)
3.3V Pulldown Slew Rate
(Note 6)
3.3
5.0
1675
(Note 4)
VOL1
VSTRPU
2.9
4.5
800
RWPU
Strong Pullup Voltage Drop
MAX
1.9
3.4
1-Wire Output Low
tAPUOT
TYP
3.3V
5V
(Note 1)
3.3V (Notes 2, 3)
5V (Notes 2, 3)
3.3V (Notes 2, 3)
5V (Notes 2, 3)
1-Wire Weak Pullup Resistor
Active Pullup On Time
MIN
V
mA
V
0.75
1.0
2.5
0.5
VCC 3.2V, 1.5mA load
0.3
VCC 5.2 V, 3mA load
0.5
Standard (3.3V 10%)
Overdrive (3.3V 10%)
Standard (5.0V 10%)
Overdrive (5.0V 10%)
Standard (3.3V 10%)
Overdrive (3.3V 10%)
Standard (5.0V 10%)
Overdrive (5.0V 10%)
UNITS
1
5
2
10
0.8
2.7
1.3
3.4
4.2
22.1
6.5
40
4
20
6
31
VPOR
V
V
µs
V
V/µs
V/µs
V/µs
V/µs
2.2
V
µs
1-Wire TIMING (Note 15) See Figures 4, 5, and 6
Write 1/Read Low Time
tW1L
Read Sample Time
tMSR
1-Wire Time Slot
tslot
Fall Time High-to-Low at
Standard Speed (Note 6)
Fall Time High-to-Low at
Overdrive Speed (Note 6)
tF1
Standard
Overdrive
7.6
0.9
8
1
8.4
1.1
Standard
Overdrive
Standard
Overdrive
3.3V to 0V (Note 5)
5.0V to 0V (Note 5)
3.3V to 0V (Note 5)
13.3
1.4
65.8
9.9
0.54
0.55
0.10
14
1.5
69.3
10.5
15
1.8
72.8
11.0
3.0
2.2
0.59
5.0V to 0V (Note 5)
0.09
2 of 23
0.44
µs
µs
µs
DS2482-800: Eight-Channel 1-Wire Master
PARAMETER
SYMBOL
Write 0 Low Time
tW0L
Write 0 Recovery Time
tREC0
Reset Low Time
tRSTL
Presence-Detect Sample Time
tMSP
Sampling for Short and
Interrupt
Reset High Time
tSI
tRSTH
CONDITIONS
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive
MIN
TYP
MAX
60
7.1
5.0
2.8
570
68.4
66.5
7.1
7.6
0.7
554.8
70.3
64
7.5
5.3
3.0
600
72
70
7.5
8
0.75
584
74
68
7.9
5.6
3.2
630
75.6
73.5
7.9
8.4
0.8
613.2
77.7
UNITS
µs
µs
µs
µs
µs
µs
I²C-Pins (Note 7) See Figure 9
LOW Level Input Voltage
VIL
VCC = 2.9V to 3.7V
-0.5
VCC = 4.5V to 5.5V
HIGH Level Input Voltage
Hysteresis of Schmitt Trigger
Inputs
LOW Level Output Voltage at
3mA Sink Current
Output Fall Time from VIhmin to
VILmax with a Bus Capacitance
from 10pF to 400pF
Pulse Width of Spikes that are
Suppressed by the Input Filter
Input Current Each I/O Pin with
an Input Voltage Between
0.1VCCmax and 0.9VCCmax
Input Capacitance
SCL Clock Frequency
Hold Time (Repeated) START
Condition. After this Period, the
First Clock Pulse is Generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a
STOP and START Condition
Capacitive Load for Each Bus
Line
Oscillator Warm-Up Time
0.7 ×
VCC
0.05 ×
VCC
VIH
Vhys
tSP
Ii
Ci
fSCL
V
V
V
250
ns
50
ns
-10
10
µA
0
10
400
pF
kHz
60
SDA and SCL pins only
(Notes 8, 9)
V
0.4
VOL
tof
0.25 ×
VCC
0.22 ×
VCC
VCC +
0.5V
(Note 8)
tHD:STA
0.6
µs
tLOW
tHIGH
1.3
0.6
µs
µs
tSU:STA
0.6
µs
tHD:DAT
tSU:DAT
tSU:STO
(Notes 10, 11)
(Note 12)
tBUF
250
0.6
0.9
µs
ns
µs
1.3
µs
Cb
(Note 13)
400
pF
tOSCWUP
(Note 14)
100
µs
3 of 23
DS2482-800: Eight-Channel 1-Wire Master
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Operating current with 1-Wire write byte sequence followed by continuous Read of Status Register at
400KHz in Overdrive.
With standard speed the total capacitive load of the 1-Wire bus should not exceed 1nF, otherwise the
passive pullup on threshold VIL1 may not be reached in the available time. With Overdrive speed the
capacitive load on the 1-Wire bus must not exceed 300pF.
Active pullup guaranteed to turn on between VIL1MAX and VIH1MIN.
Active or resistive pullup choice is configurable.
Fall time high to low (tF1) is derived from PDSRC, referenced from 0.9 × VCC to 0.1 × VCC.
These values apply at full load, i. e., 1nF at standard speed and 0.3nF at Overdrive speed. For
reduced load, the pulldown slew rate is slightly faster.
All I²C timing values are referred to VIHmin and VILmax levels.
Applies to SDA, SCL, and AD0, AD1, AD2.
I/O pins of the DS2482 do not obstruct the SDA and SCL lines if VCC is switched off.
The DS2482 provides a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
A Fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement
tSU:DAT 250ns must then be met. This is automatically the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr max + tSU:DAT = 1000 + 250 = 1250ns (according to the
standard-mode I²C-bus specification) before the SCL line is released.
CB = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according
to I²C-Bus Specification v2.1 are allowed.
I²C communication should not take place for the max tOSCWUP time following a power-on reset.
Except for tF1, all 1-Wire timing specifications and tAPUOT are derived from the same timing circuit.
Therefore, if one of these parameters is found to be off the typical value, it is safe to assume that all of
these parameters deviate from their typical value in the same direction and by the same degree.
PIN DESCRIPTION
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NAME
IO3
SCL
SDA
VCC
NC
AD2
AD1
AD0
IO7
IO6
IO5
IO4
GND
IO0
IO1
IO2
FUNCTION
IO Driver for 1-Wire Line #3
I²C Serial Clock Input; must be tied to VCC through a pullup resistor.
I²C Serial Data Input/Output; must be tied to VCC through a pullup resistor.
Power Supply Input
Not Connected
I²C Address Inputs; must be tied to VCC or GND. These inputs determine the I²C slave
address of the device, see Figure 8.
IO Driver for 1-Wire Line #7
IO Driver for 1-Wire Line #6
IO Driver for 1-Wire Line #5
IO Driver for 1-Wire Line #4
Ground Reference
IO Driver for 1-Wire Line #0
IO Driver for 1-Wire Line #1
IO Driver for 1-Wire Line #2
4 of 23
DS2482-800: Eight-Channel 1-Wire Master
Figure 1. Block Diagram
T-Time OSC
Config
Register
SDA
SCL
I²C
Interface
Controller
AD0
AD1
AD2
I/O
Controller
Channel
Select
Status
Register
Read Data
Register
Line
XCVR
IO0
Line
XCVR
IO1
Line
XCVR
IO2
Line
XCVR
IO3
Line
XCVR
IO4
Line
XCVR
IO5
Line
XCVR
IO6
Line
XCVR
IO7
DETAILED DESCRIPTION
The DS2482-800 is a self-timed 8-channel 1-Wire master, which supports advanced 1-Wire waveform features
including standard and Overdrive speeds, active pullup, and strong pullup for power delivery. Once supplied with
command and data, the I/O controller of the DS2482 performs time-critical 1-Wire communication functions such as
reset/presence detect cycle, read-byte, write-byte, single-bit R/W and triplet for ROM Search, without requiring
interaction with the host processor. The host obtains feedback (completion of a 1-Wire function, presence pulse, 1Wire short, search direction taken) through the Status Register and data through the Read Data register. The
DS2482 communicates with a host processor through its I²C bus interface in standard-mode or in fast-mode. The
logic state of three address pins (2 address pins with the 1-channel version) determines the I²C slave address of
the DS2482, allowing up to 8 devices operating on the same bus segment without requiring a hub.
DEVICE REGISTERS
The DS2482 has four registers that the I²C host can read: Channel Selection, Configuration, Status, and Read
Data. These registers are addressed by a read pointer. The position of the read pointer, i.e., the register that the
host will read in a subsequent read access, is defined by the instruction that the has DS2482 executed last. The
host has read and write access to the Channel Selection and Configuration Registers to select one of several 1Wire channels and to enable certain 1-Wire features.
5 of 23
DS2482-800: Eight-Channel 1-Wire Master
Channel Selection Register
The content of the Channel Selection Register specifies which of the channels is selected and will be the target of
subsequent 1-Wire communication commands. The DS2482-800 supports eight 1-Wire communication channels
IO0 to IO7. Only one of these channels can be active/selected at any time. Once selected, a 1-Wire channel
remains selected until a different channel is selected through the Channel Select command or by initiating a
device reset. After a device reset (power-up cycle or initiated by the Device Reset command) the IO0 channel is
selected.
Configuration Register
The DS2482 supports allows three 1-Wire features that are enabled or selected through the Configuration Register.
These features are:
Active Pullup (APU)
Strong Pullup (SPU)
1-Wire Speed (1WS)
These features can be selected in any combination. They apply equally to all 1-Wire channels. While APU, PPM
and 1WS maintain their state, SPU returns to its inactive state as soon as the strong pullup has ended.
Configuration Register Bit Assignment
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1WS
SPU
1
APU
1WS
SPU
0
APU
After a device reset (power-up cycle or initiated by the Device Reset command) the Configuration Register reads
00h. When writing to the Configuration Register, the new data is accepted only if the upper nibble (bits 7 to 4) is the
one's complement of the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h.
Active Pullup (APU)
The APU bit controls whether an active pullup (controlled slew-rate transistor) or a passive pullup (RWPU resistor)
will be used to drive a 1-Wire line from low to high. When APU = 0, active pullup is disabled (resistor mode). Active
Pullup should always be selected unless there is only a single slave on the 1-Wire line. The active pullup does
not apply to the rising edge of a presence pulse or a recovery after a short on the 1-Wire line.
The circuit that controls rising edges (Figure 2) operates as follows: At t1 the pulldown (from DS2482 or 1-Wire
slave) ends. From this point on the 1-Wire bus is pulled high through RWPU internal to the DS2482. VCC and the
capacitive load of the 1-Wire line determine the slope. In case that active pullup is disabled (APU = 0), the resistive
pullup continues, as represented by the solid line. With active pullup enabled (APU = 1), when at t2 the voltage has
reached a level between VIL1max and VIH1min, the DS2482 actively pulls the 1-Wire line high applying a controlled
slew rate, as represented by the dashed line. The active pullup continues until tAPUOT is expired at t3. From that time
on the resistive pullup will continue.
Figure 2. Rising Edge Pullup
VCC
VIH1MIN
APU = 1
APU = 0
VIL1MAX
0V
1-Wire bus is
discharged
tAPUOT
t1
t2
t3
6 of 23
DS2482-800: Eight-Channel 1-Wire Master
Strong Pullup (SPU)
The SPU bit controls whether the DS2482 applies a low-impedance pullup to VCC on the 1-Wire line after the last
bit of either a 1-Wire Write Byte command or after a 1-Wire Single Bit command has completed. The strong
pullup feature is commonly used with 1-Wire EEPROM devices when copying scratchpad data to the main memory
or when performing a SHA-1 computation, and with parasitically powered temperature sensors or A-to-D
converters. The respective device data sheets specify the location in the communications protocol after which the
strong pullup should be applied. The SPU bit in the configuration register of the DS2482 must be set immediately
prior to issuing the command that puts the 1-Wire device into the state where it needs the extra power.
If SPU is 1, the DS2482 applies active pullup to the rising edge of the time slot in which the strong pullup starts,
regardless of the APU bit setting. However, in contrast to setting APU = 1 for active pullup, the low-impedance
pullup will not end after tAPUOT is expired. Instead, as shown in Figure 3, the low-impedance pullup remains active
until: a) the next 1-Wire communication command (the typical case), b) by writing to the Configuration Register with
the SPU bit being 0 (alternative), or c) by issuing the Device Reset command. Additionally, when the pullup ends,
the SPU bit is automatically reset to 0. Using the strong pullup does not change the state of the APU bit in the
Configuration Register.
Figure 3. Low-Impedance Pullup Timing
Vcc
Last bit of 1-Wire Write Byte or 1-Wire Single Bit Function
Write 1
Edges with
active pull-up
Write 0
0V
Next
Time
Slot
tSLOT
Pull-up
DS2482 Pull-down
7 of 23
DS2482 Low Impedance Pull-up
DS2482-800: Eight-Channel 1-Wire Master
1-Wire Speed (1WS)
The 1WS bit determines the timing of any 1-Wire communication generated by the DS2482. All 1-Wire slave
devices support standard speed (1WS = 0), where the transfer of a single bit (tSLOT in Figure 3) is completed within
65µs. Many 1-Wire device can also communicate at a higher data rate, called Overdrive speed. To change from
standard to Overdrive speed, a 1-Wire device needs to receive an Overdrive Skip ROM or Overdrive Match ROM
command, as explained in the device data sheets. The change in speed occurs immediately after the 1-Wire device
has received the speed-changing command code. The DS2482 must take part in this speed change to stay
synchronized. This is accomplished by writing to the Configuration Register with the 1WS bit being 1 immediately
after the 1-Wire Byte command that changes the speed of a 1-Wire device. Writing to the Configuration Register
with the 1WS bit being 0 followed by a 1-Wire Reset command changes the DS2482 and any 1-Wire devices on
the active 1-Wire line back to standard speed.
Status Register
The read-only Status Register is the general means for the DS2482 to report bit-type data from the 1-Wire side, 1Wire busy status and its own reset status to the host processor. All 1-Wire communication commands and the
Device Reset command position the read pointer at the Status Register for the host processor to read with minimal
protocol overhead. Status information is updated during the execution of certain commands only. Details are given
in the description of the various status bits below.
Status Register Bit Assignment
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIR
TSB
SBR
RST
LL
SD
PPD
1WB
1-Wire Busy (1WB)
The 1WB bit reports to the host processor whether the 1-Wire line is busy. During 1-Wire communication 1WB is 1;
once the command is completed, 1WB returns to its default 0. Details on when 1WB changes state and for how
long it remains at 1 are found in the Function Commands section.
Presence Pulse Detect (PPD)
The PPD bit is updated with every 1-Wire Reset command. If the DS2482 detects a presence pulse from a 1-Wire
device at tMSP during the Presence Detect cycle, the PPD bit will be set to 1. This bit will return to its default 0 if
there is no presence pulse or if the 1-Wire line is shorted during a subsequent 1-Wire Reset command.
Short Detected (SD)
The SD bit is updated with every 1-Wire Reset command. If the DS2482 detects a logic 0 on the 1-Wire line at tSI
during the Presence Detect cycle, the SD bit will be set to 1. This bit will return to its default 0 with a subsequent 1Wire Reset command provided that the short has been removed. If SD is 1, PPD will be 0. The DS2482 cannot
distinguish between a short and a DS1994 or DS2404 signaling a 1-Wire interrupt. For this reason, if a
DS2404/DS1994 is used in the application, the interrupt function must be disabled. The interrupt signaling is
explained in the respective device data sheets.
Logic Level (LL)
The LL bit reports the logic state of the active 1-Wire line without initiating any 1-Wire communication. The 1-Wire
line is sampled for this purpose every time the Status Register is read. The sampling and updating of the LL bit
takes place when the host processor has addressed the DS2482 in read mode (during the acknowledge cycle),
provided that the Read Pointer is positioned at the Status Register.
Device Reset (RST)
If the RST bit is 1, the DS2482 has performed an internal reset cycle, either caused by a power-on reset or from
executing the Device Reset command. The RST bit is cleared automatically when the DS2482 executes a Write
Configuration command to restore the selection of the desired 1-Wire features.
8 of 23
DS2482-800: Eight-Channel 1-Wire Master
Single Bit Result (SBR)
The SBR bit reports the logic state of the active 1-Wire line sampled at tMSR of a 1-Wire Single Bit command or the
first bit of a 1-Wire Triplet command. The power-on default of SBR is 0. If the 1-Wire Single Bit command sends a
0-bit, SBR should be 0. With a 1-Wire Triplet command, SBR could be 0 as well as 1, depending on the response
of the 1-Wire devices connected. The same result applies to a 1-Wire Single Bit command that sends a 1-bit.
Triplet Second Bit (TSB)
The TSB bit reports the logic state of the active 1-Wire line sampled at tMSR of the second bit of a 1-Wire Triplet
command. The power-on default of TSB is 0. This bit is updated only with a 1-Wire Triplet command and has no
function with other commands.
Branch Direction Taken (DIR)
Whenever a 1-Write Triplet command is executed, this bit reports to the host processor the search direction that
was chosen by the 3rd bit of the triplet. The power-on default of DIR is 0. This bit is updated only with a 1-Wire
Triplet command and has no function with other commands. For additional information see the description of the 1Wire Triplet command and the Dallas Application Note 187, "1-Wire Search Algorithm".
FUNCTION COMMANDS
The DS2482 understands 9 function commands, which fall into four categories: device control, I²C communication,
1-Wire setup and 1-Wire communication. The feedback path to the host is controlled by a read pointer, which is set
automatically by each function command for the host to efficiently access relevant information. The host processor
sends these commands and applicable parameters as strings of one or two bytes using the I²C interface. The I²C
protocol requires that each byte be acknowledged by the receiving party to confirm acceptance or not be
acknowledged to indicate an error condition (invalid code or parameter) or to end the communication. Details of the
I²C protocol including acknowledge are found in the I²C interface description of this document.
Device Reset
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
F0h
None
Performs a global reset of device state machine logic, which in turn
selects IO0 as the active 1-Wire channel.
Terminates any ongoing 1-Wire communication.
Device initialization after power-up; re-initialization (reset) as desired.
None (can be executed at any time)
None
Maximum 525ns, counted from falling SCL edge of the command code
acknowledge bit.
Ends maximum 262.5ns after the falling SCL edge of the command code
acknowledge bit.
Status Register (for busy polling)
RST set to 1,
1WB, PPD, SD, SBR, TSB, DIR set to 0
1WS, APU, SPU set to 0
9 of 23
DS2482-800: Eight-Channel 1-Wire Master
Set Read Pointer
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
E1h
Pointer Code
Sets the read pointer to the specified register. Overwrites the read pointer
position of any 1-Wire communication command in progress.
To prepare reading the result from a 1-Wire Byte command; random read
access of registers.
None (can be executed at any time)
If the pointer code is not valid, the pointer code will not be acknowledged
and the command will be ignored.
None; the read pointer is updated on the rising SCL edge of the pointer
code acknowledge bit.
Not Affected
As Specified by the Pointer Code
None
None
Valid Pointer Codes
Register Selection
Code
Status Register
F0h
Read Data Register
E1h
Channel Selection Register
D2h
Configuration Register
C3h
Write Configuration
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
D2h
Configuration Byte
Writes a new configuration byte. The new settings take effect immediately.
NOTE: When writing to the Configuration Register, the new data is
accepted only if the upper nibble (bits 7 to 4) is the one's complement of
the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h.
Defining the features for subsequent 1-Wire communication.
1-Wire activity must have ended before the DS2482 can process this
command.
Command code and parameter will not be acknowledged if 1WB = 1 at the
time the command code is received and the command will be ignored.
None; the configuration register is updated on the rising SCL edge of the
configuration byte acknowledge bit.
None
Configuration Register (to verify write)
RST set to 0
1WS, SPU, APU updated
10 of 23
DS2482-800: Eight-Channel 1-Wire Master
Channel Select
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
C3h
Selection Code
Sets the 1-Wire IO channel for subsequent 1-Wire communication
commands. NOTE: The selection code read back is different from the
code written. See the table below for the respective values.
Selecting a 1-Wire IO channel other that IO0; randomly selecting one of
the available 1-Wire IO channels.
1-Wire activity must have ended before the DS2482 can process this
command.
Command code and parameter will not be acknowledged if 1WB = 1 at the
time the command code is received and the command will be ignored.
If the selection code is not valid, the selection code will not be
acknowledged and the command will be ignored.
None; the channel selection register is updated on the rising SCL edge of
the selection code acknowledge bit.
None
Channel Selection Register (to verify write)
None
None
Valid Channel Selection Codes
Channel Selection
Code (to be written)
Code (read back)
Channel IO0 (default)
F0h
B8h
Channel IO1
E1h
B1h
Channel IO2
D2h
AAh
Channel IO3
C3h
A3h
Channel IO4
B4h
9Ch
Channel IO5
A5h
95h
Channel IO6
96h
8Eh
Channel IO7
87h
87h
Figure 4. 1-Wire Reset/Presence Detect Cycle
RESET PULSE
tSI
VCC
PRESENCE PULSE
tMSP
APU CONTROLLED
EDGE
VIH1
VIL1
0V
PRESENCE/SHORT DETECT
tF1
tRSTL
Pullup
tRSTH
DS2482 Pulldown
11 of 23
RESISTIVE
PULLUP
1-W Slave Pulldown
DS2482-800: Eight-Channel 1-Wire Master
1-Wire Reset
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
B4h
None
Generates a 1-Wire Reset/Presence Detect cycle (Figure 4) at the
selected IO channel. The state of the 1-Wire line is sampled at tSI and tMSP
and the result is reported to the host processor through the status register,
bits PPD and SD.
To initiate or end any 1-Wire communication sequence.
1-Wire activity must have ended before the DS2482 can process this
command.
Command code will not be acknowledged if 1WB = 1 at the time the
command code is received and the command will be ignored.
tRSTL + tRSTH + maximum 262.5ns, counted from the falling SCL edge of the
command code acknowledge bit.
Begins maximum 262.5ns after the falling SCL edge of the command
code acknowledge bit.
Status Register (for busy polling)
1WB (set to 1 for tRSTL + tRSTH),
PPD is updated at tRSTL + tMSP,
SD is updated at tRSTL + tSI
1WS, APU apply
1-Wire Single Bit
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
Bit Allocation in the Bit Byte
bit 7
bit 6
bit 5
bit 4
V
x
x
x
x = don’t care
87h
Bit Byte
Generates a single 1-Wire time slot with a bit value ‘V’ as specified by the
bit byte at the selected 1-Wire IO channel. A ‘V’ value of 0b will generate a
write-zero time slot (Figure 5), a value of 1b will generate a write one slot,
which also functions as a read data time slot (Figure 6). In either case the
logic level at the 1-Wire line is tested at tMSR and SBR is updated.
To perform single bit writes or reads on a 1-Wire IO channel when single
bit communication is necessary (the exception).
1-Wire activity must have ended before the DS2482 can process this
command.
Command code and bit byte will not be acknowledged if 1WB = 1 at the
time the command code is received and the command will be ignored.
tSLOT + maximum 262.5ns, counted from the falling SCL edge of the first
bit (MS bit) of the bit byte.
Begins maximum 262.5ns after the falling SCL edge of the MS bit of the
bit byte.
Status Register (for busy polling and data reading)
1WB (set to 1 for tSLOT)
SBR is updated at tMSR
DIR (may change its state)
1WS, APU, SPU apply
bit 3
x
bit 2
x
bit 1
x
bit 0
x
12 of 23
DS2482-800: Eight-Channel 1-Wire Master
Figure 5. Write-0 Time Slot
Vcc
tW0L
tMSR
VIH1
VIL1
0V
tF1
tSLOT
Pullup (see Fig. 2)
tREC0
DS2482 Pulldown
Figure 6. Write-1 and Read-Data Time Slot
tW1L
Vcc
tMSR
VIH1
VIL1
0V
tF1
tSLOT
Pullup (see Fig. 2)
DS2482 Pulldown
1-W Slave Pulldown
NOTE on Figure 7: Depending on its internal state, a 1-Wire slave device will transmit data to its master (e.g., the
DS2482). When responding with a 0, a 1-Wire slave will start pulling the line low during tW1L; its internal timing
generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, a 1Wire slave will not hold the line low at all, and the voltage starts rising as soon as tW1L is over. 1-Wire device data
sheets use the term tRL instead of tW1L to describe a read-data time slot. Technically, tRL and tW1L have identical
specifications and cannot be distinguished from each other.
1-Wire Write Byte
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
A5h
Data Byte
Writes single data byte to selected 1-Wire IO channel.
To write commands or data to a 1-Wire IO channel; equivalent to
executing eight 1-Wire Single Bit commands, but faster due to less I²C
traffic.
1-Wire activity must have ended before the DS2482 can process this
command.
Command code and data byte will not be acknowledged if 1WB = 1 at the
time the command code is received and the command will be ignored.
8 × tSLOT + maximum 262.5ns, counted from falling edge of the last bit (LS
bit) of the data byte.
Begins maximum 262.5ns after falling SCL edge of the LS bit of the data
byte (i.e., before the data byte acknowledge).
NOTE: The bit order on the I²C bus and the 1-Wire line is different.
(1-Wire: LS-bit first; I²C: MS-bit first) Therefore, 1-Wire activity cannot
begin before the DS2482 has received the full data byte.
Status Register (for busy polling)
1WB (set to 1 for 8 × tSLOT)
1WS, SPU, APU apply
13 of 23
DS2482-800: Eight-Channel 1-Wire Master
1-Wire Read Byte
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
96h
None
Generates eight read data time slots on the selected 1-Wire IO channel
and stores result in the Read Data Register.
To read data from a 1-Wire IO channel; equivalent to executing eight 1Wire Single Bit commands with V = 1 (write 1 time slot), but faster due to
less I²C traffic.
1-Wire activity must have ended before the DS2482 can process this
command.
Command code will not be acknowledged if 1WB = 1 at the time the
command code is received and the command will be ignored.
8 × tSLOT + maximum 262.5ns, counted from the falling SCL edge of the
command code acknowledge bit.
Begins maximum 262.5ns after the falling SCL edge of the command
code acknowledge bit.
Status Register (for busy polling)
NOTE: To read the data byte received from the 1-Wire IO channel, issue
the Set Read Pointer command and select the Read Data Register. Then
access the DS2482 in read mode.
1WB (set to 1 for 8 × tSLOT)
1WS, APU apply
1-Wire Triplet
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
78h
Direction Byte
Generates three times slots, two read-time slots and one-write time slot, at
the selected 1-Wire IO channel. The type of write-time slot depends on the
result of the read-time slots and the direction byte.
The direction byte determines the type of write-time slot if both read-time
slots are 0 (a typical case). In this case the DS2482 will generate a write-1
time slot if V = 1 and a write-0 time slot if V = 0.
If the read-time slots are 0 and 1, there will follow a write 0 time slot.
If the read-time slots are 1 and 0, there will follow a write 1 time slot.
If the read-time slots are both 1 (error case), the subsequent write time
slot will be a write 1.
To perform a 1-Wire Search ROM sequence; a full sequence requires this
command to be executed 64 times to identify and address one device.
1-Wire activity must have ended before the DS2482 can process this
command.
Command code and direction byte will not be acknowledged if 1WB = 1 at
the time the command code is received and the command will be ignored.
3 × tSLOT + maximum 262.5ns, counted from the falling SCL edge of the
first bit (MS bit) of the direction byte.
Begins maximum 262.5ns after the falling SCL edge of the MS bit of the
direction byte.
Status Register (for busy polling)
1WB (set to 1 for 3 × tSLOT)
SBR is updated at the first tMSR
TSB and DIR are updated at the second tMSR (i.e., at tSLOT + tMSR)
1WS, APU apply
14 of 23
DS2482-800: Eight-Channel 1-Wire Master
Bit Allocation in the Direction Byte
bit 7
bit 6
bit 5
bit 4
bit 3
V
x
x
x
x
x = don’t care
bit 2
x
bit 1
x
bit 0
x
I²C INTERFACE
General Characteristics
The I²C bus uses a data line (SDA) plus a clock signal (SCL) for communication. Both SDA and SCL are
bidirectional lines, connected to a positive supply voltage through a pullup resistor. When there is no
communication, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain
or open-collector to perform the wired-AND function. Data on the I²C bus can be transferred at rates of up to
100kbps in the Standard-mode, up to 400kbps in the Fast-mode. The DS2482 works in both modes.
A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The
device that controls the communication is called a “master.” The devices that are controlled by the master are
“slaves.” To be individually accessed, each device must have a slave address that does not conflict with other
devices on the bus.
Data transfers may be initiated only when the bus is not busy. The master generates the serial clock (SCL),
controls the bus access, generates the START and STOP conditions, and determines the number of data bytes
transferred between START and STOP (Figure 7). Data is transferred in bytes with the most significant bit being
transmitted first. After each byte follows an acknowledge bit to allow synchronization between master and slave.
Figure 7. I²C Protocol Overview
R/W
MS-bit
ACK
bit
ACK
bit
SDA
Slave Address
Acknowledgment
from Receiver
SCL
1
Idle
START
Condition
2
6
7
8
9
ACK
Repeated if more bytes
are transferred
1
2
8
9
ACK
STOP Condition
Repeated START
Condition
Slave Address
The slave address to which the DS2482 responds is shown in Figure 8. The logic states at the address pins AD0,
AD1 and AD2 determine the value of the address bits A0, A1, and A2. The address pins allow the device to
respond to one of eight possible slave addresses. The slave address is part of the slave-address/control byte. The
last bit of the slave-address/control byte (R/W) defines the data direction. When set to a 0, subsequent data will
flow from master to slave (write access); when set to a 1, data will flow from slave to master (read access).
15 of 23
DS2482-800: Eight-Channel 1-Wire Master
Figure 8. DS2482 Slave Address
7-Bit Slave Address
A6
A5
A4
A3
0
0
1
1
Most Significant Bit
A2
A1
A0
AD2 AD1 AD0 R/W
AD2, AD1, AD0
Pin States
Determines
Read or Write
I²C Definitions
The following terminology is commonly used to describe I²C data transfers. The timing references are defined in
Figure 9.
Bus Idle or Not Busy: Both, SDA and SCL, are inactive and in their logic HIGH states.
START Condition: To initiate communication with a slave, the master has to generate a START condition. A
START condition is defined as a change in state of SDA from HIGH to LOW while SCL remains HIGH.
STOP Condition: To end communication with a slave, the master has to generate a STOP condition. A STOP
condition is defined as a change in state of SDA from LOW to HIGH while SCL remains HIGH.
Repeated START Condition: Repeated starts are commonly used for read accesses to select a specific data
source or address to read from. The master can use a repeated START condition at the end of a data transfer to
immediately initiate a new data transfer following the current one. A repeated START condition is generated the
same way as a normal START condition, but without leaving the bus idle after a STOP condition.
Data Valid: With the exception of the START and STOP condition, transitions of SDA may occur only during the
LOW state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus
the required setup and hold time (tHD:DAT after the falling edge of SCL and tSU:DAT before the rising edge of SCL, see
Figure 9). There is one clock pulse per bit of data. Data is shifted into the receiving device during the rising edge of
the SCL.
When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum
tSU:DAT + tR in Figure 9) before the next rising edge of SCL to start reading. The slave shifts out each data bit on
SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL
pulse. The master generates all SCL clock pulses, including those needed to read from a slave.
Acknowledge: Usually, a receiving device, when addressed, is obliged to generate an acknowledge after the
receipt of each byte. The master must generate a clock pulse that is associated with this acknowledge bit. A device
that acknowledges must pull SDA LOW during the acknowledge clock pulse in such a way that SDA is stable LOW
during the HIGH period of the acknowledge-related clock pulse plus the required setup and hold time (tHD:DAT after
the falling edge of SCL and tSU:DAT before the rising edge of SCL).
Not Acknowledged by Slave: A slave device may be unable to receive or transmit data, e.g., because it is busy
performing some real-time function. In this case the slave device will not acknowledge its slave address and leave
the SDA line HIGH.
A slave device that is ready to communicate will acknowledge at least its slave address. However, some time later
the slave may refuse to accept data, e.g., because of an invalid command code or parameter. In this case the slave
device will not acknowledge any of the bytes that it refuses and will leave SDA HIGH. In either case, after a slave
has failed to acknowledge, the master first needs to generate a repeated START condition or a STOP condition
followed by a START condition to begin a new data transfer.
16 of 23
DS2482-800: Eight-Channel 1-Wire Master
Not Acknowledged by Master: At some time when receiving data, the master must signal an end of data to the
slave device. To achieve this, the master does not acknowledge the last byte that it has received from the slave. In
response, the slave releases SDA, allowing the master to generate the STOP condition.
Figure 9. I²C Timing Diagram
SDA
tBUF
tHD:STA
tF
tLOW
tSP
SCL
tHD:STA
tR
tSU:STA
tHIGH
tHD:DAT
Spike
Suppression
tSU:STO
tSU:DAT
Repeated
START
STOP START
NOTE: Timing is referenced to VILMAX and VIHMIN.
Writing to the DS2482
To write to the DS2482, the master must access the device in write mode, i.e., the slave address must be sent with
the direction bit set to 0. The next byte to be sent is a command code, which, depending on the command, may be
followed by a command parameter. The DS2482 will acknowledge valid command codes and expected/valid
command parameters. Additional bytes or invalid command parameters will never be acknowledged.
Reading from the DS2482
To read from the DS2482, the master must access the device in read mode, i. e., the slave address must be sent
with the direction bit set to 1. The read pointer determines the register that the master will read from. The master
may continue reading the same register over and over again, without having to re-address the device, e. g., to
watch the 1WB changing from 1 to 0. To read from a different register, the master must issue the Set Read Pointer
command and then access the DS2482 again in read mode.
I²C Communication—Legend
SYMBOL
S
DESCRIPTION
SYMBOL
DESCRIPTION
START Condition
DRST
Command "Device Reset", F0h
AD,0
Select DS2482 for Write Access
WCFG
Command "Write Configuration", D2h
AD,1
Select DS2482 for Read Access
CHSL
Command "Channel Select", C3h
Sr
Repeated START Condition
P
STOP Condition
1WRS
Command "1-Wire Reset", B4h
A
Acknowledged
1WWB
Command "1-Wire Write Byte", A5h
A\
Not Acknowledged
1WRB
Command "1-Wire Read Byte", 96h
Bus Not Busy
1WSB
Command "1-Wire Single Bit", 87h
(Idle)
<byte>
SRP
Transfer of 1 Byte
1WT
17 of 23
Command "Set Read Pointer", E1h
Command "1-Wire Triplet", 78h
DS2482-800: Eight-Channel 1-Wire Master
Data Direction Codes
Master-to-Slave
Slave-to-Master
I²C Communication Examples
Device Reset, e.g., after power-up
S
AD,0
A
DRST
A
Sr
AD,1
A
<byte>
A\
This example includes an optional read access to verify the success of the command.
P
Write Configuration, e.g., before starting 1-Wire activity power-up
Case A: 1-Wire idle (1WB = 0)
S
AD,0
A
WCFG
A
<byte>
A
Sr
AD,1
A
<byte>
This example includes an optional read access to verify the success of the command.
Case B: 1-Wire busy (1WB = 1)
S
AD,0
A
WCFG
A\
A\
P
P
The master should stop and restart as soon as the DS2482 does not acknowledge the command code.
Channel Select, e.g., to select another 1-Wire channel
Case A: 1-Wire idle (1WB = 0)
S
AD,0
A
CHSL
A
E1h
A
Sr
AD,1
A
<byte>
A\
P
E1h is the valid channel selection code for IO1. This example includes an optional read access to verify the
success of the command.
Case B: 1-Wire idle (1WB = 0), invalid channel selection code
S
AD,0
A
CHSL
A
E5h
A\
P
E5h is an invalid channel selection code.
Case C: 1-Wire busy (1WB = 1)
S
AD,0
A
CHSL
A\
P
The master should stop and restart as soon as the DS2482 does not acknowledge the command code.
Set Read Pointer, e.g., to read from another register
Case A: valid read pointer code
S
AD,0
A
SRP
A
C3h
A
P
C3h is the valid read pointer code for the configuration register.
Case B: invalid read pointer code
S
AD,0
A
SRP
E5h is an invalid read pointer code.
A
E5h
A\
18 of 23
P
DS2482-800: Eight-Channel 1-Wire Master
1-Wire Reset, e.g., to begin or end 1-Wire communication
Case A: 1-Wire idle (1WB = 0), no busy polling to read the result
S
AD,0
A
1WRS
A
P
(Idle)
S
AD,1
A
<byte>
A\
P
In the first cycle, the master sends the command; then the master waits (Idle) for the 1-Wire Reset to complete. In
the second cycle the DS2482 is accessed to read the result of the 1-Wire Reset from the Status Register.
Case B: 1-Wire idle (1WB = 0), busy polling until the 1-Wire Command is completed, then read the result
S
AD,0
A
1WRS
A
Sr
AD,1
A
<byte>
A
<byte>
A\
P
Repeat until the 1WB bit has changed to 0
Case C: 1-Wire busy (1WB = 1)
S
AD,0
A
1WRS
A\
P
The master should stop and restart as soon as the DS2482 does not acknowledge the command code.
1-Wire Write Byte, e.g., to send a command code to a 1-Wire IO channel
Case A: 1-Wire idle (1WB = 0), no busy polling
S
AD,0
A
1WWB
A
33h
A
P
(Idle)
33h is the valid 1-Wire ROM function command for Read ROM. The idle time is needed for the 1-Wire function to
complete. There is no data read back from the 1-Wire line with this command.
Case B: 1-Wire idle (1WB = 0), busy polling until the 1-Wire Command is completed.
S
AD,0
A
1WWB
A
33h
A
Repeat until the 1WB
bit has changed to 0
Sr
AD,1
A
<byte>
A
<byte>
When 1WB has changed from 1 to 0, the 1-Wire Write Byte command is completed.
A\
P
Case C: 1-Wire busy (1WB = 1)
S
AD,0
A
1WWB
A\
P
The master should stop and restart as soon as the DS2482 does not acknowledge the command code.
1-Wire Read Byte, e. g., to read a byte from a 1-Wire IO channel
Case A: 1-Wire idle (1WB = 0), no busy polling, set read pointer after idle time.
S
AD,0
A
1WRB
A
P
(Idle)
S
AD,0
A
SRP
A
E1h
A
Sr
AD,1
A
<byte>
A\
P
The idle time is needed for the 1-Wire function to complete. Then set the read pointer to the read data register
(code E1h) and access the device again to read the data byte that was obtained from the 1-Wire IO channel.
Case B: 1-Wire idle (1WB = 0), no busy polling, set read pointer before idle time.
S
AD,0
A
1WRB
A
Sr
AD,0
A
SRP
A
(Idle)
S
AD,1
A
<byte>
E1h
A\
A
P
P
The read pointer is set to the read data register (code E1h) while the 1-Wire Read Byte command is still in
progress. Then, after the 1-Wire function is completed, the device is accessed to read the data byte that was
obtained from the 1-Wire IO channel.
19 of 23
DS2482-800: Eight-Channel 1-Wire Master
Case C: 1-Wire idle (1WB = 0), busy polling until the 1-Wire Command is completed.
Repeat until the 1WB
S
AD,0
A
1WRB
A
bit has changed to 0
Sr
AD,1
A
<byte>
A
<byte>
A\
Sr
AD,0
A
SRP
A
E1h
A
Sr
AD,1
A
<byte>
A\
P
Poll the Status Register until the 1WB bit has changed from 1 to 0. Then set the read pointer to the read data
register (code E1h) and access the device again to read the data byte that was obtained from the 1-Wire IO
channel.
Case D: 1-Wire busy (1WB = 1)
S
AD,0
A
1WRB
A\
P
The master should stop and restart as soon as the DS2482 does not acknowledge the command code.
1-Wire Single Bit, e. g., to generate a single time slot on a 1-Wire IO channel
Case A: 1-Wire idle (1WB = 0), no busy polling
S
AD,0
A
1WSB
A
<byte>
A
P
(Idle)
S
AD,1
A
<byte>
A\
P
The idle time is needed for the 1-Wire function to complete. Then access the device in read mode to get the result
from the 1-Wire single-bit command.
Case B: 1-Wire idle (1WB = 0), busy polling until the 1-Wire Command is completed.
S
AD,0
A
1WSB
A
<byte>
A
Repeat until the 1WB
bit has changed to 0
Sr
AD,1
A
<byte>
A
<byte>
A\
P
When 1WB has changed from 1 to 0, the Status Register holds the valid result of the 1-Wire Single Bit command.
Case C: 1-Wire busy (1WB = 1)
S
AD,0
A
1WSB
A\
P
The master should stop and restart as soon as the DS2482 does not acknowledge the command code.
1-Wire Triplet, e.g., to perform a Search ROM function on a 1-Wire IO channel
Case A: 1-Wire idle (1WB = 0), no busy polling
S
AD,0
A
1WT
A
<byte>
A
P
(Idle)
S
AD,1
A
<byte>
A\
P
The idle time is needed for the 1-Wire function to complete. Then access the device in read mode to get the result
from the 1-Wire Triplet command.
Case B: 1-Wire idle (1WB = 0), busy polling until the 1-Wire Command is completed.
Repeat until the 1WB
S
AD,0
A
1WT
A
<byte>
A
bit has changed to 0
Sr
AD,1
A
<byte>
A
<byte>
A\
P
When 1WB has changed from 1 to 0, the Status Register holds the valid result of the 1-Wire Triplet command.
20 of 23
DS2482-800: Eight-Channel 1-Wire Master
Case C: 1-Wire busy (1WB = 1)
S
AD,0
A
1WT
A\
P
The master should stop and restart as soon as the DS2482 does not acknowledge the command code.
Figure 10. Application Schematic
Application Information
SDA and SCL Pullup Resistors
SDA is an open-drain output on the DS2482 that requires a pullup resistor to realize high logic levels. Because the
DS2482 uses SCL only as input (no clock stretching) the master can drive SCL either through an opendrain/collector output with a pullup resistor or a push-pull output.
Pullup Resistor RP Sizing
According to the I²C specification, a slave device must be able to sink at least 3mA at a VOL of 0.4V. This DC
condition determines the minimum value of the pullup resistor: Rpmin = (VCC - 0.4V)/3mA. With an operating
voltage of 5.5V, the minimum value for the pullup resistor is 1.7k. The "Minimum RP" line in Figure 11 shows how
the minimum pullup resistor changes with the operating voltage.
For I²C systems, the rise time and fall time are measured from 30% to 70% of the pullup voltage. The maximum
bus capacitance CB is 400pF. The maximum rise time at standard speed must not exceed 1000ns and 300ns at
fast speed. Assuming maximum rise time, the maximum resistor value at any given capacitance Cb is calculated
as: Rpmaxs = 1000ns/(CB*ln(7/3)) (standard speed) and Rpmaxf = 300ns/(CB*ln(7/3)) (fast speed). For a bus
capacitance of 400pF the maximum pullup resistor values are 2.95k at standard speed and 885 at fast speed. A
value between of 1.7k and 2.95k meets all requirements at standard speed.
Since a 885 pullup resistor, as would be required to meet the rise time specification at fast speed and 400pF bus
capacitance, is lower than Rpmin at 5.5V, a different approach is necessary. The "Max. Load…" line in Figure 11 is
generated by first calculating the minimum pullup resistor at any given operating voltage ("Minimum Rp" line) and
then calculating the respective bus capacitance that yields a rise time of 300ns.
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DS2482-800: Eight-Channel 1-Wire Master
Only for pullup voltages of 3V and lower can the maximum permissible bus capacitance of 400pF be maintained. A
reduced bus capacitance of 300pF is acceptable for pullup voltages of 4V and lower. For fast speed operation at
any pullup voltage, the bus capacitance must not exceed 200pF. The corresponding pullup resistor value at the
voltage is indicated by the "Minimum Rp" line.
Figure 11. I²C Fast Mode Pullup Resistor Selection Chart
Max. Load at Min. Rp fast mode
2000
500
1600
400
1200
300
800
200
400
100
0
Load (pF)
Minimum Rp (Ohms)
"Minimum Rp"
0
1
2
3
4
5
Pull-up Voltage
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+",
"#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix
character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
16 SO (150 mil)
S16+5
21-0041
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DS2482-800: Eight-Channel 1-Wire Master
REVISION HISTORY
REVISION
DATE
8/08
11/09
DESCRIPTION
Removed the 1-Wire line termination resistor and references to it from the
Typical Operating Circuit and Figure 11.
Conversion to lead (Pb) free product.
Removed the presence pulse masking feature.
Revised the recommendation on the use of active pullup.
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