ETC L80223

L80223
10BASE-T/100BASE-TX/FX
Ethernet PHY
Technical Manual
Draft 6/5/00
Preliminary
Order Number R14016
Draft 6/5/00
This document is preliminary. As such, it contains data derived from functional
simulations and performance estimates. LSI Logic has not verified either the
functional descriptions, or the electrical and mechanical specifications using
production parts.
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
DB14-000133-00,First Edition (June 2000)
This document describes revision/release A of LSI Logic Corporation’s
L80223 10BASE-T/100BASE-TX/FX Ethernet PHY and will remain the official
reference source for all revisions/releases of this product until rescinded by an
update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of LSI
Logic or third parties.
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design is a registered trademark of LSI Logic Corporation. All
other brand and product names may be trademarks of their respective
companies.
ii
Rev. A
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Preface
This book is the primary reference and technical manual for the L80223
10BASE-T/100BASE-TX/FX Ethernet Physical Layer Device (PHY). It
contains a complete functional description for the L80223 and includes
complete physical and electrical specifications for the product.
Audience
This document assumes that you have some familiarity with Ethernet
devices and related support devices. The people who benefit from this
book are:
•
Engineers and managers who are evaluating the device for possible
use in a system
•
Engineers who are designing the device into a system
Organization
This document has the following chapters:
•
Chapter 1, Introduction, describes the device in general terms and
gives a block diagram and lists the device features.
•
Chapter 2, Functional Description, describes each of the internal
blocks in the device in some detail.
•
Chapter 3, Signal Descriptions, lists and describes the device input
and output signals.
•
Chapter 4, Registers, gives a register summary and describes each
of the bits in each register.
•
Chapter 5, Management Interface, describes the device
Management Interface, which allows the registers to be read and
written.
Preface
Rev. A
iii
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
•
Chapter 6, Specifications, lists the AC and DC characteristics and
gives typical timing parameters.
•
Appendix A, Application Information, gives practical guidelines for
incorporating the device into a design.
Abbreviations Used in This Manual
Below is a list of abbreviations used throughout this manual.
100BASE-FX
100BASE-T
10BASE-T
4B5B
CLK
CRC
CRS
CSMA
CWRD
DA
ECL
EOF
ESD
FCS
FDX
FEF
FIFO
FLP
HDX
HIZ
I/G
IETF
IPG
IREF
L/T
LSB
MIB
MLT3
ms
MSB
mV
NLP
NRZI
NRZ
OP
PCB
iv
100 Mbits/s Fiber Optic Ethernet
100 Mbits/s Twisted-Pair Ethernet
10 Mbits/s Twisted-Pair Ethernet
4-Bit 5-Bit
Clock
Cyclic Redundancy Check
Carrier Sense
Carrier Sense Multiple Access
Codeword
Destination Address
Emitter-Coupled Logic
End of Frame
End of Stream Delimiter
Frame Check Sequence
Full-Duplex
Far End Fault
First In - First Out
Fast Link Pulse
Half-Duplex
High Impedance
Individual/Group
Internet Engineering Task Force
Inter-Packet Gap
Reference Current
Length and Type
Least-Significant Bit
Management Information Base
Multi-Level Transmission (3 levels)
millisecond
Most-Significant Bit
millivolt
Normal Link Pulse
Non-Return to Zero Inverted
Non-Return to Zero
Opcode
Printed Circuit Board
Preface
Rev. A
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
pF
PRE
R/LH
R/LHI
R/LL
R/LLI
R/LT
R/LTI
R/WSC
RFC
RJ-45
RMON
SA
SFD
SNMP
SOI
SSD
STP
TP
µH
µP
UTP
picofarad
Preamble
Read Latched High
Read Latched High with Interrupt
Read Latched Low
Read Latched Low with Interrupt
Read Latched Transition
Read Latched Transition with Interrupt
Read/Write Self Clearing
Request for Comments
Registered Jack-45
Remote Monitoring
Start Address or Station Address
Start of Frame Delimiter
Simple Network Management Protocol
Start of Idle
Start of Stream Delimiter
Shielded Twisted Pair
Twisted Pair
microhenry
microprocessor
Unshielded Twisted Pair
Conventions Used in This Manual
The first time a word or phrase is defined in this manual, it is italicized.
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.
Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.
Preface
Rev. A
v
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
vi
Preface
Rev. A
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Contents
Chapter 1
Chapter 2
Introduction
1.1
Overview
1.2
Features
1-1
1-4
Functional Description
2.1
Overview
2.1.1
Channel Operation
2.1.2
Data Paths
2.2
Block Diagram Description
2.2.1
Oscillator and Clock
2.2.2
Controller Interface
2.2.3
Encoder
2.2.4
Decoder
2.2.5
Scrambler
2.2.6
Descrambler
2.2.7
Twisted-Pair Transmitters
2.2.8
Twisted-Pair Receivers
2.2.9
FX Transmitter and Receiver
2.2.10 Clock and Data Recovery
2.2.11 Link Integrity and AutoNegotiation
2.2.12 Link Indication
2.2.13 Collision
2.2.14 LED Drivers
2.3
Start of Packet
2.3.1
100 Mbits/s
2.3.2
10 Mbits/s
2.4
End of Packet
2.4.1
100 Mbits/s
2.4.2
10 Mbits/s
L80223 10BASE-T/100BASE-TX/FX Ethernet PHY
Rev. A
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-2
2-2
2-2
2-7
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2-9
2-14
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Draft 6/5/00
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
Chapter 3
Chapter 4
viii
Full/Half Duplex Mode
2.5.1
Forcing Full/Half Duplex Operation
2.5.2
Full/Half Duplex Indication
2.5.3
Loopback
Repeater Mode
10/100 Mbits/s Selection
2.7.1
Forcing 10/100 Mbits/s Operation
2.7.2
Autoselecting 10/100 Mbits/s Operation
2.7.3
10/100 Mbits/s Indication
Jabber
Automatic Jam
2.9.1
100 Mbits/s JAM
2.9.2
10 Mbits/s JAM
Reset
Powerdown
Receive Polarity Correction
Signal Descriptions
3.1
Media Interface Signals
3.2
Controller Interface Signals (MII)
3.3
Management Interface
3.4
Miscellaneous Signals
3.5
LEDs
3.6
Power Supply
Registers
4.1
Bit Types
4.2
MI Serial Port Register Summary
4.3
Registers
4.3.1
Control Register (Register 0)
4.3.2
Status Register (Register 1)
4.3.3
PHY ID 1 Register (Register 2)
4.3.4
PHY ID 2 Register (Register 3)
4.3.5
AutoNegotiation Advertisement Register
(Register 4)
4.3.6
AutoNegotiation Remote End Capability Register
(Register 5)
Contents
Rev. A
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-43
2-43
2-44
2-44
2-45
2-46
2-46
2-46
2-46
2-47
2-47
2-47
2-47
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2-49
3-2
3-4
3-5
3-6
3-7
3-10
4-2
4-4
4-7
4-7
4-9
4-11
4-12
4-13
4-15
Draft 6/5/00
4.3.7
4.3.8
4.3.9
4.3.10
4.3.11
Chapter 5
Chapter 6
Appendix A
Configuration 1 Register (Register 16)
Configuration 2 Register (Register 17)
Status Output Register (Register 18)
Interrupt Mask Register (Register 19)
Reserved Register (Register 20)
Management Interface
5.1
Signal Description
5.2
General Operation
5.3
Multiple Register Access
5.4
Frame Structure
5.5
Register Structure
5.6
Interrupts
Specifications
6.1
Absolute Maximum Ratings
6.2
Electrical Characteristics
6.2.1
Twisted-Pair DC Characteristics
6.2.2
FX Characteristics, Transmit
6.3
AC Electrical Characteristics
6.3.1
25 MHz Input/Output Clock Timing Characteristics
6.3.2
Transmit Timing Characteristics
6.3.3
Receive Timing Characteristics
6.3.4
Collision and JAM Timing Characteristics
6.3.5
Link Pulse Timing Characteristics
6.3.6
Jabber Timing Characteristics
6.4
LED Driver Timing Characteristics
6.4.1
MI Serial Port Timing Characteristics
6.5
Pinouts and Package Drawings
6.5.1
Pinouts
6.5.2
L80223 Pin Layout
6.6
Mechanical Drawing
Application Information
A.1 Example Schematics
A.2 TP Transmit Interface
A.3 TP Receive Interface
Contents
Rev. A
4-17
4-20
4-23
4-25
4-28
5-2
5-3
5-5
5-6
5-8
5-9
6-2
6-3
6-5
6-9
6-12
6-13
6-14
6-17
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6-32
6-34
6-34
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6-41
A-1
A-5
A-6
ix
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
A.4
A.5
A.6
A.7
A.8
A.9
A.10
A.11
A.12
A.13
A.14
A.15
TP Transmit Output Current Set
Cable Selection
Transmitter Droop
Automatic JAM
FX Interface
A.8.1
Connection to 3.3 V Transceivers
A.8.2
Connection to 5 V Transceivers
A.8.3
Disabling the FX Interface
MII Controller Interface
A.9.1
Clocks
A.9.2
Output Drive
A.9.3
MII Disable
A.9.4
Receive Output Enable
FBI Controller Interface
Serial Port
A.11.1 Polling and Interrupt
A.11.2 Multiple Register Access
A.11.3 Serial Port Addressing
Oscillator
LED Drivers
Repeater Applications
A.14.1 MII-Based Repeaters
A.14.2 Non-MII Based Repeaters
A.14.3 Clocks
Power Supply Decoupling
Customer Feedback
x
Contents
Rev. A
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
A-7
A-8
A-9
A-9
A-11
A-11
A-12
A-14
A-15
A-15
A-15
A-16
A-17
A-17
A-18
A-18
A-19
A-19
A-21
A-21
A-22
A-22
A-22
A-23
A-24
Draft 6/5/00
Figures
1.1
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
3.1
5.1
5.2
5.3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19
6.20
6.21
6.22
A.1
Top Level Block Diagram
L80223 Device Block Diagram
100BASE-TX/FX and 10BASE-T Frame Format
MII Frame Format
TP Output Voltage Template
TP Input Voltage Template (10 Mbits/s)
Link Pulse Output Voltage Template (10 Mbits/s)
NLP vs FLP Link Pulse
SOI Output Voltage Template - 10 Mbits/s
Device Logic Diagram
MI Serial Port Frame Timing Diagram
MI Serial Frame Structure
MDIO Interrupt Pulse
25 MHz Output Timing
Transmit Timing - 100 Mbits/s
Transmit Timing - 10 Mbits/s
Receive Timing, Start of Packet - 100 Mbits/s
Receive Timing, End of Packet - 100 Mbits/s
Receive Timing, Start of Packet - 10 Mbits/s
Receive Timing, End of Packet - 10 Mbits/s
RX_EN Timing
Collision Timing, Receive 100 Mbits/s
Collision Timing, Receive 10 Mbits/s
Collision Timing, Transmit - 100 Mbits/s
Collision Timing, Transmit - 10 Mbits/s
Collision Test Timing
JAM Timing
NLP Link Pulse Timing
FLP Link Pulse Timing
Jabber Timing
LED Driver Timing
MI Serial Port Timing
MDIO Interrupt Pulse Timing
L80223 64-Pin LQFP, Top View
64-Pin LQFP Mechanical Drawing
Typical Network Interface Adapter Card Schematic
1-3
2-3
2-4
2-5
2-20
2-25
2-32
2-33
2-42
3-2
5-4
5-6
5-10
6-13
6-15
6-16
6-19
6-20
6-21
6-22
6-22
6-24
6-24
6-25
6-25
6-25
6-26
6-29
6-29
6-30
6-31
6-33
6-33
6-40
6-42
xi
Rev. A
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
A.2
A.3
A.4
A.5
A.6
A.7
Using the L80223
Typical Switching Port Schematic Using L80223
Typical External PHY Schematic Using L80223
Connection to 3.3 V Fiber Optic Transceivers
Connection to 5 V Fiber Optic Transceivers
MII Output Driver Characteristics
Serial Device Port Address Selection
xii
Rev. A
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
A-2
A-3
A-4
A-12
A-13
A-16
A-20
Draft 6/5/00
Tables
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
4.1
5.1
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
A.1
A.2
A.3
A.4
Transmit Preamble and SFD Bits at MAC Nibble Interface
Receive Preamble and SFD Bits at MAC Nibble Interface
4B/5B Symbol Mapping
4B/5B Symbol Mapping
TP Output Voltage - 10 Mbits/s
Transmit Level Adjust
FX Transmit Level Adjust
PLED_[1:0] Output Select Bit Encoding
LED Normal Function Definition
LED Event Definition
MI Register Bit Type Definition
MI Serial Port Register Summary
Absolute Maximum Ratings
DC Characteristics
Twisted Pair Characteristics (Transmit )
Twisted Pair Characteristics (Receive )
FX Characteristics, Transmit
FX Characteristics, Receive
Test Conditions
25 MHz Input/Output Clock
Transmit Timing
Receive Timing
Collision and Jam Timing
Link Pulse Timing
Jabber Timing
LED Driver Timing
MI Serial Port Timing
L80223 Pin List (by Signal Category)
L80223 Pin List (by Pin Number)
TP Transformer Specification
TP Transformer Sources
Cable Configuration
Crystal Specifications
Rev. A
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-5
2-6
2-10
2-14
2-21
2-22
2-27
2-38
2-38
2-39
4-2
5-8
6-2
6-3
6-5
6-8
6-9
6-11
6-12
6-13
6-14
6-17
6-23
6-27
6-30
6-31
6-32
6-34
6-37
A-5
A-5
A-8
A-21
xiii
Draft 6/5/00
xiv
Rev. A
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Chapter 1
Introduction
This chapter contains a brief introduction to the L80223
10BASE-T/100BASE-TX/FX Ethernet Physical Layer Device (PHY). It
contains the following sections:
•
Section 1.1, “Overview”
•
Section 1.2, “Features”
1.1 Overview
This manual describes the L80223 device. The device contains a single
PHY channel. The convention used in this manual is that device refers
to the IC, and channel refers to the PHY in the device.
The L80223 is a highly-integrated analog interface IC for twisted-pair or
fiber optic Ethernet applications. The device can be configured for either
100 Mbits/s (100BASE-TX or 100BASE-FX) or 10 Mbits/s (10BASE-T)
Ethernet operation.
The PHY channel contains the following blocks:
•
4B5B Encoder/Manchester Encoder
•
Scrambler
•
10BASE-T Transmitter
•
100BASE-TX Transmitter
•
100BASE-FX Transmitter
•
10BASE-T Receiver
•
100BASE-TX Receiver
•
100BASE-FX Receiver
L80223 10BASE-T/100BASE-TX/FX Ethernet PHY
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
1-1
Draft 6/5/00
•
Clock and Data Recovery
•
Autonegotiation and Link Integrity
•
Descrambler
•
4B5B Decoder/Manchester Decoder
•
MII Controller Interface
•
Management Interface (MI)
•
Collision Detection
Figure 1.1 is a simplified top-level block diagram of the L80223 device.
1-2
Introduction
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Figure 1.1
Top Level Block Diagram
L80223
OSCIN
Oscillator
Scrambler
Manchester
Encoder
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Ethernet
Controller
Controller
Interface
(MII)
TPI/FXO
100BASE-TX
Transmitter
TPO/FXI
10BASE-T
Transmitter
Collision
100BASE-FX
Receiver
Squelch
4B5B
Decoder
Serial
Port
(MI)
Descrambler
Clock
& Data
Recovery
100BASE-TX
Receiver
AutoNegotiation
and Link
Squelch
LEDs
LED
Drivers
Clock & Data
Recovery
(Manchester
Decoder)
10BASE-T
Receiver
Draft 6/5/00
Overview
Rev. letter
4B5B
Encoder
100BASE-FX
Transmitter
1-3
Draft 6/5/00
Internal output waveshaping circuitry and on-chip filters in the PHY
eliminates the need for external filters normally required in 100BASE-TX
and 10BASE-T applications.
Using the on-chip AutoNegotiation algorithm, the device can
automatically configure the PHY channel to independently operate in
100 Mbits/s or 10 Mbits/s operation in either full- or half-duplex mode.
The device uses the Management Interface (MI) serial port to access 11
16-bit registers in the PHY. These registers comply to Clause 22 of IEEE
802.3u and contain bits and fields that reflect configuration inputs, status
outputs, and device capabilities.
The device is ideally suited as a media interface for
10BASE-T/100BASE-TX/FX repeaters, routers, PCMCIA cards, NIC
cards, motherboards, networked modems, and other end station
applications.
The device is implemented in 0.35 or 0.30 micron CMOS technology and
operates on a 3.3 V power supply. The outputs are 5V-tolerant and
directly interface to other 5V devices.
1.2 Features
The following list summarizes the salient features of the device:
1-4
•
Single-chip solution for a 10BASE-T/100BASE-TX/FX PHY
•
Dual speed: 10/100 Mbit/s
•
Half-duplex or full-duplex operation
•
MII interface to Ethernet MAC
•
Management Interface (MI) for configuration and status
•
Optional Repeater Interface
•
AutoNegotiation for 10/100 Mbit/s, full/half duplex operation
•
Advertisement control through pins
•
All applicable IEEE 802.3, 10BASE-T and 100BASE-TX/FX
specifications are met
•
On-chip wave shaping (no external filters required)
Introduction
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
•
Adaptive equalizer for 100BASE-TX operation
•
Baseline wander correction
•
Minimum number of external components
•
Independent programmable LED output pins reflect the following
events:
–
Link
–
Activity
–
Collision
–
Full-Duplex
–
Speed (10/100 Mbits/s)
•
3.3 V power supply, 5 V tolerant I/O
•
64-pin LQFP
Features
1-5
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
1-6
Introduction
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Chapter 2
Functional Description
This chapter contains a functional description of the PHY device. It has
the following sections:
•
Section 2.1, “Overview”
•
Section 2.2, “Block Diagram Description”
•
Section 2.3, “Start of Packet”
•
Section 2.4, “End of Packet”
•
Section 2.5, “Full/Half Duplex Mode”
•
Section 2.6, “Repeater Mode”
•
Section 2.7, “10/100 Mbits/s Selection”
•
Section 2.8, “Jabber”
•
Section 2.9, “Automatic Jam”
•
Section 2.10, “Reset”
•
Section 2.11, “Powerdown”
•
Section 2.12, “Receive Polarity Correction”
L80223 10BASE-T/100BASE-TX/FX Ethernet PHY
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-1
Draft 6/5/00
2.1 Overview
This section gives a brief overview of the device functional operation.
The L80223 is a complete 10/100 Mbits/s Ethernet Media Interface IC. A
block diagram is shown in Figure 2.1.
2.1.1 Channel Operation
The PHY operates in the 100BASE-TX or 100BASE-FX modes at 100
Mbits/s, or in the 10BASE-T mode at 10 Mbits/s. The 100 Mbits/s modes
and the 10 Mbits/s mode differ in data rate, signaling protocol, and
allowed wiring as follows:
•
100BASE-TX mode uses two pairs of category 5 or better UTP or
STP twisted-pair cable with 4B5B encoded, scrambled, and MLT3
coded 62.5-MHz ternary data to achieve a throughput of 100 Mbits/s.
•
The 100BASE-FX mode uses two fiber cables with 4B5B encoded,
125-MHz binary data to achieve a throughput of 100 Mbits/s.
•
10 Mbits/s mode uses two pairs of category 3 or better UTP or STP
twisted-pair cable with Manchester encoded 10-MHz binary data to
achieve a 10 Mbits/s throughput
The data symbol format on the twisted-pair cable for the 100 and 10
Mbits/s modes is defined in IEEE 802.3 specifications and shown in
Figure 2.2.
2.1.2 Data Paths
In each device, there is a transmit data path and a receive data path
associated with each PHY channel. The transmit data path is from the
Controller Interface to the twisted-pair transmitter. The receive data path
is from the twisted-pair receiver to the Controller Interface.
2-2
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Figure 2.1
OSCIN
L80223 Device Block Diagram
REXT
100BASE-FX Transmitter
Oscillator
+
100BASE-TX Transmitter
RESETn
4B5B
Encoder
Scrambler
Switched
Current
Sources
MLT3
Encoder
+
-
LP
Filter
+
−
TPO+/FXI−
TPO−/FXI+
Clock
Generator
PLL
10BASE-T Receiver
TX_CLK
TXD[3:0]
TX_EN
TX_ER/TXD4
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
LP
Filter
COL
RX_CLK
RXD[3:0]
CRS
RX_DV
RX_ER/RXD4
Manchester
Encoder
Controller
Interface
(MII
or
FBI)
ROM
DAC
Clock
Generator
PLL
Collision
100BASE-TX Receiver
PLED[3:0]n
MDA[3:0]n
PLED[5:4]n
Serial
Port
(MI)
LED
Drivers
4B5B
Decoder
Descrambler
Clock
& Data
Recovery
AutoNegotiation
& Link
Squelch
Vth
+/− Vth
+
+
−
Squelch
MDC
MDIO
MDINTn/MDA4n
SD_THR
SD/FXDISn
+
−
100BASE-TX Receiver
+/− Vth
MLT3
Encoder
+
+
−
Adaptive
Equalizer
10BASE-TX Receiver
+/− Vth
VDD[6:1]
GND[6:1]
2-3
Clock & Data
Recovery
(Manchester
Decoder)
+
+
−
LP
Filter
TPI+/FXO−
TPI−/FXO+
Draft 6/5/00
Overview
Rev. letter
RX_EN/JAMn
RPTR
Draft 6/5/00
Figure 2.2
100BASE-TX/FX and 10BASE-T Frame Format
Ethernet MAC Frame
Interframe
Gap
PREAMBLE
SFD
DA
SA
LN
LLC Data
FCS
LN
LLC DATA
FCS
Interframe
Gap
100BASE-TX Data Symbols
IDLE
SSD
PREAMBLE
SFD
DA
SA
IDLE = [ 1 1 1 1 ...]
SSD = [ 1 1 0 0 0 1 0 0 0 1 ]
PREAMBLE = [ 1 0 1 0 ...] 62 Bits Long
SFD = [ 1 1 ]
DA, SA, LN, LLC DATA, FCS = [ DATA ]
ESD = [ 0 1 1 0 1 0 0 1 1 1 ]
ESD
IDLE
ESD
IDLE
SOI
IDLE
Before/After
4B5B Encoding,
Scrambling, and
MLT3 Coding
100BASE-FX Data Symbols
IDLE
SSD
PREAMBLE
SFD
DA
SA
LN
IDLE = [ 1 1 1 1 ...]
SSD = [ 1 1 0 0 0 1 0 0 0 1 ]
PREAMBLE = [ 1 0 1 0 ...] 62 Bits Long
SFD = [ 1 1 ]
DA, SA, LN, LLC DATA, FCS = [ DATA ]
ESD = [ 0 1 1 0 1 0 0 1 1 1 ]
LLC DATA
FCS
Before/After
4B5B Encoding
10BASE-T Data Symbols
IDLE
PREAMBLE
SFD
DA
SA
LN
LLC DATA
FCS
IDLE = [ No Transitions ]
PREAMBLE = [ 1 0 1 0 ...] 62 Bits Long
SFD = [ 1 1 ]
DA, SA, LN, LLC DATA, FCS = [ DATA ]
SOI = [ 1 1 ] With No MID Bit
Transition
2-4
Before/After
Manchester
Encoding
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
2.1.2.1 100BASE-TX
In 100BASE-TX transmit operation, data is received on the Controller
Interface from an external Ethernet controller according to the format
shown in Figure 2.3 and Table 2.1. The data is sent to the 4B5B encoder,
which scrambles the encoded data. The scrambled data is then sent to
the TP transmitter. The TP transmitter converts the encoded and
scrambled data into MLT3 ternary format, preshapes the output, and
drives the twisted-pair cable.
Figure 2.3
MII Frame Format
a. MII Frame Format
TX_EN = 0
TX_EN = 1
IDLE
PREAMBLE
Start
of
Frame
PRMBLE
SFD
62 Bits
2 Bits
TX_EN = 0
DATA Nibbles
DATA 1
DATA 2
IDLE
DATA N-1 DATA N
PREAMBLE = [ 1 0 1 0 ...] 62 Bits Long
SFD = [ 1 1 ]
DATAn = [Between 64−1518 Data Bytes]
IDLE = [TX_EN = 0]
b. MII Nibble Order
First Bit
MAC Serial Bit Stream
D1
D0
LSB
D2
D3
D4
D5
D6
D7
MSB
Second
Nibble
First
Nibble
TXD0/RXD0
TXD1/RXD1
TXD2/RXD2
TXD3/RXD3
MII
Nibble
Stream
Table 2.1
Transmit Preamble and SFD Bits at MAC Nibble Interface
Signals
Bit Value
TXDO
X
X
11
1
1
1
1
1
1
1
1
1
1
1
1
1
12
1
D03 D44
TXD1
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D1
D5
TXD2
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D2
D6
TXD3
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
D3
D7
TX_EN
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1.
2.
3.
4.
1st
1st
1st
D0
preamble nibble transmitted.
SFD nibble transmitted.
data nibble transmitted.
through D7 are the first 8 bits of the data field.
Overview
2-5
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
In 100BASE-TX receive operation, the TP receiver takes incoming
encoded and scrambled MLT3 data from the twisted-pair cable, removes
any high-frequency noise from the input, equalizes the input signal to
compensate for the effects of the cable, performs baseline wander
correction, qualifies the data with a squelch algorithm, and converts the
data from MLT3-encoded levels to internal digital levels. The output of the
receiver then goes to a clock and data recovery block that recovers a
clock from the incoming data, uses the clock to latch valid data into the
device, and converts the data back to NRZ format. The 4B5B decoder
and descrambler then decodes and unscrambles the NRZ data,
respectively, and sends it out of the Controller Interface to an external
Ethernet controller. The format of the received data at the Controller
interface is as shown in Table 2.2.
Table 2.2
Receive Preamble and SFD Bits at MAC Nibble Interface
Signals
Bit Value
RXDO
X
11
1
1
1
1
1
1
1
1
1
1
1
1
1
1
12
1
D03 D44
RXD1
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D1
D5
RXD2
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D2
D6
RXD3
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
D3
D7
RX_DV
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1. First preamble nibble received. Depending on the mode, the device may eliminate either all or some
of the preamble nibbles, up to the first SFD nibble.
2. First SFD nibble received.
3. First data nibble received.
4. D0 through D7 are the first 8 bits of the data field.
2.1.2.2 100BASE-FX
100BASE-FX operation is similar to 100BASE-TX operation except:
2-6
•
The transmit output/receive input is not scrambled or MLT3 encoded
•
The transmit data is output to a FX transmitter instead of the TP
waveshaper/ transmitter
•
The receive data is input to the FX ECL level detector instead of the
equalizer and associated TP circuitry
•
The FX Interface has a signal detect input
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
2.1.2.3 10BASE-T
10BASE-T operation is similar to the 100BASE-TX operation except:
•
There is no scrambler/descrambler
•
The encoder/decoder is Manchester instead of 4B5B
•
The data rate is 10 Mbits/s instead of 100 Mbits/s,
•
The twisted-pair symbol data is two-level Manchester instead of
ternary MLT-3.
•
The transmitter generates link pulses during the idle period
•
The transmitter detects the jabber condition
•
The receiver detects link pulses and implements the AutoNegotiation
algorithm
2.2 Block Diagram Description
The L80223 PHY device has the following main blocks:
•
Oscillator and Clock
•
Controller Interface
•
4B5B/Manchester Encoder/Decoder
•
Scrambler/Descrambler
•
Twisted-Pair Transmitters
•
Fiber Transmitter
•
Twisted-Pair Receivers
•
Fiber Receiver
•
Clock and Data Recovery
•
AutoNegotiation/Link Integrity
•
Descrambler
•
Collision Detection
•
LED Drivers
A Management Interface (MI) serial port provides access to 11 internal
PHY registers.
Block Diagram Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-7
Draft 6/5/00
Figure 2.1 shows the main blocks, along with their associated signals.
The following sections describe each of the blocks in Figure 2.1. The
performance of the device in both the 10 and 100 Mbits/s modes is
described.
2.2.1 Oscillator and Clock
The L80223 requires a 25 MHz reference frequency for internal signal
generation. This 25 MHz reference frequency is generated with either an
external 25 MHz crystal connected between OSCIN and GND or with the
application of an external 25-MHz clock to OSCIN.
The device provides either a 2.5-MHz or 25-MHz reference clock at the
TX_CLK or RX_CLK output pins for 10-MHz or 100-MHz operation,
respectively.
2-8
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
2.2.2 Controller Interface
This section describes the controller interface operation. The L80223 has
two interfaces to an external controller:
•
Media Independent Interface (MII)
•
Five Bit Interface (FBI)
2.2.2.1 MII Interface
The device has an MII interface to an external Ethernet Media Access
Controller (MAC).
MII (100 Mbits/s) – The MII is a nibble wide packet data interface
defined in IEEE 802.3 and shown in Figure 2.3. The L80223 meets all
the MII requirements outlined in IEEE 802.3. The L80223 can directly
connect, without any external logic, to any Ethernet controller or other
device that also complies with the IEEE 802.3 MII specifications.
The MII interface contains the following signals:
•
Transmit data bits (TXD[3:0])
•
Transmit clock (TX_CLK)
•
Transmit enable (TX_EN)
•
Transmit error (TX_ER)
•
Receive data bits (RXD[3:0])
•
Receive clock (RX_CLK)
•
Carrier sense (CRS)
•
Receive data valid (RX_DV)
•
Receive data error (RX_ER)
•
Collision (COL)
The transmit and receive clocks operate at 25 MHz in 100 Mbits/s mode.
On the transmit side, the TX_CLK output runs continuously at 25 MHz.
When no data is to be transmitted, TX_EN must be deasserted. While
TX_EN is deasserted, TX_ER and TXD[3:0] are ignored and no data is
clocked into the device. When TX_EN is asserted on the rising edge of
TX_CLK, data on TXD[3:0] is clocked into the device on the rising edge
Block Diagram Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-9
Draft 6/5/00
of the TX_CLK output clock. TXD[3:0] input data is nibble wide packet
data whose format must be the same as specified in IEEE 802.3 and
shown in Figure 2.3. When all data on TXD[3:0] has been latched into
the device, TX_EN must be deasserted on the rising edge of TX_CLK.
TX_ER is also clocked in on the rising edge of TX_CLK. TX_ER is a
transmit error signal. When this signal is asserted, the device substitutes
an error nibble in place of the normal data nibble that was clocked in on
TXD[3:0]. The error nibble is defined to be the /H/ symbol, which is
defined in IEEE 802.3 and shown in Table 2.3.
Table 2.3
2-10
4B/5B Symbol Mapping
Symbol
Name
Description
5B Code
4B Code
0
Data 0
0b11110
0b0000
1
Data 1
0b01001
0b0001
2
Data 2
0b10100
0b0010
3
Data 3
0b10101
0b0011
4
Data 4
0b01010
0b0100
5
Data 5
0b01011
0b0101
6
Data 6
0b01110
0b0110
7
Data 7
0b01111
0b0111
8
Data 8
0b10010
0b1000
9
Data 9
0b10011
0b1001
A
Data A
0b10110
0b1010
B
Data B
0b10111
0b1011
C
Data C
0b11010
0b1100
D
Data D
0b11011
0b1101
E
Data E
0b11100
0b1110
F
Data F
0b11101
0b1111
I
Idle
0b11111
0b0000
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Table 2.3
4B/5B Symbol Mapping (Cont.)
Symbol
Name
Description
5B Code
4B Code
J
SSD #1
0b11000
0b0101
K
SSD #2
0b10001
0b0101
T
ESD #1
0b01101
0b0000
R
ESD #2
0b00111
0b0000
H
Halt
0b00100
Undefined
–
Invalid codes
All others1
0b0000*
1. These 5B codes are not used. The decoder decodes these 5B codes to
4B 0000. The encoder encodes 4B 0000 to 5B 11110, as shown in symbol
Data 0.
Because the OSCIN input clock generates the TX_CLK output clock, the
TXD[3:0], TX_EN, and TX_ER signals are also clocked in on rising
edges of OSCIN.
On the receive side, as long as a valid data packet is not detected, CRS
and RX_DV are deasserted and the RXD[3:0] signals are held LOW.
When the start of packet is detected, CRS and RX_DV are asserted on
the falling edge of RX_CLK. The assertion of RX_DV indicates that valid
data is clocked out on RXD[3:0] on the falling edge of the RX_CLK. The
RXD[3:0] data has the same frame structure as the TXD[3:0] data and
is specified in IEEE 802.3 and shown in Figure 2.3. When the end of the
packet is detected, CRS and RX_DV are deasserted, and RXD[3:0] is
held LOW. CRS and RX_DV also stay deasserted if the device is in the
Link Fail State.
RX_ER is a receive error output that is asserted when certain errors are
detected on a data nibble. RX_ER is asserted on the falling edge of
RX_CLK for the duration of that RX_CLK clock cycle during which the
nibble containing the error is output on RXD[3:0].
The collision output, COL, is asserted whenever the collision condition is
detected.
MII (10 Mbits/s) – MII 10 Mbits/s operation is identical to 100 Mbits/s
operation except:
Block Diagram Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-11
Draft 6/5/00
•
The TX_CLK and RX_CLK clock frequency is reduced to 2.5 MHz
•
TX_ER is ignored
•
RX_ER is disabled and always held LOW
•
Receive operation is modified as follows:
On the receive side, when the squelch circuit determines that invalid
data is present on the TP inputs, the receiver is idle. During idle,
RX_CLK follows TX_CLK, RXD[3:0] is held LOW, and CRS and
RX_DV are deasserted. When a start of packet is detected on the
TP receive inputs, CRS is asserted and the clock recovery process
starts on the incoming TP input data. After the receive clock has
been recovered from the data, the RX_CLK is switched over to the
recovered clock and the data valid signal RX_DV is asserted on a
falling edge of RX_CLK. Once RX_DV is asserted, valid data is
clocked out on RXD[3:0] on the falling edge of RX_CLK. The
RXD[3:0] data has the same packet structure as the TXD[3:0] data
and is formatted on RXD[3:0] as specified in IEEE 802.3 and shown
in Figure 2.3. When the end of packet is detected, CRS and RX_DV
are deasserted. CRS and RX_DV also stay deasserted as long as
the device is in the Link Fail State.
2.2.2.2 FBI Interface
The Five Bit Interface (also referred to as FBI) is a five-bit wide interface
that is produced when the 4B5B encoder/decoder is bypassed. The FBI
is primarily used for repeaters or Ethernet controllers that have integrated
encoder/decoders.
The FBI is identical to the MII except:
2-12
•
The FBI data path is five bits wide, not nibble wide like the MII
•
The TX_ER pin is reconfigured to be the fifth transmit data bit
(TXD4)
•
The RX_ER pin is reconfigured to be the fifth receive data bit (RXD4)
•
CRS is asserted as long as the device is in the Link Pass State
•
COL is not valid
•
RX_DV is not valid
•
The TX_EN pin is ignored
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
There is no FBI operation in the 10 Mbits/s mode.
2.2.2.3 Selection of MII or FBI
FBI Selection – The FBI is automatically enabled when the 4B5B
encoder/decoder is bypassed. Bypassing the encoder/decoder passes
the 5B symbols between the receiver/transmitter directly to the FBI
without any alterations or substitutions. To bypass the 4B5B
encoder/decoder, set the Bypass Encoder bit (BYP_ENC) in the MI serial
port Configuration 1 register.
When the FBI is enabled, it may also be desirable to bypass the
scrambler/descrambler and disable the internal CRS loopback function.
To bypass the scrambler/descrambler, set the Bypass Scrambler bit
(BYP_SCR) in the MI serial port Configuration 1 register. To disable the
internal CRS loopback, set the TX_EN to CRS loopback disable bit
(TXEN_CRS) in the MI serial port Configuration 1 register.
MII Selection – To disable the MII (and FBI) inputs and outputs, set the
MII_DIS bit in the MI serial port Control register. When the MII is
disabled, the MII and FBI inputs are ignored, and the MII, FBI, and TPI
outputs are placed in a high-impedance state. The MII pins affected are:
•
RX_CLK
•
RXD[3:0]
•
RX_DV
•
RX_ER
•
COL
If the MI address lines, MDA[4:0]n, are pulled HIGH during reset or
powerup, the L80223 powers up and resets with the MII and FBI
disabled. Otherwise, the L80223 powers up and resets with the MII and
FBI enabled.
In addition, when the R/J_CFG bit in the MI serial port Configuration 1
register is LOW, the RX_EN/JAMn pin is configured for RX_EN
operation. If the RX_EN pin is LOW in this situation, the MII controller
interface outputs are placed in the high-impedance state.
Block Diagram Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-13
Draft 6/5/00
2.2.3 Encoder
This section describes the 4B5B encoder, which is used in 100 Mbits/s
operation. It also describes the Manchester Encoder, used in 10BASE-T
operation.
2.2.3.1 4B5B Encoder (100 Mbits/s)
100BASE-TX operation requires that the data be 4B5B encoded. The
4B5B Encoder block shown in Figure 2.1 converts the four-bit data
nibbles into five-bit data words. The mapping of the 4B nibbles to 5B
codewords is specified in IEEE 802.3 and is shown in Table 2.4.
Table 2.4
2-14
4B/5B Symbol Mapping
Symbol Name
Description
5B Code
4B Code
0
Data 0
11110
0000
1
Data 1
01001
0001
2
Data 2
10100
0010
3
Data 3
10101
0011
4
Data 4
01010
0100
5
Data 5
01011
0101
6
Data 6
01110
0110
7
Data 7
01111
0111
8
Data 8
10010
1000
9
Data 9
10011
1001
A
Data A
10110
1010
B
Data B
10111
1011
C
Data C
11010
1100
D
Data D
11011
1101
E
Data E
11100
1110
F
Data F
11101
1111
I
Idle
11111
0000
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Table 2.4
4B/5B Symbol Mapping (Cont.)
Symbol Name
Description
5B Code
4B Code
J
SSD #1
11000
0101
K
SSD #2
10001
0101
T
ESD #1
01101
0000
R
ESD #2
00111
0000
H
Halt
00100
Undefined
---
Invalid codes
All others1
0000
1. These 5B codes are not used. The decoder converts them
to a 4B code of 0000. The encoder converts the 4B 0000
code to the 5B 11110 code, as shown in symbol 0.
The 4B5B encoder takes 4B (four-bit) nibbles from the Transmit MAC
block, converts them into 5B (five-bit) words according to Table 2.4, and
sends the 5B words to the scrambler. The 4B5B encoder also substitutes
the first eight bits of the preamble with the Start of Stream Delimiter
(SSD) (/J/K/ symbols) and adds an End of Stream Delimiter (ESD) (/T/R/
symbols) to the end of each packet, as defined in IEEE 802.3 and shown
in Figure 2.2. The 4B5B encoder also fills the period between packets
(idle period), with a continuous stream of idle symbols, as shown in
Figure 2.2.
2.2.3.2 Manchester Encoder (10 Mbits/s)
The Manchester Encoder shown in Figure 2.1 is used for 10 Mbits/s
operation. It combines clock and non-return to zero inverted (NRZI) data
such that the first half of the data bit contains the complement of the
data, and the second half of the data bit contains the true data, as
specified in IEEE 802.3. This process guarantees that a transition always
occurs in the middle of the bit cell. The Manchester encoder on the
device converts the 10 Mbits/s NRZI data from the Ethernet controller
interface into a single data stream for the TP transmitter and adds a start
of idle pulse (SOI) at the end of the packet as specified in IEEE 802.3
and shown in Figure 2.2. The Manchester encoding process is only done
on actual packet data; during the idle period between packets, no signal
is transmitted except for periodic link pulses.
Block Diagram Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-15
Draft 6/5/00
2.2.3.3 Encoder Bypass
Setting the Bypass Encoder/Decoder bit (BYP_ENC) in the MI serial port
Configuration 1 register bypasses the 4B5B encoder. When this bit is set,
5B code words are passed directly from the controller interface to the
scrambler without any of the alterations described in Section 2.2.3.1,
“4B5B Encoder (100 Mbits/s),” page 2-14. Setting the bit automatically
places the device in the FBI mode as described in the subsection entitled
“FBI Selection” on page 2-13.
2.2.4 Decoder
This section describes the 4B5B decoder, used in 100 Mbits/s operation,
which converts 5B encoded data to 4B nibbles. It also describes the
Manchester Decoder, used in 10BASE-T operation.
2.2.4.1 4B5B Decoder (100 Mbits/s)
Because the TP input data is 4B5B encoded on the transmit side, the
4B5B decoder must decode it on the receive side. The mapping of the
5B codewords to the 4B nibbles is specified in IEEE 802.3. The 4B5B
decoder takes the 5B codewords from the descrambler, converts them
into 4B nibbles according to Table 2.4, and sends the 4B nibbles to the
receive Ethernet controller.
The 4B5B decoder also strips off the SSD delimiter (/J/K/ symbols), and
replaces it with two 4B Data 5 nibbles (/5/ symbol). It also strips off the
ESD delimiter (/T/R/ symbols), and replaces it with two 4B Data 0 nibbles
(/I/ symbol), per IEEE 802.3 specifications (see Figure 2.2).
The 4B5B decoder detects SSD, ESD, and codeword errors in the
incoming data stream as specified in IEEE 802.3. To indicate these
errors, the device asserts the RX_ER output as well as the SSD, ESD,
and CWRD bits in the MI serial port Status Output register while the
errors are being transmitted across RXD[3:0].
2.2.4.2 Manchester Decoder (10 Mbits/s)
In Manchester coded data, the first half of the data bit contains the
complement of the data, and the second half of the data bit contains the
true data. The Manchester Decoder converts the single data stream from
the TP receiver into non-return to zero (NRZ) data for the controller
2-16
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
interface. To do this, it decodes the data and strips off the SOI pulse.
Because the Clock and Data Recovery block has already separated the
clock and data from the TP receiver, that block inherently performs the
the Manchester decoding.
2.2.4.3 Decoder Bypass
Setting the Bypass Encoder/Decoder bit (BYP_ENC) in the MI serial port
Configuration 1 register bypasses the 4B5B decoder. When this bit is set,
5B code words are passed directly to the controller interface from the
descrambler without any of the alterations described in Section 2.2.4,
“Decoder,” page 2-16. Additionally, the CRS pin is continuously asserted
whenever the device is in the Link Pass state. Setting the bit
automatically places the device in the FBI mode as described in the
subsection entitled “FBI Selection” on page 2-13.
2.2.5 Scrambler
100BASE-TX transmission requires scrambling to reduce the radiated
emissions on the twisted pair. The scrambler takes the NRZI encoded
data from the 4B5B encoder, scrambles it per the IEEE 802.3
specifications, and sends it to the TP transmitter. A scrambler is not used
for 10 Mbits/s operation.
2.2.5.1 Scrambler Bypass
Setting the Bypass Encoder/Decoder bit (BYP_SCR) in the MI serial port
Configuration 1 register bypasses the scrambler. When this bit is set, 5B
data bypasses the scrambler and goes directly to the 100BASE-TX
transmitter.
2.2.6 Descrambler
The descrambler block shown in Figure 2.1 is used in 100BASE-TX
operation. The device descrambler takes the scrambled NRZI data from
the data recovery block, descrambles it according to IEEE 802.3
specifications, aligns the data on the correct 5B word boundaries, and
sends it to the 4B5B decoder.
The algorithm for synchronization of the descrambler is the same as the
algorithm outlined in the IEEE 802.3 specification.
Block Diagram Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-17
Draft 6/5/00
After the descrambler is synchronized, it maintains synchronization as
long as enough descrambled idle pattern ones are detected within a
given interval. To stay in synchronization, the descrambler needs to
detect at least 25 consecutive descrambled idle pattern ones in a 1 ms
interval. If 25 consecutive descrambled idle pattern ones are not
detected within the 1 ms interval, the descrambler goes out of
synchronization and restarts the synchronization process.
If the descrambler is in the unsynchronized state, the descrambler Loss
of Synchronization Detect bit (LOSS_SYNC) is set in the MI serial port
Status Output register. The bit stays set until the descrambler achieves
synchronization.
The descrambler is disabled for 10BASE-T operation.
2.2.6.1 Descrambler Bypass
Setting the Bypass Encoder/Decoder bit (BYP_SCR) in the MI serial port
Configuration 1 register bypasses the descrambler. When this bit is set,
5B data bypasses the descrambler and goes directly from the
100BASE-T receiver to the 4B5B decoder.
2-18
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
2.2.7 Twisted-Pair Transmitters
This section describes the operation of the 10 and 100 Mbits/s TP
transmitters.
2.2.7.1 100 Mbits/s TP Transmitter
The TP transmitter consists of an MLT3 encoder, waveform generator,
and line driver.
The MLT3 encoder converts the NRZI data from the scrambler into a
three-level code required by IEEE 802.3. MLT3 coding uses three levels,
converting ones to transitions between the three levels, and zeros to no
transitions or changes in level.
The purpose of the waveform generator is to shape the transmit output
pulse. The waveform generator takes the MLT3 three level encoded
waveform and uses an array of switched current sources to control the
shape of the twisted-pair output signal. The waveform generator consists
of switched current sources, a clock generator, filter, and logic. The
switched current sources control the rise and fall time as well as signal
level to meet IEEE 802.3 requirements. The output of the switched
current sources goes through a second order low-pass filter that
“smooths” the current output and removes any high-frequency
components. In this way, the waveform generator preshapes the output
waveform transmitted onto the twisted-pair cable such that the waveform
meets the pulse template requirements outlined in IEEE 802.3. The
waveform generator eliminates the need for any external filters on the TP
transmit output.
The line driver converts the shaped and smoothed waveform to a current
output that can drive greater than 100 meters of category 5 unshielded
twisted-pair cable or 150-ohm shielded twisted-pair cable.
2.2.7.2 10 Mbits/s TP Transmitter
Even though the 10 Mbits/s transmitter operation is much different than
that of 100 Mbits/s, it also consists of a waveform generator and line
driver (see Figure 2.1).
The waveform generator, which consists of a ROM, DAC, clock
generator, and filter, shapes the output transmit pulse. The DAC
Block Diagram Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
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Draft 6/5/00
generates a stair-stepped representation of the desired output waveform.
The stairstepped DAC output then is passed through a low-pass filter to
“smooth” the DAC output and remove any high-frequency components.
The DAC values are determined from the data at the ROM addresses.
The data is chosen to shape the pulse to the desired template. The clock
generator clocks the data into the DAC at high speed. In this way, the
waveform generator preshapes the output waveform to be transmitted
onto the twisted-pair cable to meet the pulse template requirements
outlined in IEEE 802.3 Clause 14 and shown in Figure 2.4 and Table 2.5.
The waveshaper replaces and eliminates external filters on the TP
transmit output.
The line driver converts the shaped and smoothed waveform to a current
output that can drive greater than 100 meters of category 3/4/5 100-ohm
unshielded twisted-pair cable or 150-ohm shielded twisted-pair cable
without any external filters.
During the idle period, no output signals are transmitted on the TP
outputs except for link pulses.
Figure 2.4
TP Output Voltage Template
Voltage (V)
N
B
1.0
0.8
P
H
0.6
I
D
0.4
O
E
C
0.2
0.0
Q
A
M
F
R
J
S
- 0.2
- 0.4
U
LK
- 0.6
W
V
- 0.8
G
- 1.0
0
10
20
30
40
50
T
60
70
80
90
100
110
Time (ns)
2-20
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
T
Table 2.5
TP Output Voltage - 10 Mbits/s
Reference
Time (ns) Internal MAU
Voltage (V)
A
0
0
B
15
1.0
C
15
0.4
D
25
0.55
E
32
0.45
F
39
0
G
57
−1.0
H
48
0.7
I
67
0.6
J
89
0
K
74
−0.55
L
73
−0.55
M
61
0
N
85
1.0
O
100
0.4
P
110
0.75
Q
111
0.15
R
111
0
S
111
−0.15
T
110
−1.0
U
100
−0.3
V
110
−0.7
W
90
−0.7
Block Diagram Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-21
Draft 6/5/00
2.2.7.3 Transmit Level Adjust
The transmit output current level is derived from an internal reference
voltage and the external resistor on the REXT pin. The transmit level can
be adjusted with either:
•
The external resistor on the REXT pin, or
•
The four Transmit Level Adjust bits (TLVL[3:0]) in the MI serial port
Configuration 1 register as shown in Table 2.6. The adjustment range
is approximately -14% to +16% in 2% steps.
Table 2.6
2-22
Transmit Level Adjust
TLVL[3:0]
Bits
Gain
0000
1.16
0001
1.14
0010
1.12
0011
1.10
0100
1.08
0101
1.06
0110
1.04
0111
1.02
1000
1.00
1001
0.98
1010
0.96
1011
0.94
1100
0.92
1101
0.90
1110
0.88
1111
0.86
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
2.2.7.4 Transmit Rise and Fall Time Adjust
The transmit output rise and fall time can be adjusted with the two
Transmit Rise/Fall time adjust bits (TRF[1:0]) in the MI serial port
Configuration 1 register. The adjustment range is −0.25 ns to +0.5 ns in
0.25 ns steps.
2.2.7.5 STP (150 Ohm) Cable Mode
The transmitter can be configured to drive 150 Ω shielded twisted-pair
cable. To enable this configuration, set the Cable Type Select bit
(CABLE) in the MI serial port Configuration 1 register. When STP mode
is enabled, the output current is automatically adjusted to comply with
IEEE 802.3 levels.
2.2.7.6 Transmit Activity Indication
Appropriately setting the programmable LED Output Select bits in the MI
serial port LED Configuration 2 register programs transmit activity to
appear on some of the PLED[5:0]n pins. When one or more of the
PLED[5:0]n pins is programmed to be an activity or transmit activity
detect output, that pin is asserted LOW for 100 ms every time a transmit
packet occurs. The PLED[5:0]n outputs are open-drain with resistor
pullup and can drive an LED from VDD or can drive other digital inputs.
See Section 2.2.14, “LED Drivers,” page 2-37 for more detailed
information on the LED outputs.
2.2.7.7 Transmit Disable
Setting the Transmit Disable bit (XMT_DIS) in the MI serial port
Configuration 1 register disables the TP transmitter. When the bit is set,
the TP transmitter is forced into the idle state, no data is transmitted, no
link pulses are transmitted, and internal loopback is disabled.
2.2.7.8 Transmit Powerdown
Setting the Transmit Powerdown bit (XMT_PDN) in the MI serial port
Configuration 1 register powers down the TP transmitter. When the bit is
set, the TP transmitter is powered down, the TP transmit outputs are high
impedance, and the rest of the L80223 operates normally.
Block Diagram Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-23
Draft 6/5/00
2.2.8 Twisted-Pair Receivers
The device is capable of operating at either 10- or 100-Mbits/s. This
section describes the twisted-pair receivers and squelch operation for
both modes of operation.
2.2.8.1 100 Mbits/s TP Receiver
The TP receiver detects input signals from the twisted-pair input and
converts them to a digital data bit stream ready for clock and data
recovery. The receiver can reliably detect 100BASE-TX compliant
transmitter data that has been passed through 0 to 100 meters of
100 Ω category 5 UTP or 150-ohm STP cable.
The 100 Mbits/s receiver consists of an adaptive equalizer, baseline
wander correction circuit, comparators, and an MLT3 decoder. The TP
inputs first go to an adaptive equalizer. The adaptive equalizer
compensates for the low-pass characteristics of the cable, and can adapt
and compensate for 0 to 100 meters of category 5, 100-ohm or 150-ohm
STP cable. The baseline wander correction circuit restores the DC
component of the input waveform that the external transformers have
removed. The comparators convert the equalized signal back to digital
levels and qualify the data with the squelch circuit. The MLT3 decoder
takes the three-level MLT3 encoded output data from the comparators
and converts it to normal digital data to be used for clock and data
recovery.
2.2.8.2 10 Mbits/s TP Receiver
The 10 Mbits/s receiver detects input signals from the twisted-pair cable
that are within the template shown in Figure 2.5 The TP inputs are
biased by internal resistors and go through a low-pass filter designed to
eliminate any high-frequency input noise. The output of the receive filter
goes to two different types of comparators: squelch and zero crossing.
The squelch comparator determines whether the signal is valid, and the
zero crossing comparator senses the actual data transitions after the
signal is determined to be valid. The output of the squelch comparator
goes to the squelch circuit and is also used for link pulse detection, SOI
detection, and reverse polarity detection. The output of the zero-crossing
comparator is used for clock and data recovery in the Manchester
decoder.
2-24
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Figure 2.5
TP Input Voltage Template (10 Mbits/s)
Short Bit
3.1 V
Slope 0.5 V/ns
585 mV
585 mV sin (π ∗ t/PW)
0
Long Bit
PW
3.1 V
Slope 0.5 V/ns
585 mV
585 mV sin (π ∗ t/PW)
585 mV sin[2 π (t − PW2)/PW)]
0
PW/4
3PW/4
PW
2.2.8.3 Squelch (100 Mbits/s)
The Squelch block determines if the TP input contains valid data. The
100 Mbits/s TP squelch is one of the criteria used to determine link
integrity. The squelch comparators compare the TP inputs against fixed
positive and negative thresholds, called squelch levels. The output from
the squelch comparator goes to a digital squelch circuit, which
determines whether the receive input data on that port is valid. If the data
is invalid, the receiver is in the squelched state. If the input voltage
exceeds the squelch levels at least four times with alternating polarity
within a 10 µs interval, the squelch circuit determines that the data is
valid and the receiver enters into the unsquelch state.
In the unsquelch state, the receive threshold level is reduced by
approximately 30% for noise immunity reasons and is called the
unsquelch level. When the receiver is in the unsquelch state, the input
signal is considered valid.
The device stays in the unsquelch state until loss of data is detected.
Loss of data is detected if no alternating polarity unsquelch transitions
Block Diagram Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-25
Draft 6/5/00
are detected during any 10 µs interval. When a loss of data is detected,
the receive squelch is turned on again.
2.2.8.4 Squelch (10 Mbits/s)
The TP squelch algorithm for 10 Mbits/s mode is identical to the
100 Mbits/s mode, except:
•
The 10 Mbits/s TP squelch algorithm is not used for link integrity, but
to sense the beginning of a packet
•
The receiver goes into the unsquelch state if the input voltage
exceeds the squelch levels for three bit times with alternating polarity
within a 50 to 250 ns interval
•
The receiver goes into the squelch state when SOI is detected
•
Unsquelch detection has no effect on link integrity (link pulses are
used in 10 Mbits/s mode for that purpose)
•
Start of packet is determined when the receiver goes into the
unsquelch state and CRS is asserted
•
The receiver meets the squelch requirements defined in IEEE 802.3
Clause 14.
2.2.8.5 Equalizer Disable
Setting the Equalizer Disable bit (EQLZR) in the MI serial port
Configuration 1 register disables the adaptive equalizer. When disabled,
the equalizer is forced into the response it would normally have if zero
cable length was detected.
2.2.8.6 Receive Level Adjust
Setting the Receive Level Adjust bit (RLV0) in the MI serial port
Configuration 1 register lowers the receiver squelch and unsquelch levels
by 4.5 dB. Setting this bit may allow the device to support longer cable
lengths.
2.2.8.7 Receive Activity Indication
Appropriately setting the programmable LED output select bits in the MI
serial port LED Configuration 2 register programs receive activity to
appear on some of the PLED[5:0]n pins. When one or more of the
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Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
PLED[5:0]n pins is programmed to be a receive activity or activity detect
output, that pin is asserted LOW for 100 ms every time a receive packet
occurs. The PLED[5:0]n outputs are open-drain with resistor pullup and
can drive an LED from VDD or can drive another digital input. See
Section 2.2.14, “LED Drivers,” page 2-37 for more detailed information on
the LED outputs.
2.2.9 FX Transmitter and Receiver
The FX transmitter and receiver implement the 100BASE-FX function
defined in IEEE 802.3. 100BASE-FX is intended for transmission and
reception of data over fiber and is specified to operate at 100 Mbits/s.
Thus, the FX transmitter and receiver in the device only operate when
the device is placed in 100 Mbits/s mode.
2.2.9.1 Transmitter
The FX transmitter converts data from the 4B5B encoder into binary
NRZI data and outputs the data onto the FXO+/- pins. The output driver
is a differential current source that is able to drive a 100 Ω load to ECL
levels. The FXO+/- pins can directly drive an external fiber optic
transceiver. The FX transmitter meets all the requirements defined in
IEEE 802.3.
The FX transmit output current level is derived from an internal reference
voltage and the external resistor on the REXT pin. The FX transmit level
can be adjusted with this resistor or it can also be adjusted with the two
FX Transmit Level Adjust bits (FXLVL[1:0]) in the MI serial port Mask
register as shown in Table 2.7.
Table 2.7
FX Transmit Level Adjust
FXLVL[1:0]
Bits
Gain
11
1.30
10
1.15
01
0.85
00
1.00
Block Diagram Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-27
Draft 6/5/00
2.2.9.2 Receiver
The FX receiver:
•
Converts the differential ECL inputs on the FXI+/- pins to a digital bit
stream
•
Validates the data on FXI+/- with the SD/FXDISn input pin
•
Enable or disables the FX interface with the SD/FXDISn pin.
The FX receiver meets all requirements defined in IEEE 802.3.
The input to the FXI+/- pins can be directly driven from a fiber optic
transceiver and first goes to a comparator. The comparator compares the
input waveform against the internal ECL threshold levels to produce a
low jitter serial bit stream with internal logic levels. The data from the
comparator output is then passed to the clock and data recovery block,
provided that the signal detect input, SD/FXDISn, is asserted.
Signal Detect – The FX receiver has a signal detect input pin,
SD/FXDISn, which indicates whether the incoming data on FXI+/- is valid
or not. The SD/FXDISn input can be driven directly from an external fiber
optic transceiver and meets all requirements defined in the IEEE 802.3
specifications.
The SD/FXDISn input goes directly to a comparator. The comparator
compares the input waveform against the internal ECL threshold level to
produce a digital signal with internal logic levels. The output of the signal
detect comparator then goes to the link integrity and squelch blocks. If
the SD/FXDISn input is asserted, the device is placed in the Link Pass
state and the input data on FXI+/- is determined to be valid. If the
SD/FXDISn input is deasserted, the device is placed in the Link Fail state
and the input data on FXI+/- is determined to be invalid.
The SD_THR pin adjusts the ECL trip point of the SD/FXDISn input.
When the SD_THR pin is tied to a voltage between GND and GND +
0.45V, the trip point of the SD/FXDISn ECL input buffer is internally set
to VDD − 1.3 V. When the SD_THR pin is set to a voltage greater than
GND + 0.85 V, the trip point of the SD/FXDISn ECL input buffer is set to
the voltage that is applied to the SD_THR pin. The trip level for the
SD/FXDISn input buffer must be set to VDD − 1.3 V. Having external
control of the SD/FXDISn buffer trip level with the SD_THR pin allows
this trip level to be referenced to an external supply, which facilitates
2-28
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
connection to an external fiber optic transceiver. If the device is to be
connected to a 3.3V external fiber optic transceiver, SD_THR must be
tied to GND. If the device is to be connected to a 5V external fiber optic
transceiver, SD_THR must be tied to VDD − 1.3V, which can be
accomplished with an external resistor divider. Refer to the Appendix A,
Application Information for more details on connections to external fiber
optic transceivers.
2.2.9.3 FX Disable
The FX interface is disabled if the SD/FXDISn pin is connected to GND;
otherwise, the FX interface is enabled. Disabling the FX interface
automatically enables the TP interface. Conversely, enabling the TP
interface disables the FX interface.
Block Diagram Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-29
Draft 6/5/00
2.2.10 Clock and Data Recovery
This section describes clock and data recovery methods implemented in
the device for both the 100 Mbits/s and 10 Mbits/s modes.
2.2.10.1 100 Mbits/s Clock and Data Recovery
Clock recovery is accomplished with a phase-locked-loop (PLL). If valid
data is not present on the receive inputs, the PLL is locked to the
25-MHz TX_CLK signal. When the squelch circuit detects valid data on
the receive TP input, and if the device is in the Link Pass state, the PLL
input is switched to the incoming data on the receive inputs. The PLL
then locks on to the transitions in the incoming signal to recover the
clock. The recovered data clock is then used to generate the 25 MHz
nibble clock, RX_CLK, which clocks data into the controller interface
section.
The recovered clock extracted by the PLL latches in data from the TP
receiver to perform data recovery. The data is then converted from a
single bit stream into nibble wide data words according to the format
shown in Figure 2.3
2.2.10.2 10 Mbits/s Clock and Data Recovery
The clock recovery process for 10 Mbits/s mode is identical to the 100
Mbits/s mode except:
•
The recovered clock frequency is a 2.5 MHz nibble clock
•
The PLL is switched from TX_CLK to the TP input when the squelch
indicates valid data
•
The PLL takes up to 12 transitions (bit times) to lock onto the
preamble, so some of the preamble data symbols are lost. However,
the clock recovery block recovers enough preamble symbols to pass
at least six nibbles of preamble to the receive controller interface as
shown in Figure 2.3.
The data recovery process for 10 Mbits/s mode is identical to that of the
100 Mbits/s mode. As mentioned in the Manchester Decoder section, the
data recovery process inherently performs decoding of Manchester
encoded data from the TP inputs.
2-30
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
2.2.11 Link Integrity and AutoNegotiation
The device can be configured to implement either the standard link
integrity algorithms or the AutoNegotiation algorithm.
The standard link integrity algorithms are used solely to establish a link
to and from a remote device. The AutoNegotiation algorithm is used to
establish a link to and from a remote device and automatically configure
the device for 10 or 100 Mbits/s and Half or Full Duplex operation. The
different standard link integrity algorithms for 10 and 100 Mbits/s modes
are described in following subsections.
The AutoNegotiation algorithm in the device meets all requirements
specified in IEEE 802.3.
AutoNegotiation is only specified for 100BASE-TX and 10BASE-T
operation, and must be disabled when the device is placed in
100BASE-FX mode.
2.2.11.1 10BASE-T Link Integrity Algorithm (10 Mbits/s)
The device implements the same 10BASE-T link integrity algorithm
defined in IEEE 802.3. This algorithm uses normal link pulses (NLPs),
which are transmitted during idle periods, to determine if a device has
successfully established a link with a remote device (called Link Pass
state). The transmit link pulse meets the template requirements defined
in IEEE 802.3 and shown in Figure 2.6. Refer to IEEE 802.3 for more
details if needed.
Block Diagram Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-31
Draft 6/5/00
Figure 2.6
Link Pulse Output Voltage Template (10 Mbits/s)
1.3 BT
0 BT
3.1 V
0.5 V/ns
585 mV
0.5 BT
0.6 BT
+ 50 mV
− 50 mV
2.0 BT
200 mV
0.25 BT
300 mV
4.0 BT
+ 50 mV
− 50 mV
4.0 BT 42.0 BT
− 3.1 V
0.85 BT 2.0 BT
2.2.11.2 100BASE-TX Link Integrity Algorithm (100 Mbits/s)
Because the IEEE 802.3 specification defines 100BASE-TX to have an
active idle signal, there is no need to have separate link pulses such as
those defined for 10BASE-T. The L80223 uses the squelch criteria and
descrambler synchronization algorithm on the input data to determine if
the device has successfully established a link with a remote device (called
Link Pass state). Refer to IEEE 802.3 for more details if needed.
2.2.11.3 AutoNegotiation Algorithm
As stated previously, the AutoNegotiation algorithm is used for two
purposes:
•
To establish a link to and from a remote device
•
To automatically configure the device for either 10 or 100 Mbits/s
operation and either Half- or Full-Duplex operation.
The AutoNegotiation algorithm is the same algorithm defined in IEEE
802.3 Clause 28. AutoNegotiation uses a burst of link pulses, called fast
link pulses (FLPs), to pass up to 16 bits of signaling data back and forth
between the L80223 and a remote device. The transmit FLP pulses meet
2-32
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
the template specified in IEEE 802.3 and shown in Figure 2.6. A timing
diagram contrasting NLPs and FLPs is shown in Figure 2.7.
Figure 2.7
NLP vs FLP Link Pulse
Normal Link Pulse (NLP)
TPO
Fast Link Pulse (FLP)
TPO
D0
D1
D2
D3
D14 D15
Clock Clock Clock Clock Clock Clock Clock
Data Data Data Data Data Data
Any of the following events initiates the AutoNegotiation algorithm:
•
Power up
•
Device reset
•
The AutoNegotiation Enable (ANEG_EN) bit in the MI serial port
Control register for that port is cleared, then set
•
The AutoNegotiation Reset (ANEG_RST) bit in the MI serial port
Control register is set
•
The channel enters the Link Fail state
Once a negotiation has been initiated, the device first determines if the
remote device has AutoNegotiation capability. If the remote device is not
AutoNegotiation capable and is just transmitting either 10BASE-T or
100BASE-TX signals, the device senses it and places itself in the same
mode as the remote device.
If the device detects FLPs from the remote device, the remote device is
determined to have AutoNegotiation capability, and the device then uses
the contents of the MI serial port AutoNegotiation Advertisement register
for that port to advertise its capabilities to the remote device.
The remote device does the same, and the capabilities read back from
the remote device are stored in the MI serial port AutoNegotiation
Block Diagram Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-33
Draft 6/5/00
Remote End Capability register. The L80223 negotiation algorithm then
matches its capabilities to the remote device's capabilities and
determines the device configuration according to the priority resolution
algorithm defined in IEEE 802.3 Clause 28.
When the negotiation process is completed, the L80223 then configures
itself for either 10 or 100 Mbits/s mode and either Full- or Half-Duplex
modes (depending on the outcome of the negotiation process), and it
switches to either the 100BASE-TX or 10BASE-T link integrity algorithms
(depending on which mode was enabled through AutoNegotiation). Refer
to IEEE 802.3 Clause 28 for more details.
2.2.11.4 AutoNegotiation Outcome Indication
The outcome or result of the AutoNegotiation process is stored in the
10/100 Speed Detect (SPD_DET) and Duplex Detect (DPLX_DET) bits
in the MI serial port Status Output register.
2.2.11.5 AutoNegotiation Status
To monitor the status of the AutoNegotiation process, simply read the
AutoNegotiation Acknowledgement (ANEG_ACK) bit in the MI serial port
Status register. The ANEG_ACK bit is 1 when an AutoNegotiation has
been initiated and successfully completed.
2.2.11.6 AutoNegotiation Enable
To enable the AutoNegotiation algorithm, set the AutoNegotiation Enable
bit (ANEG_EN) in the MI serial port Control register, or assert the ANEG
pin. To disable the AutoNegotiation algorithm, clear the ANEG_EN bit, or
deassert the ANEG pin.
When the AutoNegotiation algorithm is enabled, the device halts all
transmissions including link pulses for 1200 to 1500 ms, enters the Link
Fail State, and restarts the negotiation process. When the
AutoNegotiation algorithm is disabled, the selection of 100 Mbits/s or
10 Mbits/s mode is determined with the SPEED bit in the MI serial port
Control register, and the selection of Half- or Full-Duplex mode
determined from the state of the DPLX bit in the MI serial port Control
register.
2-34
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
2.2.11.7 AutoNegotiation Reset
Appropriately setting the AutoNegotiation Reset (ANEG_RST) bit in the
MI serial port Control register can initiate or reset the AutoNegotiation
algorithm at any time.
2.2.12 Link Indication
Receive link detect activity can be monitored through the Link Detect bit
(LINK) in the MI serial port Status register and the Link Fail Detect bit
(LNK_FAIL) in the Status Output register. Link detect activity can also be
programmed to appear on the PLED3n or PLED0n pins. To do this,
appropriately set the Programmable LED Output Select bits in the MI
serial port Configuration 2 register as shown in Table 2.9. When either
the PLED3n or PLED0n pins are programmed to be a link detect output,
they are asserted LOW whenever the device is in the Link Pass State.
The PLED3 output is an open-drain pin with pullup resistor and can drive
an LED from VDD. The PLED0 output has both pullup and pulldown
driver transistors in addition to a weak pullup resistor, so it can drive an
LED from either VDD or GND. Both the PLED3n and PLED0n outputs can
also drive another digital input. Refer to Section 2.2.14, “LED Drivers,”
page 2-37 for a description on how to program the PLED[3:0]n pins and
their default values.
2.2.13 Collision
Collisions occur whenever transmit and receive operations occur
simultaneously while the device is in Half-Duplex mode.
2.2.13.1 100 Mbits/s
In 100 Mbits/s operation, a collision occurs and is sensed whenever there
is simultaneous transmission (packet transmission on TPO+/-) and
reception (non-idle symbols detected at the TPI+/- input). When a
collision is detected, the COL output is asserted, TP data continues to
be transmitted on the twisted-pair outputs, TP data continues to be
received on the twisted-pair inputs, and internal CRS loopback is
disabled. After a collision is in process, CRS is asserted and stays
asserted until the receive and transmit packets that caused the collision
are terminated.
Block Diagram Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-35
Draft 6/5/00
The collision function is disabled if the device is in the Full-Duplex mode,
is in the Link Fail state, or if the device is in the diagnostic loopback
mode.
2.2.13.2 10 Mbits/s
A collision in the 10 Mbits/s mode is identical to one the 100 Mbits/s
mode except:
•
The 10 Mbits/s squelch criteria determines reception
•
The RXD[3:0] outputs are all forced LOW
•
The collision signal (COL) is asserted when the SQE test is
performed
•
The collision signal (COL) is asserted when the jabber condition has
been detected.
2.2.13.3 Collision Test
To test the Controller Interface collision signal (COL), set the COLTST bit
in the MI serial port Control register. When this bit is set, TX_EN is
looped back onto COL and the TP outputs are disabled.
2.2.13.4 Collision Indication
Collisions are indicated through the COL pin, which is asserted HIGH
every time a collision occurs. The device can also be programmed to
indicate collisions on the PLED2n output.
In the MI serial port Configuration 2 register, set the LED function select
bits (LED_DEF_[1:0]) so that collision activity is indicated at the PLED2n
output. Set the PLED2_[1:0] bits in the same register to 0b11 (normal).
With these settings, a LED connected to the PLED2n pin will reflect
collision activity.
When the PLED2n pin is programmed to be a collision detect output, it
is asserted LOW for 100 ms every time a collision occurs. The PLED2n
output is open drain with a pullup resistor and can drive an LED from
VDD or can drive another digital input.
See Section 2.2.14, “LED Drivers,” page 2-37 for more details on how to
program the LED output pins to indicate various conditions.
2-36
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
2.2.14 LED Drivers
The PLED[5:2]n outputs are open-drain with a pullup resistor and can
drive LEDs tied to VDD. The PLED[1:0]n outputs have both pullup and
pulldown driver transistors with a pullup resistor, so the PLED[1:0]n
outputs can drive LEDs tied to either VDD or GND.
The PLED[5:0]n outputs can be programmed through the MI serial port
Configuration 2 register for the following functions:
•
Normal Function
•
On
•
Off
•
Blink
The PLED[5:0]n outputs are programmed with the LED output select bits
(PLED_[1:0]) and the LED Normal Function select bits (LED_DEF[1:0])
in the MI serial port Configuration register.
2.2.14.1 LED Output Select Bits
There are four sets of output select bits in MI serial port Configuration
register, one set for each LED output pin:
•
PLED3_[1:0] control the PLED3n output
•
PLED2_[1:0] control the PLED2n output
•
PLED1_[1:0] control the PLED1n output
•
PLED0_[1:0] control the PLED0n output
The PLEDx_[1:0] bits program the outputs to operate in the following
modes:
•
Normal operation (see Section 2.2.14.2, “LED Normal Function
Select Bits”)
•
Blink
•
Steady On (PLED[3:0]n pin LOW)
•
Steady Off (PLED[3:0]n pin HIGH)
Block Diagram Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-37
Draft 6/5/00
Table 2.8 shows the encoding of the output select bits.
Table 2.8
PLED_[1:0] Output Select Bit Encoding
PLED_[1]
PLED_[0]
LED State
LED Pin
1
1
Normal
LED pin reflects the functions selected with the
LED_DEF[1:0] bits
1
0
LED Blink
LED output driver continuously toggles at a rate of
100 ms on, 100 ms off
0
1
LED On
LED output driver is LOW
0
0
LED Off
LED output driver is HIGH
2.2.14.2 LED Normal Function Select Bits
When the PLED[5:0]n pins are programmed for their normal functions
(PLED_[1:0] = 0b11), the pin output states indicate four specific types of
events. The LED Normal Function select bits (LED_DEF[1:0]) in the MI
serial port Configuration register determine the states of the pins, as
indicated in Table 2.9 and Table 2.10.
Table 2.9
LED Normal Function Definition
LED_DEF[1:0]
PLED5n
PLED4n
PLED3n
PLED2n
PLED1n
PLED0n
0b11
RCV ACT
XMT ACT
LINK
COL
FDX
10/100
0b10
RCV ACT
XMT ACT
LINK
ACT
FDX
10/100
0b01
RCV ACT
XMT ACT
LINK + ACT
COL
FDX
10/100
0b001
RCV ACT
XMT ACT
LINK 100
ACT
FDX
LINK10
1. The L80223 powers up with the LED_DEF[1:0] bits set to the default value of 0b00.
2-38
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
The default Normal Functions for PLED[5:0]n are Receive Activity,
Transmit Activity, Link 100, Activity, Full Duplex, and Link 10, respectively.
Table 2.10
LED Event Definition
Symbol
Definition
RCV ACT
Receive activity occurred, stretch pulse to 100 ms
XMT ACT
Transmit activity occurred, stretch pulse to 100 ms
LINK
100 or 10 Mbits/s link detected
LINK+ACT
100 or 10 Mbits/s link detected or activity occurred, stretch
pulse to 100 ms (link detect causes LED to be on, activity
causes LED to blink)
ACT
Activity occurred, stretch pulse to 100 ms
LINK100
100 Mbit/s link detected
COL
Collision occurred, stretch pulse to 100 ms
FDX
Full-Duplex mode enabled
10/100
10 Mbits/s mode enabled (HIGH), or 100 Mbits/s mode
enabled (LOW)
LINK10
10 Mbits/s link detected
Block Diagram Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-39
Draft 6/5/00
2.3 Start of Packet
This section describes start of packet operation for both the 100 Mbits/s
and 10 Mbits/s modes.
2.3.1 100 Mbits/s
A unique Start of Stream Delimiter (SSD) indicates the start of packet for
100 Mbits/s mode. The SSD pattern consists of two /J/K/ 5B symbols
inserted at the beginning of the packet in place of the first two preamble
symbols, as defined in IEEE 802.3 Clause 24 and shown in Table 2.4
and Figure 2.2.
The 4B5B encoder generates the transmit SSD and inserts the /J/K/
symbols at the beginning of the transmit data packet in place of the first
two 5B symbols of the preamble, as shown in Figure 2.2.
The 4B5B decoder detects the receive pattern. To do this, the decoder
examines groups of 10 consecutive code bits (two 5B words) from the
descrambler. Between packets, the receiver detects the idle pattern
(5B /I/ symbols). When in the idle state, the device deasserts the CRS
and RX_DV pins.
If the receiver is in the idle state and 10 consecutive code bits from the
receiver consist of the /J/K/ symbols, the start of packet is detected, data
reception begins, and /5/5/ symbols are substituted in place of the /J/K/
symbols.
If the receiver is in the idle state and 10 consecutive code bits from the
receiver are a pattern that is neither /I/I/ nor /J/K/ symbols, but contain
at least two noncontiguous zeros, activity is detected but the start of
packet is considered to be faulty and a False Carrier Indication (also
referred to as bad SSD) is signaled to the controller interface.
When False Carrier is detected, CRS is asserted, RX_ER is asserted,
RX_DV remains deasserted, the RXD[3:0] output state is 0b1110 while
RX_ER is asserted, and the Start of Stream Error bit (SSD) is set in the
MI serial port Status Output register. Once a False Carrier Event is
detected, the idle pattern (two /I/I/ symbols) must be detected before any
new SSDs can be sensed.
2-40
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
If the receiver is in the idle state and 10 consecutive code bits from the
receiver consist of a pattern that is neither /I/I/ nor /J/K/ symbols but does
not contain at least two noncontiguous zeros, the data is ignored and the
receiver stays in the idle state.
2.3.2 10 Mbits/s
Because the idle period in 10 Mbits/s mode is defined to be when there
is no valid data on the TP inputs, the start of packet for 10 Mbits/s mode
is detected when the TP squelch circuit detects valid data. When the
start of packet is detected, CRS is asserted as described in Section
2.2.2, “Controller Interface,” page 2-9. See Section 2.2.8.4, “Squelch (10
Mbits/s),” page 2-26 for details on the squelch algorithm.
2.4 End of Packet
This section describes end of packet operation for both the 100 Mbits/s
and 10 Mbits/s modes.
2.4.1 100 Mbits/s
The End of Stream Delimiter (ESD) indicates the end of packet for 100
Mbits/s mode. The ESD pattern consists of two /T/R/ 4B5B symbols
inserted after the end of the packet, as defined in IEEE 802.3 Clause 24
and shown in Table 2.4 and Figure 2.2.
The 4B5B encoder generates the transmit ESD and inserts the /T/R/
symbols after the end of the transmit data packet, as shown in
Figure 2.2.
The 4B5B decoder detects the ESD pattern when there are groups of 10
consecutive code bits (two 5B words) from the descrambler during valid
packet reception.
If the 10 consecutive code bits from the receiver during valid packet
reception consist of the /T/R/ symbols, the end of packet is detected,
data reception is terminated, the CRS and RX_DV pins are asserted, and
/I/I/ symbols are substituted in place of the /T/R/ symbols.
If 10 consecutive code bits from the receiver during valid packet
reception do not consist of /T/R/ symbols, but instead consist of /I/I/
End of Packet
2-41
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
symbols, the packet is considered to have been terminated prematurely
and abnormally, and the end of packet condition is signalled to the
controller interface.
When the premature end of packet condition is detected, the RX_ER
signal is asserted for the nibble associated with the first /I/ symbol
detected, then the CRS and RX_DV pins are deasserted.
The device also sets End of Stream Error bit (ESD) in the MI serial port
Status Output register to indicate the premature end of packet condition.
2.4.2 10 Mbits/s
The end of packet for 10 Mbits/s mode is indicated with the SOI (Start
of Idle) pulse. The SOI pulse is a positive double wide pulse containing
a Manchester code violation inserted at the end of every packet.
The TP transmitter generates the transmit SOI pulse and inserts it at the
end of the data packet after TX_EN has been deasserted. The transmit
waveshaper shapes the transmitted SOI output pulse at the TP output to
meet the pulse template requirements specified in IEEE 802.3 Clause 14
and shown in Figure 2.8.
Figure 2.8
SOI Output Voltage Template - 10 Mbits/s
4.5 BT
0 BT
3.1 V
0.5 V/ns
0.25 BT
2.25 BT
6.0 BT
585 mV
+ 50 mV
− 50 mV
45.0 BT
585 mV sin (2 ∗ π ∗ (t/1 BT))
0 ≤ t ≤ 0.25 BT and
225 ≤ t ≤ 2.5 BT
− 3.1 V
2.5 BT
2-42
4.5 BT
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
The TP receiver senses missing data transitions in order to detect the
receive SOI pulse. Once the SOI pulse is detected, data reception is
ended and the CRS and RX_DV pins are deasserted.
2.5 Full/Half Duplex Mode
Half-Duplex mode is the CSMA/CD operation defined in IEEE 802.3. It
allows transmission or reception, but not both at the same time. FullDuplex operation is a mode that allows simultaneous transmission and
reception. Full duplex in the 10 Mbits/s mode is identical to operation in
the 100 Mbits/s mode.
The device can be forced into either the Full- or Half-Duplex mode, or
the device can use AutoNegotiation to autoselect Full/Half-Duplex
operation. When the device is placed in Full-Duplex mode:
•
The collision function is disabled, and
•
TX_EN to CRS loopback is disabled
2.5.1 Forcing Full/Half Duplex Operation
To independently force a channel into either the Full- or Half-Duplex
mode, set the Duplex Mode Select (DPLX) bit in the MI serial port
Control register, or assert the DPLX pin, assuming that AutoNegotiation
is not enabled with the ANEG_EN bit in the MI serial port Control
register.
The device automatically configures itself for Full- or Half-Duplex mode.
To do this, the device uses the AutoNegotiation algorithm to advertise
and detect Full and Half Duplex capabilities to and from a remote device.
To enable AutoNegotiation, set the AutoNegotiation Enable (ANEG_EN)
bit in the MI serial port Control register or assert the ANEG pin.
To select the advertised Full/Half Duplex capability, appropriately set the
bits in the MI serial port AutoNegotiation Advertisement register.
AutoNegotiation functionality is described in more detail in Section
2.2.11, “Link Integrity and AutoNegotiation”.
Full/Half Duplex Mode
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-43
Draft 6/5/00
2.5.2 Full/Half Duplex Indication
Full Duplex detection can be monitored through the Duplex Detect bit
(DPLX_DET) in the MI serial port Status Output register.
The device can also be programmed such that the Full-Duplex indication
appears on the PLED1n pin. To do this, appropriately set the
Programmable LED Output Select bits in the MI serial port Configuration
2 register as described in Table 2.9. When the PLED1n pin is
programmed to be a Full-Duplex detect output, it is asserted LOW when
the device is configured for Full Duplex operation. The PLED1 output has
both pullup and pulldown driver transistors and a weak pullup resistor, so
it can drive an LED from either VDD or GND and can also drive a digital
input.
2.5.3 Loopback
2.5.3.1 Internal CRS Loopback
TX_EN is internally looped back onto CRS during every transmit packet.
This internal CRS loopback is disabled during collision, in Full-Duplex
mode, in the Link Fail State, and when the Transmit Disable bit
(XMT_DIS) is set in the MI serial port Configuration 1 register. In 10
Mbits/s mode, internal CRS loopback is also disabled when jabber is
detected.
2.5.3.2 Diagnostic Loopback
Setting the loopback bit (LPBK) in the MI serial port Control register
selects the diagnostic loopback mode. When diagnostic loopback is
enabled, the TXD[3:0] data is looped back onto RXD[3:0], TX_EN is
looped back onto CRS, RX_DV operates normally, the TP receive and
transmit paths are disabled, the transmit link pulses are halted, and the
Half/Full Duplex modes do not change. Diagnostic loopback cannot be
enabled when in the FBI mode (see Section 2.2.2.2, “FBI Interface,”
page 2-12).
2-44
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
2.6 Repeater Mode
The L80223 uses the standard MII as the physical interface for MII-based
repeater cores.
The L80223 has one predefined repeater mode. To enable this mode,
assert the RPTR pin. When this repeater mode is enabled with the RPTR
pin:
•
TX_EN to CRS loopback is disabled
•
AutoNegotiation is disabled
•
100 Mbits/s operation is enabled
•
Half-Duplex operation is enabled
Note:
Enabling the repeater mode with the RPTR pin is only one
of many possible repeater modes available on the device.
Other repeater modes are available when appropriate register bits are set to enable or disable the desired functions
for a given repeater mode type.
For additional information, see Section A.14, “Repeater Applications,”
page A-22.
Repeater Mode
2-45
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
2.7 10/100 Mbits/s Selection
The device can be forced into either the 10 or 100 Mbits/s mode, or it
can use AutoNegotiation to autoselect 10 or 100 Mbits/s operation.
2.7.1 Forcing 10/100 Mbits/s Operation
To independently force each channel into either the 10 Mbits/s or 100
Mbits/s mode:
•
Clear the ANEG_EN bit in the MI serial port Control register, and
•
Appropriately set the Speed Select (SPEED) bit in the MI serial port
Control register.
Alternatively, if the ANEG pin is LOW, the SPEED pin controls the speed.
Asserting the SPEED pin HIGH forces 100 Mbits/s operation and
deasserting it LOW forces 10 Mbits/s operation.
2.7.2 Autoselecting 10/100 Mbits/s Operation
The device can automatically configure itself for 10 or 100 Mbits/s mode.
To do this, it uses the AutoNegotiation algorithm to advertise and detect
10 and 100 Mbits/s capabilities to and from a remote device. Setting the
AutoNegotiation Enable (ANEG_EN) bit in the MI serial port Control
register enables AutoNegotiation. Appropriately setting the bits in the MI
serial port AutoNegotiation Advertisement register selects the advertised
speed capability. AutoNegotiation functionality is described in more detail
in Section 2.2.11, “Link Integrity and AutoNegotiation”.
2.7.3 10/100 Mbits/s Indication
The device can be programmed such that the operation speed (10 or 100
Mbits/s) appears on the PLED0n pin. To do this, appropriately set the
Programmable LED Output Select bits in the MI serial port Configuration
2 register as described in Table 2.9. When the PLED0n pin is programmed to be speed detect output, it is asserted LOW when the device
is configured for 100 Mbit/s operation. The PLED0n output has both pullup and pulldown driver transistors and a weak pullup resistor, so it can
drive an LED from either VDD or GND and can also drive a digital input.
2-46
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
2.8 Jabber
A jabber condition occurs in 10 Mbits/s mode when the transmit packet
exceeds a predetermined length. When jabber is detected, the TP
transmit outputs are forced to the idle state, a collision is asserted, the
JAB register bit is set in the MI serial port Status register, and the JAB
bit is set in the MI serial port Status Output register.
To disable the jabber function, set the Jabber Disable bit (JAB_DIS) in
the MI serial port Configuration 2 register
The jabber function is disabled in the 100 Mbits/s mode.
2.9 Automatic Jam
This section describes automatic JAM operation for both 100 and 10
Mbits/s operation.
2.9.1 100 Mbits/s JAM
The L80223 has an automatic JAM feature that causes the device to
automatically transmit a JAM packet if receive activity is detected. If
automatic JAM is enabled, the following JAM packet is transmitted on
TPO when the RX_EN/JAMn pin is asserted LOW and receive activity is
detected on the TP inputs (expressed in 5B code words):
/J/K/5/5/5/5/5/5/5/5/5/5/5/5/5/D/H/H/H/H/H/H/H/H/T/R/
This automatic JAM feature is enabled when the RX_EN/JAM pin is
programmed to be a JAM input. To configure the RX_EN/JAMn pin as a
JAMn input, set the R/J_CFG bit in the MI serial port Configuration 2
register.
2.9.2 10 Mbits/s JAM
The JAM feature for the 10 Mbits/s mode is identical to that of the
100 Mbits/s mode except that the JAM packet transmitted on TPO
consists of the standard 62-bit preamble (alternating 1s and 0s) followed
with the SFD pattern (0b11), which is then followed with 32 bits of
alternating 1s and 0s.
Jabber
2-47
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
2.10 Reset
The device is reset when:
1. VDD is applied to the device, or
2. The reset bit (RST) is set in the MI serial port Control register, or
3. The RESETn pin is asserted (LOW).
When reset occurs because of (1) or (2), an internal power-on reset
pulse is generated that resets all internal circuits, forces the MI serial port
bits to their default values, and latches in new values for the MI address.
After the power-on reset pulse has finished, the reset bit (RST) in the MI
serial port Control register is cleared and the device is ready for normal
operation.
When reset is initiated because of (3), the same procedure occurs except
the device stays in the reset state as long as the RESETn pin is held
LOW. The RESETn pin has an internal pullup to VDD. The device is
guaranteed to be ready for normal operation 50 ms after the reset
sequence is initiated.
2.11 Powerdown
To powerdown the L80223, set the Powerdown bit (PDN) in the MI serial
port Control register. In powerdown mode, the TP outputs are in a
high-impedance state, all functions are disabled except the MI serial port,
and the power consumption is reduced to a minimum. The device is
guaranteed to be ready for normal operation 500 ms after the PDN bit is
cleared.
2-48
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
2.12 Receive Polarity Correction
In 10 Mbits/s mode, the polarity of the signal on the TP receive input is
continuously monitored. If either three consecutive link pulses or one SOI
pulse indicates incorrect polarity on the TP receive input, the polarity is
internally determined to be incorrect. In this case, the Reverse Polarity
Detect bit (RPOL) is set in the MI serial port Status Output register.
The device automatically corrects for the reverse polarity condition,
provided the autopolarity feature is not disabled. To disable autopolarity,
set the Autopolarity Disable bit (APOL_DIS) in the MI serial port
Configuration 2 register.
No polarity detection or correction is needed in the 100 Mbits/s mode.
Receive Polarity Correction
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
2-49
Draft 6/5/00
2-50
Functional Description
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Chapter 3
Signal Descriptions
This chapter describes the device signals. It contains the following
sections:
•
Section 3.1, “Media Interface Signals”
•
Section 3.2, “Controller Interface Signals (MII)”
•
Section 3.3, “Management Interface”
•
Section 3.4, “Miscellaneous Signals”
•
Section 3.5, “LEDs”
•
Section 3.6, “Power Supply”
Figure 3.1 is a logic diagram for the device.
L80223 10BASE-T/100BASE-TX/FX Ethernet PHY
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
3-1
Draft 6/5/00
Figure 3.1
Device Logic Diagram
TPI+/FXOTPI-/FXO+
Media
Interface
PLED5n
PLED4n
PLED3n/MDA3n
PLED2n/MDA2n
PLED1n/MDA1n
PLED0n/MDA0n
TPO+/FXITPO-/FXI+
REXT
SD/FXDISn
SD_THR
L80223
10/100 Mbit/s
Ethernet
Physical Layer
Device (PHY)
OSCIN
CRS
Controller
Interface
(MII)
LEDs/
MI Address
COL
RESETn
SPEED
DPLX
ANEG
RPTR
TX_CLK
TX_EN
TX_ER/TXD4
TXD[3:0]
Miscellaneous
RX_CLK
RX_EN/JAMn
RXD[3:0]
RX_DV
RX_ER/RXD4
Management
Interface
MDC
MDIO
MDINTn/MDA4n
3.1 Media Interface Signals
REXT
Transmit Current Set
I/O
An external resistor connected between the REXT pin
and GND sets the output current for the TP and FX
transmit outputs.
SD/FXDISn
I
FX Signal Detect Input/FX Interface Disable
When this pin is not tied to GND, the FX interface is
enabled and this pin becomes an ECL signal detect input.
3-2
Signal Descriptions
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
The voltage on SD_THR determines the trip point for this
ECL input.
When this pin is tied to GND, the FX interface is disabled
and the TP interface is enabled.
SD_THR
Signal Detect Input Threshold Level Set
I
The voltage on this pin determines the ECL threshold
level (trip point) for the SD input pin so that the device
can directly interface to both 3.3 V and 5 V fiber optic
transceivers. Typically, this pin is either tied to GND (for
3.3 V operation) or to an external voltage divider (for 5 V
operation).
TPO+/FXI-
Twisted-Pair Transmit Output (Positive), or
Fiber Optic Receive Input (Negative)
I/O
The TPO+/FXI- pin is shared for the twisted-pair and fiber
optic signals. It functions as the positive signal in the
twisted-pair output or the negative signal in the fiber optic
input.
TPO-/FXI+
Twisted-Pair Transmit Output (Negative), or
Fiber Optic Receive Input (Positive)
I/O
The TPO-/FXI+ pin is shared for the twisted-pair and fiber
optic signals. It functions as the negative signal in the
twisted-pair output or the positive signal in the fiber optic
input.
TPI+/FXO-
Twisted-Pair Receive Input (Positive), or
Fiber Optic Transmit Output (Negative)
I/O
The TPI+/FXO- pin is shared for the twisted-pair and fiber
optic signals. It functions as the positive signal in the
twisted-pair input or the negative signal in the fiber optic
output.
TPI-/FXO+
Twisted-Pair Receive Input (Negative), or
Fiber Optic Output (Positive)
I/O
The TPI-/FXO+ pin is shared for the twisted-pair and fiber
optic signals. It functions as the negative signal in the
twisted-pair input or the positive signal in the fiber optic
output.
Media Interface Signals
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
3-3
Draft 6/5/00
3.2 Controller Interface Signals (MII)
CRS
Carrier Sense Output
O
The CRS output is asserted HIGH when valid data is
detected on the receive TP inputs. CRS is clocked out on
the falling edge of RX_CLK.
OSCIN
Clock Oscillator Input
I
There must be either a 25 MHz crystal between this pin
and GND or a 25 MHz clock applied to this pin. TX_CLK
output is generated from this input.
RX_CLK
Receive Clock Output
O
Receive data on RXD, RX_DV, and RX_ER is clocked out
to an external controller on the falling edge of RX_CLK.
RXD[3:0]
Receive Data Output
O
RXD[3:0] contain receive nibble data from the TP input,
and they are clocked out on the falling edge of RX_CLK.
RX_DV
Receive Data Valid Output
O
RX_DV is asserted HIGH when valid decoded data is
present on the RXD outputs. RX_DV is clocked out on the
falling edge of RX_CLK.
RX_EN/JAMn Receive Enable Input
I
The function of this pin is configured through the R/J
Configuration Select bit (R/J_CFG) in the MI serial port
Configuration 1 register. When R/J_CFG is set, the pin is
configured as JAMn; when it is cleared, the pin functions
as RX_EN
RX_EN function: when RX_EN is HIGH, all of the receive
outputs (RX_CLK, RXD[3:0], RX_DV, RX_ER, COL) are
enabled. When RX_EN is LOW, the outputs are in a
high-impedance state.
JAMn function: when JAMn is HIGH, a JAM packet is
transmitted when receive activity is detected. When
JAMn is LOW, no JAM packet is transmitted.
RXER/RXD4
3-4
Receive Error Output/Fifth Receive Data Output
O
The RXER/RXD4 output is asserted HIGH when a coding
error or other specified errors are detected on the receive
Signal Descriptions
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
twisted-pair inputs. The signal is clocked out on the falling
edge of RX_CLK.
If the device is placed in the Bypass 4B5B Decoder mode
(the BYP_ENC bit is set in the MI serial port Configuration 1 register), this pin is reconfigured to be the fifth RXD
receive data output, RXD4.
TX_CLK
Transmit Clock Output
O
Transmit data from the controller on TXD, TX_EN, and
TX_ER is clocked in on the rising edge of TX_CLK and
OSCIN.
TXD[3:0]
Transmit Data Input
I
TXD[3:0] contain input nibble data to be transmitted on
the TP outputs, and they are clocked in on the rising
edge of TX_CLK and OSCIN when TX_EN is asserted.
TX_EN
Transmit Enable Input
I
TX_EN must be asserted HIGH to indicate that data on
TXD and TX_ER is valid. TX_ER is clocked in on the rising edge of TX_CLK and OSCIN.
TX_ER/TXD4 Transmit Error Input/Fifth Transmit Data Input
I
The TXER pin, when asserted, causes a special pattern
to be transmitted on the twisted-pair outputs in place of
normal data, and it is clocked in on the rising edge of
TX_CLK when TX_EN is asserted.
If the device is placed in the Bypass 4B5B Encoder mode
(the BYP_ENC bit is set in the MI serial port Configuration 1 register), this pin is reconfigured to be the fifth TXD
transmit data input, TXD4.
3.3 Management Interface
MDC
MI Clock
I
The MDC clock shifts serial data for the internal registers
into and out of the MDIO pin on its rising edge.
MDINTn/MDA4n
Management Interface Interrupt Output/
Management Interface Address Input Pullup O.D. I/O
This pin is an interrupt output and is asserted LOW
whenever there is a change in certain MI serial port
Management Interface
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
3-5
Draft 6/5/00
register bits. The pin is deasserted after all changed bits
have been read out.
During powerup or reset, this pin is high impedance and
the state of the pin is latched in as the physical device
address MDA4 for the MI serial port.
MDIO
MI Data
I/O
This bidirectional pin contains serial data for the internal
registers. The data on this pin is clocked in and out of the
device on the rising edge of MDC.
3.4 Miscellaneous Signals
ANEG
AutoNegotiation Input
This pin control AutoNegotiation operation.
ANEG Pin
Meaning
HIGH
AutoNegotiation is on.
AutoNegotiation Enable is controlled
from the ANEG_EN bit, 10/100 Mbits/s
operation is controlled from the
SPEED bit, and Half/Full Duplex
operation is controlled from the DPLX
bit.
LOW
AutoNegotiation is off.
10/100 Mbits/s operation is controlled
from the SPEED pin and Half/Full
Duplex operation is controlled from the
DPLX pin.
COL
Collision Output
O
COL is asserted HIGH when a collision between transmit
and receive data is detected.
DPLX
Full/Half Duplex Select Input
When the ANEG pin is LOW, the DPLX pin selects
Half/Full Duplex operation.
DUPLX Pin
Meaning
HIGH
Full Duplex operation
LOW
Half Duplex operation
When the ANEG pin is HIGH, the DPLX pin is ignored
and the Half/Full Duplex operation is controlled from the
3-6
I
Signal Descriptions
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
I
Draft 6/5/00
Duplex Mode Select bit (DPLX) in the MI serial port Control register or the AutoNegotiation outcome.
NC
No Connect
13 of the pins are not connected.
RESETn
Hardware Reset Input
RESETn Pin
RPTR
Pullup I
Meaning
HIGH
Normal
LOW
Device is in a reset state.
Repeater Mode Enable Input
The RPTR pin controls the device repeater operation.
RPTR Pin
SPEED
—
Meaning
HIGH
Repeater mode enabled
LOW
Normal operation
Speed Select Input
When the ANEG pin is LOW, the SPEED pin selects
10/100 Mbits/s operation.
SPEED Pin
I
I
Meaning
HIGH
100 Mbits/s operation
LOW
10 Mbits/s operation
When the ANEG pin is HIGH, this pin is ignored and the
speed is determined from the Speed Select bit (SPEED)
in the MI serial port Control register or the
AutoNegotiation outcome.
3.5 LEDs
PLED5n
Receive LED Output Pullup O.D.
O
The function of this pin is to be a Receive Activity Detect
output. The pin can drive an LED from VDD.
PLED5n
Pin
HIGH
LOW
Function
No receive activity
Receive packet occurred (held LOW for 100 ms)
LEDs
3-7
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
PLED4n
Transmit LED Output Pullup O.D.
O
The function of this pin is to be a Transmit Activity Detect
output. The pin can drive an LED from VDD.
PLED4n
Pin
HIGH
LOW
Function
No transmit activity
Transmit packet occurred (held LOW for 100 ms)
PLED3n/MDA3n
Programmable LED Output/MI Address Bit
Pullup O.D. I/O
The default function of this pin is to be a 100 Mbits/s Link
Detect output. This pin can also be programmed through
the MI serial port to indicate other events or be user controlled. This pin can drive an LED from VDD.
When programmed as a 100 Mbits/s Link Detect Output
(default):
PLED3n/MDA3n
Pin
HIGH
LOW
Function
No Link Detect
100 Mbits/s Link Detected
During powerup or reset, this pin is high-impedance and
the level on this pin is latched in as the physical device
address MDA3n for the MI serial port.
PLED2n/MDA2n
Programmable LED Output/MI Address Bit
Pullup O.D. I/O
The default function of this pin is to be an Activity Detect
output. This pin can also be programmed through the MI
serial port to indicate other events or be user controlled.
This pin can drive an LED from VDD.
When programmed as an Activity Detect Output (default):
PLED2n/MDA2n
Pin
HIGH
LOW
Function
No Activity
Transmit or receive packet
occurred (held LOW for 100 ms)
During powerup or reset, this pin is high-impedance and
the level on this pin is latched in as the physical device
address MDA2n for the MI serial port.
3-8
Signal Descriptions
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
PLED1n/MDA1n
Programmable LED Output/MI Address Bit
Pullup O.D. I/O
The default function of this pin is to be a Full Duplex
Detect output. This pin can also be programmed through
the MI serial port to indicate other events or be user
controlled. This pin can drive an LED from both VDD and
GND.
When programmed as Full Duplex Detect Output
(default):
PLED1n/MDA1n
Pin
HIGH
LOW
Function
Half-Duplex
Full-Duplex
During powerup or reset, this pin is high-impedance and
the level on this pin is latched in as the physical address
device address MDA1n for the MI serial port.
PLED0n/MDA0n
Programmable LED Output/MI Address Bit
Pullup O.D. I/O
The default function of this pin is to be a 10 Mbits/s Link
Detect output. This pin can also be programmed through
the MI serial port to indicate other events or be user
controlled. This pin can drive an LED from both VDD and
GND.
When programmed as 10 Mbits/s Link Detect Output
(default):
PLED0n/MDA0n
Pin
HIGH
LOW
Function
No Detect
10 Mbits/s Link Detected
During powerup or reset, this pin is high-impedance and
the value on this pin is latched in as the address MDA0n
for the MI serial port.
LEDs
3-9
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
3.6 Power Supply
3-10
GND
Ground
I
There are six ground pins. They must be connected to
ground (0 Volts).
VDD
Positive Supply
There are six VDD pins. They must be connected to
3.3 ± 5% Volts.
Signal Descriptions
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
I
Draft 6/5/00
Chapter 4
Registers
This chapter contains a description of the registers accessed over the
management interface (MI) serial interface. It contains the following
sections:
•
Section 4.1, “Bit Types”
•
Section 4.2, “MI Serial Port Register Summary”
•
Section 4.3, “Registers”
For further information about the operation of the MI serial interface, see
Chapter 5, Management Interface.
L80223 10BASE-T/100BASE-TX/FX Ethernet PHY
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
4-1
Draft 6/5/00
4.1 Bit Types
Because the serial port is bidirectional (capable of both read and write
operations), there are many types of bits. The following bit type
definitions are summarized in Table 4.1:
Table 4.1
•
Write bits (W) are inputs during a write cycle and are high
impedance during a read cycle
•
Read bits (R) are outputs during a read cycle and high impedance
during a write cycle
•
Read/Write bits (R/W) are actually write bits that can be read out
during a read cycle
•
R/WSC bits are R/W bits that are self-clearing after a set period of
time or after a specific event has completed
•
R/LL bits are read bits that latch themselves when they go LOW, and
they stay LOW until read. After they are read, they are reset HIGH.
•
R/LH bits are the same as R/LL bits, except that they latch HIGH.
•
R/LT are read bits that latch themselves whenever they make a
transition or change value, and they stay latched until they are read.
After R/LT bits are read, they are updated to their current value.
MI Register Bit Type Definition
Definition
Symbol
Name
W
Write
Input
No operation, Hi-Z
R
Read
No operation, Hi-Z
Output
R/W
Read/Write
Input
Output
R/WSC
Read/Write, Self-Clearing
Input
Output
(clears itself
after the operation completes)
4-2
Write Cycle
Read Cycle
Registers
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Table 4.1
MI Register Bit Type Definition (Cont.)
Definition
Symbol
Name
R/LL
Read/Latching LOW
Write Cycle
No operation, Hi-Z
Read Cycle
Output
When the bit goes LOW, it is latched.
When the bit is read, it is updated.
R/LH
Read/Latching HIGH
No operation, Hi-Z
Output
When the bit goes HIGH, it is
latched.
When the bit Is read, it is updated.
R/LT
Read/Latching on transition
No operation, Hi-Z
Output
When the bit transitions, the bit is
latched.
When the bit is read, the bit is
updated.
Bit Types
4-3
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
4.2 MI Serial Port Register Summary
The following tables summarize the device registers accessible through
the MI serial port.
Control Register (register 0) –
15
14
13
12
11
10
9
8
RST
LPBK
SPEED
ANEG_EN
PDN
MII_DIS
ANEG_RST
DPLX
7
6
0
COLTST
Reserved
Status Register (register 1) –
15
14
13
12
11
CAP_T4
CAP_TXF
CAP_TXH
CAP_TF
CAP_TH
10
8
Reserved
7
6
5
4
3
2
1
0
Reserved
CAP_SUPR
ANEG_ACK
REM_FLT
CAP_ANEG
LINK
JAB
EXREG
PHY ID #1 Register (register 2) –
15
14
13
12
11
10
9
8
OUI3
OUI4
OUI5
OUI6
OUI7
OUI8
OUI9
OUI10
7
6
5
4
3
2
1
0
OUI11
OUI12
OUI13
OUI14
OUI15
OUI16
OUI17
OUI18
PHY ID #2 Register (register 3) –
4-4
15
14
13
12
11
10
9
8
OUI19
OUI20
OUI21
OUI22
OUI23
OUI24
PART5
PART4
7
6
5
4
3
2
1
0
PART3
PART2
PART1
PART0
REV3
REV2
REV1
REV0
Registers
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
AutoNegotiation Advertisement Register (register 4) –
15
14
13
NP
ACK
RF
7
6
5
TX_HDX
10_FDX
10_HDX
12
10
Reserved
4
9
8
T4
TX_FDX
1
0
Reserved
CSMA
AutoNegotiation Remote End Capability Register (register 5) –
15
14
13
NP
ACK
RF
7
6
5
TX_HDX
10_FDX
10_HDX
12
10
Reserved
4
9
8
T4
TX_FDX
1
0
Reserved
CSMA
Configuration 1 Register (register 16) –
15
14
13
12
11
10
9
8
LINK_DIS
XMT_DIS
XMT_PDN
TXEN_CRS
BYP_ENC
BYP_SCR
UNSCR_DIS
EQLZR
7
6
5
2
1
0
CABLE
RLVL0
TLVL[3:0]
TRF[1:0]
Configuration 2 Register (register 17) –
15
14
13
12
11
10
9
8
PLED3_1
PLED3_0
PLED2_1
PLED2_0
PLED1_1
PLED1_0
PLED0_1
PLED0_0
7
6
5
4
3
2
1
0
LED_DEF1
LED_DEF0
APOL_DIS
JAB_DIS
MREG
INT_MDIO
R/J_CFG
0
Status Output Register (register 18) –
15
14
13
12
11
10
9
8
INT
LINK_FAIL
LOSS_SYNC
CWRD
SSD
ESD
RPOL
JAB
7
6
5
SPD_DET
DPLX_DET
0
Reserved
MI Serial Port Register Summary
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
4-5
Draft 6/5/00
Mask Register (register 19) –
15
MASK_INT
7
14
13
12
11
MASK_LNK_ MASK_LOSS
MASK_CWRD MASK_SSD
FAIL
_SYNC
6
5
MASK_SPD_ MASK_DPLX
DET
_DET
4
10
9
8
MASK_ESD MASK_RPOL MASK_JAB
3
0
FXLVL[1:0]
Reserved
Reserved Register (register 20) –
15
14
13
12
11
10
9
8
Reserved
7
6
5
0
Reserved
4-6
Registers
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
4.3 Registers
This section contains a description of each of the bits in each register.
4.3.1 Control Register (Register 0)
The default value for this register is 0x3000.
15
14
13
12
11
10
9
8
RST
LPBK
SPEED
ANEG_EN
PDN
MII_DIS
ANEG_RST
DPLX
7
6
0
COLTST
Reserved
RST
Reset
R/WSC 15
RST Bit
LPBK
1
Reset. The bit is bit self-clearing in less than
or equal to 200 µs after reset finishes.
0
Normal (Default)
Loopback Enable
LPBK Bit
SPEED
Meaning
Meaning
1
Loopback mode enabled
0
Normal (Default)
Speed Select
SPEED
Bit1
R/W 14
R/W 13
Meaning
1
100 Mbit/s (100BASE-TX) (default)
0
10 Mbit/s (10BASE-T)
1. The SPEED bit is effective only when AutoNegotiation is off,
and the bit can be overridden with the assertion of the
SPEED pin.
ANEG_EN
AutoNegotiation Enable
ANEG_EN
Bit1
R/W 12
Meaning
1
1 = AutoNegotiation enabled (default)
0
0 = Disabled
Registers
4-7
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
1. The ANEG_EN pin can be overridden with the
assertion of the ANEG pin.
PDN
Power Down Enable
PDN Bit
MII_DIS
R/W 11
Meaning
1
Power down
0
Normal (default)
MII Interface Disable
R/W 10
1
MII_DIS Bit
0
MII interface disable
1
Normal (default)
1. If MDA[3:0]n is not read as 0b1111 at reset
time, the MII_DIS default value is changed
to 0.
ANEG_RST
AutoNegotiation Reset
R/WSC 9
ANEG_RST Bit
DPLX
1
Restart AutoNegotiation process. The bit is
self-clearing after reset is finished
0
Normal (default)
Duplex Mode Select
R/W 8
DPLX Bit1
1
Full-duplex
0
Half-duplex (default)
1. This bit is effective only when AutoNegotiation is off, and the bit can be overridden with
the assertion of the DPLX pin.
COLTST
Collision Test Enable
R/W 7
COLTST Bit
R
4-8
1
Collision test enabled
0
Normal (default)
Reserved
R [6:0]
These bits are reserved and must be remain at the
default value of 0x00 for proper device operation.
Registers
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
4.3.2 Status Register (Register 1)
The default value of this register is 0x7809.
15
14
13
12
11
CAP_T4
CAP_TXF
CAP_TXH
CAP_TF
CAP_TH
7
6
5
4
3
2
1
0
Reserved
CAP_SUPR
ANEG_ACK
REM_FLT
CAP_ANEG
LINK
JAB
EXREG
CAP_T4
10
8
Reserved
100BASE-T4 Capable
R 15
CAP_T4
Bit
Meaning
1
0
CAP_TXF
Capable of 100BASE-T4 operation
Not capable of 100BASE-T4 Operation (default)
100BASE-TX Full Duplex Capable
R 14
CAP_TXF
Bit
Meaning
1
0
CAP_TXH
Capable of 100BASE-TX Full-Duplex (default)
Not capable of 100BASE-TX Full-Duplex
100BASE-TX Half Duplex Capable
R 13
CAP_TXH
Bit
Meaning
1
0
CAP_TF
Capable of 100BASE-TX Half-Duplex (default)
Not capable of 100BASE-TX Half-Duplex
10BASE-T Full Duplex Capable
R 12
CAP_TF
Bit
Meaning
1
0
CAP_TH
Capable of 10BASE-T Full-Duplex (default)
Not capable of 10BASE-T Full-Duplex
10BASE-T Half Duplex Capable
R 11
CAP_TH
Bit
Meaning
1
0
R
Capable of 10BASE-T Half Duplex (default)
Not capable of 10BASE-T Half Duplex
Reserved
R [10:7]
These bits are reserved and must be remain at the
default value of 0x0 for proper device operation
Registers
4-9
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
CAP_SUPR
MI Preamble Suppression Capable
R6
CAP_SUPR
Bit
Meaning
1
Capable of accepting MI frames with preamble
suppression
Not capable of accepting MI frames with
preamble suppression (default)
0
ANEG_ACK
AutoNegotiation Acknowledgment
R5
ANEG_ACK
Bit
Meaning
1
AutoNegotiation acknowledgment process
complete
AutoNegotiation not complete (default)
0
REM_FLT
Remote Fault Detect
R/LH 4
REM_FLT
Bit
Meaning
1
0
CAP_ANEG
Remote fault detect. The REM_FLT bit is set when
the Remote Fault (RF) bit is set in the
AutoNegotiation Remote End Capability register.
No remote fault (default)
AutoNegotiation Capable
R3
CAP_ANEG
Bit
Meaning
1
0
LINK
Capable of AutoNegotiation (default)
Not capable of AutoNegotiation
Link Status
R/LL 2
LINK Bit Meaning
1
0
JAB
Link detected (same as the LNK_FAIL bit inverted).
See Section 4.3.9, “Status Output Register (Register
18),” page 4-23)
Link not detected (default)
Jabber Detect
R/LH 1
JAB Bit Meaning
1
0
4-10
Jabber detected (same as the JAB bit in Section 4.3.9,
“Status Output Register (Register 18),” page 4-23)
Normal (default)
Registers
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
EXREG
Extended Register Capable
R0
EXREG
Bit
Meaning
1
0
Extended registers exist (default)
Extended registers do not exist
4.3.3 PHY ID 1 Register (Register 2)
15
14
13
12
11
10
9
8
OUI3
OUI4
OUI5
OUI6
OUI7
OUI8
OUI9
OUI10
7
6
5
4
3
2
1
0
OUI11
OUI12
OUI13
OUI14
OUI15
OUI16
OUI17
OUI18
OUI[3:18]
Company ID, Bits 3–18
R [15:0]
OUI[3:18] in this register and OUI[19:24] of the PHY ID 2
register make up the LSI OUI, whose default value is
0x00.A07D. The table below shows the default bit positions for the entire OUI field:
Bit
Default Value
OIU24
0
OIU23
1
OIU22
1
OIU21
1
OIU20
1
OIU19
1
OIU18
0
OIU17
1
OIU16
1
OIU15
0
OIU14
1
OIU13
0
OIU12
0
OIU11
0
OIU10
0
OIU9
0
Hex Value
Registers
0x7
0xD
0xA
0x0
4-11
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Bit
Default Value
OIU8
0
OIU7
0
OIU6
0
OIU5
0
OIU4
0
OUI3
0
Hex Value
0x0
0x0
4.3.4 PHY ID 2 Register (Register 3)
15
14
13
12
11
10
9
8
OUI19
OUI20
OUI21
OUI22
OUI23
OUI24
PART5
PART4
7
6
5
4
3
2
1
0
PART3
PART2
PART1
PART0
REV3
REV2
REV1
REV0
OUI[19:24]
Company ID, Bits 19–24
R [15:10]
OUI[19:24] in this register and OUI[3:18] of the PHY ID 1
register make up the LSI OUI, whose default value is
0x00.A07D. See the table in the PHY ID 1 description for
a description of the entire OUI field.
PART[5:0]
Manufacturer’s Part Number
R [9:4]
The default value for this field is 0x04. The table below
shows the default bit positions for the PART[5:0] field:
REV[3:0]
4-12
Bit
Default Value
PART[5]
0
PART[4]
0
PART[3]
0
PART[2]
1
PART[1]
0
PART[0]
0
Hex Value
Manufacturer’s Revision Number
The default value for this field is 0x0.
Registers
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
0x0
0x4
R [3:0]
Draft 6/5/00
4.3.5 AutoNegotiation Advertisement Register (Register 4)
The default value for this register is 0x01E1.
15
14
13
NP
ACK
RF
7
6
5
TX_HDX
10_FDX
10_HDX
NP
12
10
Reserved
4
9
8
T4
TX_FDX
1
0
Reserved
CSMA
Next Page Enable
NP Bit
1
0
R 15
Meaning
Next page1
No next page (default)
1. Next page is not currently supported
ACK
Acknowledge
R 14
ACK Bit Meaning
1
0
RF
Received AutoNegotiation word recognized
Not recognized (default)
Remote Fault
RF Bit
1
0
R/W 13
Meaning
AutoNegotiation remote fault detect
No remote fault detect (default)
R
Reserved
R/W[12:10]
These bits are reserved and must be remain at the
default value of 0b00 for proper device operation
T4
100BASE-T4 Capable
T4 Bit
1
0
R/W 9
Meaning
Capable of 100BASE-T4 operation
Not capable (default)
Registers
4-13
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
TX_FDX
100BASE-TX Full Duplex Capable
R/W 8
TX_FDX
Bit
Meaning
1
0
TX_HDX
Capable of 100BASE-TX Full Duplex operation
(default)
Not capable
100BASE-TX Half Duplex Capable
R/W 7
TX_HDX
Bit
Meaning
1
0
10_FDX
Capable of 100BASE-TX Half-Duplex operation
(default)
Not capable
10BASE-TX Full Duplex Capable
R/W 6
10_FDX
Bit
Meaning
1
0
10_HDX
Capable of 10BASE-T Full-Duplex operation
(default)
Not capable
10BASE-TX Half Duplex Capable
R/W 5
10_HDX
Bit
Meaning
1
0
Capable of 10BASE-T Half-Duplex operation
(default)
Not capable
R
Reserved
R/W [4:1]
These bits are reserved and must be remain at the
default value of 0x0 for proper device operation
CSMA
CSMA 802.3 Capable
CSMA Bit Meaning
1
0
Capable of 802.3 CSMA1 operation (default)
Not capable
1. Carrier-Sense, Multiple-Access
4-14
Registers
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
R/W 0
Draft 6/5/00
4.3.6 AutoNegotiation Remote End Capability Register (Register 5)
The default value for this register is 0x0000.
15
14
13
NP
ACK
RF
7
6
5
TX_HDX
10_FDX
10_HDX
NP
12
Reserved
4
9
8
T4
TX_FDX
1
0
Reserved
CSMA
Next Page Enable
NP Bit
1
0
ACK
10
R 15
Meaning
Next Page exists
No Next Page (default)
Acknowledge
R 14
ACK Bit Meaning
1
0
RF
Received AutoNegotiation Word recognized
Not Recognized (default)
Remote Fault
RF Bit
1
0
R 13
Meaning
AutoNegotiation Remote Fault detect
No Remote Fault (default)
R
Reserved
R [12:10]
These bits are reserved and must be remain at the
default value of 0b00 for proper device operation
T4
100BASE-T4 Capable
T4 Bit
1
0
R9
Meaning
Capable of 100BASE-T4 operation
Not capable (default)
Registers
4-15
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
TX_FDX
100BASE-TX Full Duplex Capable
R8
TX_FDX
Bit
Meaning
1
0
TX_HDX
Capable of 100BASE-TX Full Duplex operation
Not capable (default)
100BASE-TX Half Duplex Capable
R7
TX_HDX
Bit
Meaning
1
0
10_FDX
Capable of 100BASE-TX Half Duplex operation
Not capable (default)
10BASE-TX Full Duplex Capable
R6
10_FDX
Bit
Meaning
1
0
10_HDX
Capable of 10BASE-T Full Duplex operation
Not capable (default)
10BASE-TX Half Duplex Capable
R5
10_HDX
Bit
Meaning
1
0
Capable of 10BASE-T Half Duplex operation
Not capable (default)
R
Reserved
R [4:1]
These bits are reserved and must be remain at the
default value of 0x0 for proper device operation
CSMA
CSMA 802.3 Capable
CSMA Bit Meaning
1
0
Capable of 802.3 CSMA1 Operation
Not capable (default)
1. Carrier-Sense, Multiple-Access
4-16
Registers
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
R0
Draft 6/5/00
4.3.7 Configuration 1 Register (Register 16)
The default value for this register is 0x0022.
15
14
13
12
11
10
9
8
LNK_DIS
XMT_DIS
XMT_PDN
TXEN_CRS
BYP_ENC
BYP_SCR
UNSCR_DIS
EQLZR
7
6
5
4
3
2
1
0
CABLE
RLVL0
TLVL3
TLVL2
TLVL1
TLVL0
TRF1
TRF0
LNK_DIS
Link Disable
R/W 15
LNK_DIS
Bit
Meaning
1
0
XMT_DIS
Receive Link Detect function disable
(Force Link Pass)
Normal (default)
Device Reset
R/WSC 14
XMT_DIS
Bit
Meaning
1
0
XMT_PDN
TP transmitter disabled
Normal (default)
TP Transmit Powerdown
R/W 13
XMT_PDN
Bit
Meaning
1
0
TXEN_CRS
TP transmitter powered down
Normal (default)
TX_EN to CRS Loopback Disable
R/W 12
TXEN_CRS
Bit
Meaning
1
0
TX_EN to CRS loopback disabled
Loopback enabled (default)
Registers
4-17
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
BYP_ENC
Bypass Encoder/Decoder Select
R/W 11
BYP_ENC
Bit
Meaning
1
0
BYP_SCR
Bypass 4B/5B Encoder/Decoder
Normal (default)
Bypass Scrambler/Descrambler Select
R/W 10
BYP_SCR
Bit
Meaning
1
0
UNSCR_DIS
Bypass Scrambler/Descrambler
Normal (default)
Unscrambled Idle Reception Disabled
R/W 9
UNSCR_DIS
Bit
Meaning
1
0
EQLZR
Disable AutoNegotiation with devices that
transmit unscrambled idle on powerup and
various instances
Enable AutoNegotiation with devices that
transmit unscrambled idle on powerup and
various instances (default)
Receive Equalizer Select
R/W 8
EQLZR
Bit
Meaning
1
0
CABLE
Receive equalizer disabled (set to zero length)
Receive equalizer on (for 100 Mbits/s mode only)
(default)
Cable Type Select
R/W 7
CABLE
Bit
Meaning
1
0
RLVL0
Receive Input Level Adjust
RLVL0
Bit
1
0
4-18
STP (150 Ohm)
UTP (100 Ohm) (default)
Meaning
Receive squelch levels reduced by 4.5 dB
Normal (default)
Registers
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
R/W 6
Draft 6/5/00
TLVL[3:0]
TRF[1:0]
Transmit Output Level Adjust
R/W [5:2]
The transmit output current level is derived from an internal reference voltage and the external resistor on the
REXT pin. The transmit level can be adjusted with either
the external resistor on the REXT pin, or the four Transmit Level Adjust bits (TLVL[3:0]), as shown. The adjustment range is approximately -14% to +16% in 2% steps.
TLVL[3:0] Bits
Gain
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
(default)
0b1001
0b1010
0b1011
0b1100
0b1101
0b1110
0b1111
1.16
1.14
1.12
1.10
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
0.90
0.88
0.86
Transmit Rise/Fall Time Adjust
R/W [1:0]
TRF[1:0]
Bits
Adjustment
0b11
0b10
(default)
0b01
0b00
-0.25 ns
+0.0 ns
+.25 ns
+.50 ns
Registers
4-19
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
4.3.8 Configuration 2 Register (Register 17)
The default value for this register is 0xFF00.
15
14
13
12
11
10
9
8
PLED3_1n
PLED3_0n
PLED2_1n
PLED2_0n
PLED1_1n
PLED1_0n
PLED0_1n
PLED0_0n
4
3
2
1
0
JAB_DIS
MREG
7
LED_DEF1
LED_DEF0
APOL_DIS
Reserved
PLED3_[1:0]n Programmable LED 3 Output Select
R/W [15:14]
PLED3_1n PLED3_0n Meaning
1
1
1
0
0
1
0
0
Normal (PLED3n pin state is determined
from the LED_DEF[1:0] bits (default is
LINK100).
0b11 is the default for these bits
LED tied to PLED3n blinks (toggles 100
ms LOW, then 100 ms HIGH)
LED tied to PLED3n ON steady
(PLED3n output LOW)
LED tied to PLED3n OFF steady
(PLED3n output HIGH)
PLED2_[1:0]n Programmable LED 2 Output Select
R/W [13:12]
PLED2_1n PLED2_0n Meaning
4-20
1
1
1
0
0
1
0
0
Normal (PLED2n pin state is determined
from the LED_DEF[1:0] bits (default is
Activity).
0b11 is the default for these bits
LED tied to PLED2n blinks (toggles 100
ms LOW, then 100 ms HIGH)
LED tied to PLED2n ON steady
(PLED2n output LOW)
LED tied to PLED2n OFF steady
(PLED2n output HIGH)
Registers
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
PLED1_[1:0]n Programmable LED 1 Output Select
R/W [11:10]
PLED1_1n PLED1_0n Meaning
1
1
1
0
0
1
0
0
Normal (PLED1n pin state is determined
from the LED_DEF[1:0] bits (default is
Full-Duplex).
0b11 is the default for these bits
LED tied to PLED1n blinks (toggles 100
ms LOW, then 100 ms HIGH)
LED tied to PLED1n ON steady
(PLED1n output LOW)
LED tied to PLED1n OFF steady
(PLED1n output HIGH)
PLED0_[1:0]n Programmable LED 0 Output Select
R/W [9:8]
PLED0_1n PLED0_0n Meaning
1
1
1
0
0
1
0
0
Normal (PLED0n pin state is determined
from the LED_DEF[1:0] bits (default is
Link 10).
b11 is the default for these bits
LED tied to PLED0n blinks (toggles 100
ms LOW, then 100 ms HIGH)
LED tied to PLED0n ON steady
(PLED0n output LOW)
LED tied to PLED0n OFF steady
(PLED0n output HIGH)
LED_DEF_[1:0]
LED Normal Function Select
R/W [7:6]
See Table 2.8 on page 2-32 for these bit definitions.
APOL_DIS
Autopolarity Disable
R5
APOL_DIS
Bit
Meaning
1
0
JAB_DIS
Autopolarity correction disabled
Normal (default)
Jabber Disable
R4
JAB_DIS Bit Meaning
1
0
Jabber disabled
Jabber enabled (default)
Registers
4-21
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
MREG
Multiple Register Access Enable
MREG Bit
1
0
INT_MDIO
R3
Meaning
Multiple register access enabled
No multiple register access (default)
Interrupt Scheme Select
R/W 2
INT_MDIO
Bit
Meaning
1
0
R/J_CFG
R/J Configuration Select
R/J_CFG
Bit
1
0
R
4-22
Interrupt signaled with MDIO pulse during idle
Interrupt not signaled on MDIO (default)
R/W 1
Meaning
RX_EN/JAMn pin is configured to be JAMn
RX_EN/JAMn pin is configured to be RX_EN
(default)
Reserved
R/W 0
This bit is reserved and must be remain at the default
value of 0x0 for proper device operation.
Registers
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
4.3.9 Status Output Register (Register 18)
The default value for this register is 0x0080.
15
INT
8
LNK_FAIL
LOSS_SYNC
7
SPD_DET
CWRD
SSD
ESD
RPOL
5
0
DPLX_DET
INT
Reserved
Interrupt Detect
INT Bit
1
0
LNK_FAIL
JAB
R 15
Meaning
Interrupt bit(s) have changed since last read
operation
No change (default)
Link Fail Detect
R/LT 14
LNK_FAIL Bit Meaning
1
0
Link not detected
Normal (default)
LOSS_SYNC Descrambler Loss of Synchronization Detect R/LT 13
LOSS_SYNC
Bit
Meaning
1
0
CWRD
Codeword Error
CWRD Bit
1
0
SSD
Descrambler has lost sync
Normal (default)
Meaning
Invalid 4B5B code detected on receive data
Normal (default)
Start of Stream Error
SSD Bit
R/LT 12
R/LT 11
Meaning
1
No Start of Stream Delimiter detected on
receive data
0
Normal (default)
Registers
4-23
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
ESD
End of Stream Error
ESD Bit
1
0
RPOL
R/LT 10
Meaning
No End of Stream Delimiter detected on receive
data
Normal (default)
Reversed Polarity Detect
R/LT 9
RPOL Bit Meaning
1
0
JAB
Reversed Polarity detect
Normal (default)
Jabber Detect
R/LT 8
JAB Bit Meaning
1
0
SPD_DET
Jabber detected
Normal (default)
100/10 Speed Detect
R/LT 7
SPD_DET Bit Meaning
1
0
DPLX_DET
Device in 100BASE-TX Mode (default)
Device in 10BASE-T Mode
Duplex Detect
R/LT 6
DPLX_DET
Bit
Meaning
1
0
R
4-24
Device in Full Duplex mode
Device in Half Duplex mode (default)
Reserved
R [5:0]
These bits are reserved and must be remain at the
default value of 0x0 for proper device operation.
Registers
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
4.3.10 Interrupt Mask Register (Register 19)
The default value for this register is 0xFFC0.
15
MASK_INT
14
13
12
11
10
MASK_LNK_ MASK_LOSS
MASK_CWRD MASK_SSD
FAIL
_SYNC
7
6
5
4
MASK_
SPD_DET
MASK_
DPLX_DET
FXLVL1
FXLVL0
9
8
MASK_ESD MASK_RPOL MASK_JAB
3
0
Reserved
MASK_ INT
R/W 15
Interrupt Mask - Interrupt Detect
MASK_INT Bit Meaning
1
Mask interrupt when INT bit = 1 in register 18
(default)
No interrupt mask
0
MASK_ LNK_FAIL
Interrupt Mask - Link Fail Detect
R/W 14
MASK_LNK_FAIL
Bit
Meaning
1
Mask interrupt for LNK_FAIL bit in register
18 (default)
No mask
0
MASK_ LOSS_SYNC
R/W 13
Interrupt Mask - Descrambler Loss of Sync Detect
MASK_LOSS_SYNC
Bit
Meaning
1
0
Mask interrupt for LOSS_SYNC bit in
register 18 (default)
No mask
MASK_ CWRD
Interrupt Mask - Codeword Error
R/W 12
MASK_CWRD
Bit
Meaning
1
0
Mask Interrupt for CWRD bit in register 18
(default)
No mask
Registers
4-25
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
MASK_ SSD Interrupt Mask - Start of Stream Error
R/W 11
MASK_SSD
Bit
Meaning
1
Mask Interrupt for SSD bit in register 18
(default)
No mask
0
MASK_ ESD Interrupt Mask - End of Stream Error
R/W 10
MASK_ESD
Bit
Meaning
1
Mask Interrupt For ESD bit in register 18
(default)
No mask
0
MASK_ RPOL
R/W 9
Interrupt Mask - Reverse Polarity Detect
MASK_RPOL
Bit
Meaning
1
Mask interrupt for RPOL bit in register 18
(default)
No mask
0
MASK_ JAB
R/W 8
Interrupt Mask - Jabber Detect
MASK_JAB Bit Meaning
1
0
Mask interrupt for JAB bit in register 18
(default)
No mask
MASK_ SPD_DET
Interrupt Mask - 10/100 Speed Detect
R/W 7
MASK_SPD_DET
Bit
Meaning
1
0
4-26
Mask Interrupt for SPD_DET bit in register
18 (default)
No mask
Registers
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
MASK_ DPLX_DET
Interrupt Mask - 10/100 Duplex Detect
R/W 6
MASK_DPLX_DET
Bit
Meaning
1
Mask Interrupt for DPLX_DET bit in
register 18 (default)
No mask
0
FXLVL[1:0]
Fiber Transmit Level Adjust
R/W [5:4]
FXLVL[1:0]
Bits
Adjustment
0b11
0b10
0b01
0b00
(default)
R
1.30
1.15
0.85
1.00
Reserved
R/W [3:0]
These bits are reserved and must be remain at the
default value of 0 for proper device operation
Registers
4-27
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
4.3.11 Reserved Register (Register 20)
The default value for this register is 0x0000.
15
8
Reserved
7
0
Reserved
R
4-28
Reserved
R/W [15:0]
These bits are reserved and must be remain at the
default value of 0 for proper device operation.
Registers
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Chapter 5
Management Interface
This chapter describes the Management Interface, over which the
internal device registers are accessed. It contains the following sections:
•
Section 5.1, “Signal Description”
•
Section 5.2, “General Operation”
•
Section 5.3, “Multiple Register Access”
•
Section 5.4, “Frame Structure”
•
Section 5.5, “Register Structure”
•
Section 5.6, “Interrupts”
The Management Interface, referred to as the MI serial port, is an eightpin bidirectional link through which the internal device registers are
accessed. The internal register bits control the configuration and
capabilities of the device, and reflect device status.
The MI serial port provides access to 11 internal registers and meets all
IEEE 802.3 specifications for the Management Interface.
L80223 10BASE-T/100BASE-TX/FX Ethernet PHY
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
5-1
Draft 6/5/00
5.1 Signal Description
The MI serial port has eight pins:
•
MDC: serial shift clock input pin
•
MDIO: bidirectional data pin
•
MDINTn: interrupt pin
•
MDA[4:0]n: physical address pins
The MDA[4:0]n pins configure the device for a particular address, from
0b0000 to 0b1111, such that 16 devices can exist in the same address
domain, and each be addressed separately over the MI serial port. When
an MI read or write cycle occurs, the device compares the internally
inverted and latched state of the MDA[4:0]n pins to the PHYAD[4:0]
address bits of the MI frame. If the states compare, the device knows it
is being addressed.
The MDA[4:0]n inputs share the same pins as the MDINTn and
PLED[3:0]n outputs, respectively. At powerup or reset, the PLED[3:0]n
and MDINTn output drivers are 3-stated for an interval called the
power-on reset time. During the power-on reset interval, the value on
these pins is latched into the device, inverted, and used as the MI serial
port physical device addresses.
5-2
Management Interface
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
5.2 General Operation
The MI serial port is idle when at least 32 continuous ones are detected
on the bi-directional MDIO data pin and remains idle as long as
continuous ones are detected. During idle, the MDIO output driver is in
the high-impedance state. When the MI serial port is in the idle state, a
0b01 pattern on the MDIO pin initiates a serial shift cycle. Control and
address bits are clocked into MDIO on the next 14 rising edges of MDC
(the MDIO output driver is still in a high-impedance state). If the multiple
register access mode is not enabled, data is either shifted in or out on
MDIO on the next 16 rising edges of MDC, depending on whether a write
or read cycle was selected with the READ and WRITE operation bits.
After the 32 MDC cycles have been completed:
•
One complete register has been read or written
•
The serial shift process is halted
•
Data is latched into the device
•
The MDIO output driver goes into a high-impedance state.
Another serial shift cycle cannot be initiated until the idle condition is
detected again (at least 32 continuous ones). Figure 5.1 shows a timing
diagram for a MI serial port cycle.
General Operation
5-3
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
5-4
Figure 5.1
MI Serial Port Frame Timing Diagram
WRITE Cycle
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
1
P4
P3
P2
P1
P0
R4
R3
R2
R1
R0
1
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
D8
D7
D6
D5
D4
D3
D2
D1 D0
28
29
30
MDIO
0
ST
OP
PHYAD
REGAD
D15 D14 D13 D12 D11 D10 D9
TA
DATA
WRITE Bits
PHY clocks in data on rising edges of MDC with ts = 10 ns minimum and th = 10 ns minimum
READ Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
1
0
P4
P3
P2
P1
P0
R4
R3
R2
R1
R0
Z
15
16
17
18
19
20
21
22
23
24
25
26
27
MDC
MDIO
0
ST
OP
PHYAD
REGAD
WRITE Bits
PHY clocks in data on rising edges of MDC with
ts = 10 ns minimum, and th = 10 ns minimum
0 D15 D14 D13 D12 D11 D10 D9
TA
D8
D7
D6
D5
D4
D3
D2
D1
DATA
READ Bits
PHY clocks out data on rising edges of MDC with
td = 20 ns maximum
Note: ST = start bits, OP = operation bits (read or write), PHAD = PHY address, REGAD = register address, TA = turnaround bits
For more detailed timing information on th, th, and th, see Chapter 6, “Specifications.”
D0
31
Draft 6/5/00
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Management Interface
Rev. letter
1
MDC
Draft 6/5/00
5.3 Multiple Register Access
Multiple registers can be accessed on a single MI serial port access
cycle with the multiple register access feature. Setting the Multiple
Register Access Enable (MREG) bit in the MI serial port Configuration 2
Register enables the multiple register access feature.
When the PHYAD[4:0] bits in the MI frame match MDA[4:0]n pins on the
device and the REGAD[4:0] bits are set to 0b11111 during the first 16
clock cycles, all 11 registers are accessed on the 176 rising edges of
MDC (11 registers x 16 bits per register) that occur after the first 16 MDC
clock cycles of the MI serial port access cycle. There is no actual register
residing at 0b1111, but this condition triggers the access of multiple
registers.
The registers (0, 1, 2, 3, 4, 5, 16, 17, 18, 19, and 20) are accessed in
numerical order from 0 to 20. After all 192 MDC clocks (16 + 176) have
been completed:
•
All the registers have been read or written
•
The serial shift process is halted
•
Data is latched into the device
•
MDIO goes into a high-impedance state.
Another serial shift cycle cannot be initiated until the idle condition (at
least 32 continuous ones) is detected.
Multiple Register Access
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
5-5
Draft 6/5/00
5.4 Frame Structure
The structure of the serial port frame is shown in Figure 5.2 and a timing
diagram is shown in Figure 5.1. Each serial port access cycle consists
of 32 bits, exclusive of idle. The first 16 bits of the serial port cycle are
always write bits and are used for control and addressing. The last 16
bits are data that is written to or read from a data register.
The first two bits in Figure 5.2 and Figure 5.1 are start bits (ST[1:0]) and
must be written as a 0b01 for the serial port cycle to continue. The next
two bits are the READ and WRITE bits, which determine whether a
registers is being read or written. The next five bits are the PHY device
address bits (PHYAD[4:0]), and they must match the inverted values
latched from the MDA[4:0]n pins during the power on reset time for
access to continue.
The next five bits are register address select (REGAD[4:0]) bits, which
select one of the 11 registers for access. The next two bits are
turnaround (TA) bits, which are not actual register bits but provide the
device extra time to switch the MDIO pin function from a write pin to a
read pin, if necessary. The final 16 bits of the MI serial port cycle are
written to or read from the specific data register that the register address
bits (REGAD[4:0]) designate. Figure 5.2 shows the MI frame structure.
Figure 5.2
IDLE
5-6
MI Serial Frame Structure
ST[1:0]
READ
WRITE
PHYAD[4:0]
REGAD[4:0]
TA[1:0]
D[15:0]
IDLE
Idle Pattern
W
These bits are an idle pattern. The device does not
initiate an MI cycle until it detects an idle pattern of at
least 32 consecutive ones.
ST[1:0]
Start Bits
W
When ST[1:0] = 01, a MI serial port access cycle starts.
READ
Read Select
When the READ bit is 1, it designates a read cycle.
WRITE
Write Select
W
When the WRITE bit is 1, it designates a write cycle.
Management Interface
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
W
Draft 6/5/00
PHYAD[4:0]
Physical Device Address
W
When the PHYAD[4:0] bits match the inverted latched
value of the MDA[3:0]n pins, the device’s MI serial port is
selected for operation.
REGAD[4:0]
Register Address
W
The REGAD[4:0] bits determine the specific register to
access.
TA[1:0]
Turnaround Time
R/W
These bits provide some turnaround time for MDIO to
allow it to switch to a write input or read output, as
needed. When READ = 1, TA[1:0] = 0bZ0; when
WRITE = 1, TA[1:0] = 0b10.
D[15:0]
Data
R or W
These 16 bits contain data to or from one of the registers
selected with the register address bits REGAD[4:0].
Frame Structure
5-7
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
5.5 Register Structure
The device has 11 16-bit registers. A map of the registers is shown in
Section 4.2, “MI Serial Port Register Summary”. See Chapter 4,
Registers for a complete description of each register.
The 11 registers consist of six registers that are defined by IEEE 802.3
specifications (registers 0 to 5) and five registers that are unique to the
device (registers 16 through 20). Table 5.1 gives a summary of the
functions of each register.
Table 5.1
Name
Description
0
Control Register
Stores various configuration bits
1
Status Register
Contains device capability and status output bits
2
PHY ID 1
Contain an identification code unique to the device
3
PHY ID 2
4
AutoNegotiation
Advertisement
Contains bits that control the operation of the AutoNegotiation
algorithm
5
AutoNegotiation
Remote End
Capability
Contains bits that reflect the AutoNegotiation capabilities of the
link partner’s PHY
16
Configuration 1
Stores various configuration bits
17
Configuration 2
Stores various configuration bits
18
Channel Status Output Contains status
19
Mask
Contains interrupt mask bits
20
Reserved
Reserved for factory use
Register
5-8
MI Serial Port Register Summary
Management Interface
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
5.6 Interrupts
The device has hardware and software interrupt capability. Certain output
status bits (also referred to as interrupt bits) in the serial port trigger
interrupts.
The R/LT interrupt bits (bits [14:6]) in the Channel Status Output Register
cause an interrupt when they transition provided they are not masked
with the mask bits in the Interrupt Mask register. These interrupt bits stay
latched until read. When all interrupt bits are read, the interrupt indication
is removed and the interrupt bits that caused the interrupt are updated
to their current value.
Setting the appropriate mask register bits in the Interrupt Mask Register
individually can mask and remove an interrupt bit as a source of
interrupt.
Interrupt indication is done in three ways:
•
MDINTn pin: The MDINTn pin is an active-LOW interrupt output
indication.
•
INT bit: The INT bit in the Status Output Register, when set, indicates
that one or more interrupt bits have changed since the register was
last read.
•
Interrupt pulse on MDIO: When the Interrupt Scheme Select bit
(INT_MDIO) is set in the Configuration 2 register, an interrupt is
indicated with a low-going pulse on MDIO when MDC is high and the
serial port is in the idle state, as shown in the timing diagram in
Figure 5.3. After the interrupt pulse, MDIO goes back to the highimpedance state. If the interrupt occurs while the serial port is being
accessed, the MDIO interrupt pulse is delayed until one clock bit
after the serial port access cycle has ended, as shown in Figure 5.3
Interrupts
5-9
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Figure 5.3
MDIO Interrupt Pulse
INTERNAL
INTERRUPT
MDC
MDIO
MDIO HI-Z
Pulled High Externally
Interrupt
Pulse
MDIO HI-Z
Pulled High Externally
Interrupt
Pulse
MDIO HI-Z
Pulled High Externally
INTERNAL
INTERRUPT
MDC
MDIO
B1
B0
Last Two Bits
of Read Cycle
5-10
MDIO HI-Z
Pulled High Externally
Management Interface
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Chapter 6
Specifications
This chapter contains the complete electrical, timing, and mechanical
specifications for the device. It contains the following sections:
•
Section 6.1, “Absolute Maximum Ratings”
•
Section 6.2, “Electrical Characteristics”
•
Section 6.2.2, “FX Characteristics, Transmit”
•
Section 6.3, “AC Electrical Characteristics”
•
Section 6.4, “LED Driver Timing Characteristics”
•
Section 6.5, “Pinouts and Package Drawings”
•
Section 6.6, “Mechanical Drawing”
L80223 10BASE-T/100BASE-TX/FX Ethernet PHY
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-1
Draft 6/5/00
6.1 Absolute Maximum Ratings
Table 6.1 shows the device absolute maximum ratings. These are limits
which, if exceeded, could cause permanent damage to the device or
affect device reliability. All voltages are specified with respect to GND
unless otherwise specified.
Table 6.1
Absolute Maximum Ratings
Parameter
Range
Units
VDD Supply Voltage
−0.3V to +4.0V
V
All Inputs and Outputs
−0.3V to 5.5V
V
Package Power Dissipation
2.0 @ 70˚C
W
Storage Temperature
−65 to +150
˚C
−10 to +80 ˚C
˚C
Lead Temperature (soldering, 10 sec)
260
˚C
Body Temperature (soldering, 30 sec)
220
˚C
Temperature Under Bias
6-2
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
6.2 Electrical Characteristics
Table 6.2 lists the device DC electrical characteristics. Unless otherwise
noted, all test conditions are as follows:
TA = 0 to + 70 ˚C
VDD = 3.3 V 5%
Clock = 25 MHz + 0.01%
REXT = 10 KΩ 1%, no load
Table 6.2
DC Characteristics
Limit
Sym
Parameter
VIL
Input Low Voltage
VIH
IIL
Min
Input High Voltage
Typ
Max
Unit
0.8
Volt
All except OSCIN, MDA[4:0]n
SD/FXDISn, SD_THR
VDD −1.0
Volt
MDA[4:0]n
1.5
Volt
OSCIN
0.45
Volt
SD/FXDISn (for FX disable),
SD_THR (for 3.3V/5V select)
2
Volt
All except OSCIN, MDAn[4:0],
SD/FXDISn, SD_THR
VDD − 0.5
Volt
MDA[4:0]n
2.3
Volt
OSCIN
0.85
Volt
SD/FXDISn (for FX disable),
SD_THR (for 3.3 V/5 V select)
−1
uA
VIN = GND All except OSCIN,
MDA[4:0]n, RESETn
−4
−25
uA
VIN = GND.
MDA[4:0]n
−12
−120
uA
VIN = GND.
RESETn
−150
uA
VIN = GND.
OSCIN
Input Low Current
Conditions
Electrical Characteristics
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-3
Draft 6/5/00
Table 6.2
DC Characteristics (Cont.)
Limit
Sym
Parameter
Min
IIH
Input High Current
Typ
Max
Unit
1
uA
VIN = VDD. All except OSCIN,
RPTR
120
uA
VIN = VDD. RPTR
150
uA
VIN = VDD. OSCIN
0.4
Volt
IOL = −4 mA.
All except PLED[5:0]n
1
Volt
IOL = −10 mA. PLED[5:0]n
VDD − 1.0
Volt
IOH = 4 mA. All Except
PLED[5:0]n, MDINTn
2.4
Volt
IOH = 4 uA.
PLED[5:2n], MDINTn
VDD − 1.0
Volt
IOH = 10 mA. PLED[1:0]n
12
VOL
VOH
Output Low
Voltage
Output High
Voltage
CIN
Input Capacitance
IDD
VDD Supply
Current
IGND
IPDN
GND Supply
Current
Powerdown
Supply Current
5
Conditions
pF
120
mA
Transmitting, 100 Mbits/s
140
mA
Transmitting, 10 Mbits/s
190
mA
Transmitting, 100 Mbits/s1
220
mA
Transmitting, 10 Mbits/s1
200
µA
Powerdown, either IDD or IGND
1. IGND includes current flowing into GND from the external resistors and transformer on TPO/FXO
as shown in Figure A.1
6-4
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
6.2.1 Twisted-Pair DC Characteristics
Unless otherwise noted, all test conditions for TP transmit and receive
operations are as follows:
TA = 0 to + 70 ˚C
VDD = 3.3 V 5%
Clock = 25 MHz 0.01%
REXT = 10 KΩ 1%,no load
TPO+/- loading is as shown in Figure A.1 or equivalent
62.5/10 MHz Square Wave on TP+/- inputs in 100/10 Mbits/s modes
Table 6.3 shows the twisted-pair characteristics for transmit operation.
Table 6.3
Twisted Pair Characteristics (Transmit )
Limit
Sym
TOV
Parameter
TP Differential Output
Voltage
Min
Typ
Max
Unit
Conditions
0.950
1.000
1.050
V pk
100 Mbits/s, UTP
Mode, 100 Ohm Load
1.165
1.225
1.285
V pk
100 Mbits/s, STP
Mode, 150 Ohm Load
2.2
2.5
2.8
V pk
10 Mbits/s, UTP Mode,
100 Ohm Load
2.694
3.062
3.429
V pk
10 Mbits/s, STP Mode,
150 Ohm Load
TOVS
TP Differential Output
Voltage Symmetry
98
102
%
100 Mbits/s, ratio of
positive and negative
amplitude peaks on
TPO±
TORF
TP Differential Output
Rise and Fall Time
3.0
5.0
nS
100 Mbits/s
TRF[1:0] = 0b10
TORFS
TP Differential Output
Rise and Fall Time
Symmetry
± 0.5
nS
100 Mbits/s, difference
between rise and fall
times on TPO±
TODC
TP Differential Output
Duty Cycle Distortion
± 0.25
nS
100 Mbits/s, output
data = 0101... NRZ
pattern unscrambled,
measure at 50% Points
Electrical Characteristics
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-5
Draft 6/5/00
Table 6.3
Twisted Pair Characteristics (Transmit (Cont.) )
Limit
Sym
Parameter
Min
Typ
Max
Unit
Conditions
TOJ
TP Differential Output
Jitter
± 1.4
nS
100 Mbits/s, output
data = scrambled /H/
TOO
TP Differential Output
Overshoot
5.0
%
100 Mbits/s
TOVT
TP Differential Output
Voltage Template
See Figure 2.4
10 Mbits/s
TSOI
TP Differential Output
SOI Voltage Template
See Figure 2.8
10 Mbits/s
TLPT
TP Differential Output
Link Pulse Voltage
Template
See Figure 2.6
10 Mbits/s, NLP and
FLP
TOIV
TP Differential Output
Idle Voltage
TOIA
TP Output Current
TOIR
6-6
TP Output Current
Adjustment Range
± 50
mV
10 Mbits/s. Measured
on secondary side of
transformer in
Figure A.1.
38
40
42
mA pk
100 Mbits/s, UTP with
TLVL[3:0] = 0b1000
31.06
32.66
34.26
mA pk
100 Mbits/s, STP with
TLVL[3:0] = 0b1000
88
100
112
mA pk
10 Mbits/s, UTP with
TLVL[3:0] = 0b1000
71.86
81.64
91.44
mA pk
10 Mbits/s, STP with
TLVL[3:0] = 0b1000
0.80
1.2
VDD = 3.3 V, adjustable
with REXT, relative to
TOIA with REXT = 10K
0.86
1.16
VDD = 3.3 V,
Adjustable with
TLVL[3:0] See Section
A.4, “TP Transmit
Output Current Set,”
page A-7, relative to
value at TLVL[3:0] =
0b1000
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Table 6.3
Twisted Pair Characteristics (Transmit (Cont.) )
Limit
Sym
Parameter
TORA
TP Output Current TLVL
Step Accuracy
TOR
TP Output Resistance
TOC
TP Output Capacitance
Min
Typ
Max
Unit
Conditions
± 50
%
Relative to ideal values
in Table 2.6. Table 2.6
values relative to output
with TLVL[3:0] =
0b1000.
10 K
Ohm
15
pF
Electrical Characteristics
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-7
Draft 6/5/00
Table 6.4 shows the twisted-pair characteristics for receive operation.
Table 6.4
Twisted Pair Characteristics (Receive )
Limit
Sym
RST
RUT
Parameter
Min
TP Input Squelch Threshold
TP Input Unsquelch
Threshold
ROCV
TP Input Open Circuit
Voltage
RCMR
TP Input Common Mode
Voltage Range
RDR
TP Input Differential Voltage
Range
RIR
TP Input Resistance
RIC
TP Input Capacitance
6-8
Typ
Max
Unit
Conditions
166
500
mV pk
100 Mbits/s, RLVL0 = 0
310
540
mV pk
10 Mbits/s, RLVL0 = 0
60
200
mV pk
100 Mbits/s, RLVL0 = 1
186
324
mVpk
10 Mbits/s, RLVL0 = 1
100
300
mV pk
100 Mbits/s, RLVL0 = 0
186
324
mV pk
10 Mbits/s, RLVL0 = 0
20
90
mV pk
100 Mbits/s, RLVL0 = 1
112
194
mVpk
10 Mbits/s, RLVL0 = 1
VDD − 2.4
± 0.2
Volt
Voltage on either TPI+
or TPI− with respect to
GND.
ROCV ±
0.25
Volt
Voltage on TPI with
respect to GND.
VDD
5K
Volt
Ohm
10
pF
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
6.2.2 FX Characteristics, Transmit
Unless otherwise noted, all test conditions for FX transmit and receive
operations are as follows:
•
TA = 0 to +70 C
•
VDD=3.3 V ± 5%
•
25 MHz ± 0.01%
•
REXT=10 K ± 1%, no load
•
FXO± Loading as shown in Figure A.1 or Equivalent
•
125 MHz Square Wave on FXI+/- and SD Inputs
Table 6.5 shows the FX characteristics for transmit operation.
Table 6.5
FX Characteristics, Transmit
Limit
Sym
Parameter
Min
Typ
Max
Unit
Conditions
FOVH
FXO Output
Voltage, High
VDD 1.020
VDD 0.880
V
Single-ended, measure
FXO relative to GND
FOVL
FXO Output
Voltage, Low
VDD 1.810
VDD 1.620
V
Single-ended, measure
FXO relative to GND
FOIA
FXO Output
Current
12
20
mA pk
FOIR
FXO Output
Current
Adjustment
Range
0.85
1.15
VDD = 3.3 V, adjustable
with REXT, relative to FOIA
with REXT = 10 K
0.85
1.30
VDD = 3.3 V, adjustable
With FLVL[1:0], relative To
value at FLVL[1:0] = 0b10
FORA
FXO Output
Current TLVL
Step Accuracy
0.50
%
FORF
FXO
Differential
Output Rise and
Fall Time
1.3
ns
Relative to ideal values In
Table 2.9
Electrical Characteristics
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-9
Draft 6/5/00
Table 6.5
FX Characteristics, Transmit
Limit
Sym
Parameter
Min
Typ
Max
Unit
Conditions
FORFS
FXO
Differential
Output and Fall
Time Symmetry
0.5
ns
Difference between rise nd
fall times on FXO+
FODC
FXO
Differential
Output Duty
Cycle Distortion
0.25
ns
Output Data = 0101...
pattern measure at 50%
points
FOJ
FXO
Differential
Output Jitter
1.3
ns
Output data = /H/
FOR
FXO Output
Resistance
10 K
Ohm
FOC
FXO Output
Capacitance
10
pF
6-10
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Table 6.6 shows the FX characteristics for receive operation.
Table 6.6
FX Characteristics, Receive
Limit
Sym
Parameter
Min
FDIV
FXI
Differential
Input Voltage
0.150
FCMR
FXI Input
Common Mode
Voltage Range
1.35
FSDIH
SD/FXDISn
Input High
Voltage
FSDIL
Typ
Max
Unit
Conditions
V pk
VDD 0.80
V
Voltage on Either FXI+ or FXIwith respect to GND
VTRIP 50mV
V
When SD/FXDISn is used as a
Signal Detect input, not as the FX
disable input.
VTRIP = (VDD -1.3V) 10%.
SD/FXDISn
Input Low
Voltage
VTRIP 50 mV
V
When SD/FXDISn is used as a
Signal Detect input, not as the FX
disable input.
VTRIP = (VDD - 1.3V) 10%
FSDTHR
SD_THR Input
Voltage
VDD 1.3V 2%
V
When interfacing to 5 V fiber
transceivers. When interfacing to
3.3 V fiber transceivers, SD_THR
is tied to GND.
FIR
FXI ,
SD/FXDISn
Input
Resistance
5K
FIC
FX
SD/FXDISn
Input
Capacitance
VDD 1.3V
VDD 1.3V +
2%
ohm
10
pF
Electrical Characteristics
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-11
Draft 6/5/00
6.3 AC Electrical Characteristics
Unless otherwise noted, all test conditions are as shown in Table 6.7.
Table 6.7
Test Conditions
Test Condition
Parameter
Value
Temperature
TA
0 to +70 C
Voltage
VDD
3.3V 5%
Clock Frequency
25 MHz 0.01%
External Resistor
REXT
10K 1%, no load
Input Conditions
(all inputs)
tr, tf
≤ 10 ns, 20-80% points
Same as Figure A.1 or
equivalent
10 pF
Output Loading
TPO
Open-drain outputs
1K pullup, 50 pF
All other digital
outputs
25 pF
Measurement Points
TPO ,TPI
All other inputs and
outputs
0.0 V during data, 0.3 V at
start/end of packet
1.4 V
6-12
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
6.3.1 25 MHz Input/Output Clock Timing Characteristics
Table 6.8
25 MHz Input/Output Clock1
Limit
Sym
Parameter
Min
Typ
Max
Unit
Conditions
39.996
40
40.004
ns
Clock applied to OSCIN
t1
OSCIN Period
t2
OSCIN High Time
16
ns
Clock applied to OSCIN
t3
OSCIN Low Time
16
ns
Clock applied to OSCIN
t4
OSCIN to TX_CLK
Delay
10
ns
100 Mbits/s
20
ns
10 Mbits/s
1. Refer to Figure 6.1 for Timing Diagram
Figure 6.1
25 MHz Output Timing
t1
t2
t3
OSCIN
t4
TX_CLK
(100 Mbits/s)
t4
t4
TX_CLK
(10 Mbits/s)
AC Electrical Characteristics
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-13
Draft 6/5/00
6.3.2 Transmit Timing Characteristics
Table 6.9 shows the Transmit AC timing parameters. See Figure 6.2 and
Figure 6.3 for the 100 Mbits/s and 10 Mbits/s transmit timing diagrams.
Table 6.9
Transmit Timing
Limit
Sym
t11
t12
t13
Parameter
TX_CLK Period
TX_CLK Low Time
TX_CLK High Time
Min
Typ
Max
Unit
39.996
40
40.004
ns
100 Mbits/s
399.96
400
400.04
ns
10 Mbits/s
16
20
24
ns
100 Mbits/s
160
200
240
ns
10 Mbits/s
16
20
24
ns
100 Mbits/s
160
200
240
ns
10 Mbits/s
10
ns
t14
TX_CLK Rise/Fall Time
t15
TX_EN Setup Time
15
ns
t16
TX_EN Hold Time
0
ns
t17
CRS During Transmit
Assert Time
t18
CRS During Transmit
Deassert Time
ns
100 Mbits/s
400
ns
10 Mbits/s
160
ns
100 Mbits/s
900
ns
10 Mbits/s
Note 1
TXD Setup Time
15
ns
t20
TXD Hold Time
0
ns
t21
TX_ER Setup Time
15
ns
t22
TX_ER Hold Time
0
ns
t23
Transmit Propagation Delay
t24
Transmit Output Jitter
t25
Transmit SOI Pulse Width
To 0.3 V
t26
Transmit SOI Pulse Width to
40 mV
Note 1
140
ns
100 Mbits/s, MII
140
ns
100 Mbits/s, FBI
600
ns
10 Mbits/s
0.7
ns pk-pk
100 Mbits/s
5.5
ns pk-pk
10 Mbits/s
ns
10 Mbits/s
ns
10 Mbits/s
250
4500
(Sheet 1 of 2)
6-14
Note1
40
t19
60
Conditions
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Table 6.9
Transmit Timing (Cont.)
Limit
Sym
Parameter
t27
PLEDn Delay Time
t28
PLEDn Pulse Width
Min
Typ
80
Max
Unit
Conditions
25
ms
PLEDn
programmed for
activity
105
ms
PLEDn
programmed for
activity
(Sheet 2 of 2)
1. Setup time measured with 5 pF loading on TXC. Additional leading will create a delay on TXC rise
time, which requires increased setup times.
Figure 6.2
Transmit Timing - 100 Mbits/s
MII 100 Mbits/s
t11
TX_CLK
t15
t16
t12
t13
t14
t14
TX_EN
t17
t18
CRS
t20
t19
TXD[3:0]
N0
N1
N2
N3
t21
t22
TX_ER
t24
t23
TPO
IDLE
IDLE
/J/K/
DATA
/T/R/
IDLE
t27
t28
PLEDn
FBI 100 Mbits/s
Same as MII 100 Mbits Except:
1. TX_ER Converted to TXD4
2. RX_ER Converted to RXD4
AC Electrical Characteristics
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-15
Draft 6/5/00
Figure 6.3
Transmit Timing - 10 Mbits/s
MII 10 Mbits/s
t11
TX_CLK
t15
t16
t12
t13
t14
t14
TX_EN
t17
t18
CRS
t20
t19
TXD[3:0]
N0
N1
N2
N3
t24
t23
TP0
PREAMBLE
t27
PREAMBLE
t25
DATA
DATA
t28
PLEDn
6-16
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
SOI
t26
Draft 6/5/00
6.3.3 Receive Timing Characteristics
Table 6.10 shows the Receive AC timing parameters. See Figure 6.4
through Figure 6.8 for the receive timing diagrams.
Table 6.10
Receive Timing
Limit
Sym
t31
t32
t33
t34
t37
t38
t39
t40
Parameter
Min
Typ
Max
Unit
200
ns
100 Mbits/s, MII
200
ns
100 Mbits/s, FBI
700
ns
10 Mbits/s
240
ns
100 Mbits/s, MII
240
ns
100 Mbits/s, FBI
600
ns
10 Mbits/s. relative to start
of SOI pulse
240
ns
100 Mbits/s
3600
ns
10 Mbits/s
280
ns
100 Mbits/s
1000
ns
10 Mbits/s. relative to start
of SOI pulse
−8
8
ns
100 Mbits/s
−80
80
ns
10 Mbits/s
Start Of Packet To
CRS
Assert Delay
End Of Packet To
CRS
Deassert Delay
130
Start Of Packet To
RX_DV Assert
Delay
End Of Packet To
RX_DV Deassert
Delay
RX_CLK To
RX_DV,
RXD, RX_ER
Delay
RX_CLK High
Time
RX_CLK Low Time
SOI Pulse
Minimum Width
Required for Idle
Detection
Conditions
18
20
22
ns
100 Mbits/s
180
200
600
ns
10 Mbits/s
18
20
22
ns
100 Mbits/s
180
200
600
ns
10 Mbits/s
200
ns
10 Mbits/s measure TPI±
from last zero cross to
0.3V point.
125
AC Electrical Characteristics
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-17
Draft 6/5/00
Table 6.10
Receive Timing (Cont.)
Limit
Sym
t41
Parameter
Min
Receive Input Jitter
Typ
Max
Unit
3.0
ns pk pk
100 Mbits/s
13.5
ns pk pk
10 Mbits/s
25
ms
PLEDn programmed for
activity
105
ms
PLEDn programmed for
activity
t43
PLEDn Delay Time
t44
PLEDn Pulse
Width
t45
RX_CLK, RXD,
CRC, RX_DV,
RX_ER Output
Rise and Fall
Times
10
ns
t46
RX_EN Deassert
to Rcv MII Output
HI-Z Delay
40
ns
t47
RX_EN Assert to
Rcv MII Output
Active Delay
40
ns
6-18
80
Conditions
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Figure 6.4
Receive Timing, Start of Packet - 100 Mbits/s
MII 100 Mbits/s
TPI+/−
DATA
T
R
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
t32
CRS
t39
t38
RX_CLK
RX
RX
RX
RX
RX
RX
RX
RX
TX
TX
t37
t34
RX_DV
RXD[3:0]
DATA
DATA
DATA
DATA
DATA
DATA
DATA
FBI 100 Mbits/s
Same as MII 100 Mbits Except:
1. TX_ER converted to RXD4
2. RX_ER converted to TXD4
AC Electrical Characteristics
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-19
Draft 6/5/00
Figure 6.5
Receive Timing, End of Packet - 100 Mbits/s
MII 100 Mbits/s
TPI+/−
DATA
T
R
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
t32
CRS
t39
t38
RX_CLK
RX
RX
RX
RX
RX
RX
RX
RX
TX
t37
t34
RX_DV
RXD[3:0]
DATA
DATA
DATA
DATA
DATA
DATA
DATA
FBI 100 Mbits/s
Same as MII 100 Mbits Except:
1. TX_ER converted to RXD4
2. RX_ER converted to TXD4
6-20
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
TX
I
Draft 6/5/00
Figure 6.6
Receive Timing, Start of Packet - 10 Mbits/s
MII 10 Mbits/s
t41
DATA
TPI+/−
DATA
t31
CRS
t38
RX_CLK
TX
TX
TX
TX
t39
TX
RX
RX
RX
RX
RX
PREAMBLE
PREAMBLE
DATA
DATA
RX
t37
t33
RX_DV
t37
RXD[3:0]
DATA
RX_ER
t43
t44
PLEDn
AC Electrical Characteristics
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-21
Draft 6/5/00
Figure 6.7
Receive Timing, End of Packet - 10 Mbits/s
MII 10 Mbits/s
t41
TPI+/−
DATA
SOI
DATA DATA DATA DATA
t40
t32
CRS
t38
RX_CLK
RX
RX
RX
RX
RX
RX
RX
t39
RX
t37
t34
RX_DV
RXD[3:0]
Figure 6.8
DATA
DATA
DATA
DATA
DATA
DATA
DATA
RX_EN Timing
RX_EN
RX_CLK
RXD[3:0]
RX_DV
RX_ER
COL
6-22
t46
t47
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
TX
TX
Draft 6/5/00
6.3.4 Collision and JAM Timing Characteristics
Table 6.11 shows the Collision and JAM timing parameters. See
Figure 6.9 through Figure 6.14 for the associated timing diagrams.
Table 6.11
Collision and Jam Timing
LIMIT
SYM
t51
t52
t53
t54
PARAMETER
MIN
TYP
MAX
UNIT
200
ns
100 Mbits/s
700
ns
10 Mbits/s
240
ns
100 Mbits/s
300
ns
10 Mbits/s
200
ns
100 Mbits/s
700
ns
10 Mbits/s
240
ns
100 Mbits/s
300
ns
10 Mbits/s
25
ms
PLEDn programmed for collision
105
ms
PLEDn programmed for collision
5120
ns
Rcv Packet Start To
COL Assert Time
Rcv Packet Stop To
COL Deassert Time
130
Xmt Packet Start To
COL Assert Time
Xmt Packet Stop To
COL Deassert Time
CONDITIONS
t55
PLEDn Delay Time
t56
PLEDn Pulse Width
t57
Collision Test Assert
Time
t58
Collision Test
Deassert Time
40
ns
t59
CRS Assert To
Transmit
JAM Packet Start
During JAM
300
ns
100 Mbits/s
800
ns
10 Mbits/s
COL Rise And Fall
Time
10
ns
t601
80
1. Timing not shown
AC Electrical Characteristics
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-23
Draft 6/5/00
Figure 6.9
Collision Timing, Receive 100 Mbits/s
MII 100 Mbits/s
TPO+/−
I
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
TPI+/−
I
I
I
I
J
K
DATA
DATA
DATA
DATA
T
R
I
I
t51
t52
COL
t55
t56
PLEDn
FBI 100 Mbits/s
Same as MII 100 Mbits
Figure 6.10 Collision Timing, Receive 10 Mbits/s
MII 100 Mbits/s
TPO+/−
TPI+/−
t52
t51
COL
t55
t56
PLEDn
6-24
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Figure 6.11 Collision Timing, Transmit - 100 Mbits/s
MII 100 Mbits/s
TPI+/−
I
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
TPO+/−
I
I
I
I
J
K
DATA
DATA
DATA
DATA
T
R
I
I
t53
t54
COL
t55
t56
PLEDn
FBI 100 Mbits/s
Same as MII 100 Mbits
Figure 6.12 Collision Timing, Transmit - 10 Mbits/s
MII 100 Mbits/s
TPI+/−
TPO+/−
t54
t53
COL
t55
t56
PLEDn
Figure 6.13 Collision Test Timing
TX_EN
t57
t58
COL
AC Electrical Characteristics
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-25
Draft 6/5/00
Figure 6.14 JAM Timing
MII 100 Mbits/s
JAMn
TPO+/−
I
I
J
K
DATA
DATA DATA DATA DATA
DATA
DATA DATA DATA
JAM
JAM
DATA DATA
DATA
t53
CRS
t59
TPO+/−
I
I
I
I
I
J
K
t53
JAM
JAM
R
T
t54
COL
FBI 100 Mbits/s
Same as MII 100 Mbits
6-26
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
I
I
I
Draft 6/5/00
6.3.5 Link Pulse Timing Characteristics
Table 6.12 shows the Link Pulse AC timing parameters. See Figure 6.15
and Figure 6.16 for the Link Pulse timing diagrams.
Table 6.12
Link Pulse Timing
Limit
Sym
Parameter
Min
Typ
Max
Unit
Condition
t61
NLP Transmit Link Pulse
Width
See Figure 2.7
ns
t62
NLP Transmit Link Pulse
Period
8
t63
NLP Receive Link Pulse
Width Required For
Detection
50
t64
NLP Receive Link Pulse
Minimum Period Required
For Detection
6
7
ms
link_test_min
t65
NLP Receive Link Pulse
Maximum Period Required
For Detection
50
150
ms
link_test_max
t66
NLP Receive Link Pulses
Required To Exit Link Fail
State
3
3
Link
Pulses
lc_max
t67
FLP Transmit Link Pulse
Width
100
150
ns
t68
FLP Transmit Clock Pulse To
Data Pulse Period
55.5
62.5
69.5
µs
t69
FLP Transmit Clock Pulse To
Clock Pulse Period
111
125
139
µs
t70
FLP Transmit Link Pulse
Burst Period
8
22
ms
t71
FLP Receive Link Pulse
Width Required For
Detection
50
t72
FLP Receive Link Pulse
Minimum Period Required
For Clock Pulse Detection
5
24
ms
ns
3
interval_timer
transmit_link_burst
_timer
ns
25
µs
flp_test_min_timer
AC Electrical Characteristics
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-27
Draft 6/5/00
Table 6.12
Link Pulse Timing (Cont.)
Limit
Sym
Parameter
Min
Typ
Max
Unit
Condition
t73
FLP Receive Link Pulse
Maximum Period Required
For Clock Pulse Detection
165
185
µs
flp_test_max_timer
t74
FLP Receive Link Pulse
Minimum Period Required
For Data Pulse Detection
15
47
µs
data_detect_min_
timer
t75
FLP Receive Link Pulse
Maximum Period Required
For Data Pulse Detection
78
100
µs
data_detect_max_
timer
t76
FLP Receive Link Pulses
Required To Detect Valid
FLP Burst
17
17
Link
Pulses
t77
FLP Receive Link Pulse
Burst Minimum Period
Required For Detection
5
7
ms
nlp_test_min_timer
t78
FLP Receive Link Pulse
Burst Maximum Period
Required For Detection
50
150
ms
nlp_test_max_
timer
t79
FLP Receive Link Pulses
Bursts Required To Detect
AutoNegotiation Capability
3
3
Link
Pulse
t80
FLP Receive Acknowledge
Fail Period
1200
1500
ms
t81
FLP Transmit Renegotiate
Link Fail Period
1200
1500
ms
break_link_timer
t82
NLP Receive Link Pulse
Maximum Period Required
For Detection After FLP
Negotiation Has Completed
750
1000
ms
link_fail_inhibit_
timer
6-28
3
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Figure 6.15 NLP Link Pulse Timing
a. Transmit NLP
TPO+/−
t61
t62
b. Receive NLP
TPI+/−
t63
t64
t65
t66
PLEDn
Figure 6.16 FLP Link Pulse Timing
a. Transmit FLP and Transmit FLP Burst
CLK
DATA
CLK
DATA
CLK
CLK
DATA
TPO+/−
t67
t68
t69
t70
b. Receive FLP
CLK
DATA
CLK
DATA
TPI+/−
t71
31.25
62.50
93.75
125.00
156.25
t72
t73
t74
t75
c. Receive FLP Burst
TPI+/−
t77
t78
t79
PLEDn
AC Electrical Characteristics
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-29
Draft 6/5/00
6.3.6 Jabber Timing Characteristics
Table 6.13 shows the Jabber AC timing parameters. See Figure 6.17 for
the Jabber timing diagram.
Table 6.13
Jabber Timing
Limit
Sym
Parameter
Min
Typ
Max
Unit
Conditions
t91
Jabber Activation Delay Time
50
100
ms
10 Mbits/s
t92
Jabber Deactivation Delay Time
250
750
ms
10 Mbits/s
Figure 6.17 Jabber Timing
MII 100 Mbits/s
Not applicable
FBI 100 Mbits/s
Not applicable
MI 10 Mbits/s
TXEN
t91
TPO+/−
t91
t92
COL
t91
CRS
6-30
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
6.4 LED Driver Timing Characteristics
Table 6.14 shows the Jabber AC timing parameters. See Figure 6.18 for
the Jabber timing diagram.
Table 6.14
LED Driver Timing
Limit
Sym
Parameter
Min
Typ
Max
Unit
Conditions
t96
PLED[5:0]n On Time
80
105
ms
PLED[5:0]n
programmed to blink
t97
PLED[5:0]n Off Time
80
105
ms
PLED[5:0]n
programmed to blink
Figure 6.18 LED Driver Timing
t96
t97
PLED[5:0]n
LED Driver Timing Characteristics
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-31
Draft 6/5/00
6.4.1 MI Serial Port Timing Characteristics
Table 6.15 shows the MI Serial Port AC timing parameters. See
Figure 6.19 and Figure 6.20 for the associated timing diagram.
Table 6.15
MI Serial Port Timing
Limit
Sym
Parameter
Min
Typ
Max
Unit
Conditions
t101
MDC High Time
20
ns
t102
MDC Low Time
20
ns
t103
MDIO Setup Time
10
ns
Write bits
t104
MDIO Hold Time
10
ns
Write bits
t105
MDC To MDIO Delay
20
ns
Read bits
t106
MDIO Hi-Z To Active Delay
20
ns
Write-Read Bit
Transition
t107
MDIO Active To HI-Z Delay
20
ns
Read-Write bit
transition
t108
Frame Delimiter (Idle)
t109
End Of Frame To MDINTn
Transition
100
ns
t110
MDC To MDIO Interrupt
Pulse Assert Delay
100
ns
t111
MDC To MDIO Interrupt
Pulse Deassert Delay
100
ns
6-32
32
Clocks
Number of
consecutive MDC
clocks with MDIO = 1
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Figure 6.19 MI Serial Port Timing
t102
t101
MDC
1
0
15
ST1
ST0
REGAD0
16
17
t105
t106
TA1
TA0
30
31
t107
D15
D14
D0
t104
t103
MDIO
(WRITE)
14
t104
t103
MDIO
(READ)
13
ST1
ST0
REGAD0
TA1
TA0
D15
D1
D0
t109
MDINTn
Figure 6.20 MDIO Interrupt Pulse Timing
Internal
Interrupt
Signal
MDC
t110
t111
MDIO
LED Driver Timing Characteristics
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-33
Draft 6/5/00
6.5 Pinouts and Package Drawings
This section contains the alphabetical and numerical pin listings for the
L80223 as well as its pinouts and package drawing.
6.5.1 Pinouts
Table 6.16 and Table 6.17 contain the list of L80223 signals. The first
table lists the signals by category and the second lists them by pin
number.
Table 6.16
L80223 Pin List (by Signal Category)
Pin Name
Pin
Number
Description
Media Interface
REXT
50
Transmit Current Set
SD/FXDISn
53
Signal Detect/FX Interface Disable
SD_THR
51
Signal Detect Input Threshold Level Set
TPI -/FXO+
59
Twisted Pair Receive Input, Negative/Fiber Pair Transmit Output,
Positive
TPI+/FXO-
58
Twisted Pair Receive Input, Positive/Fiber Pair Transmit Output,
Negative
TPO-/FXI+
55
Twisted Pair Transmit Output, Negative/Fiber Pair Transmit Input,
Positive
TPO+/FXI-
54
Twisted Pair Transmit Output, Positive/Fiber Pair Transmit Input,
Negative
CRS
13
Carrier Sense Output
OSCIN
42
Clock Oscillator Input
RX_CLK
26
Receive Clock Output
RX_DV
14
Receive Data Valid Output
RX_EN/JAMn
27
Receive Enable Input/JAM Input
RX_ER/RXD4
18
Receive Error Output/Fifth Receive Data Bit Output
RXD0
22
Receive Data Output.
RXD1
21
Receive Data Output.
Controller Interface
6-34
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Table 6.16
L80223 Pin List (by Signal Category) (Cont.)
Pin Name
Pin
Number
RXD2
20
Receive Data Output.
RXD3
19
Receive Data Output
TX_CLK
34
Transmit Clock Output
TX_EN
40
Transmit Enable Input
TX_ER/TXD4
39
Transmit Error Input/Fifth Transmit Data Bit Input
TXD0
35
Transmit Data Input.
TXD1
36
Transmit Data Input.
TXD2
37
Transmit Data Input.
TXD3
38
Transmit Data Input
Description
Management Interface (MI)
MDC
10
Management Interface (MI) Clock Input
MDIO
11
Management Interface (MI) Data Input/Output
MDINTn/MDA4n
9
Management Interface (MI) Data Input/Output
PLED0n/MDA0n
61
Programmable LED Output /Management Interface Address Input.
PLED1n/MDA1n
62
Programmable LED Output /Management Interface Address Input
PLED2n/MDA2n
3
Programmable LED Output /Management Interface Address Input
PLED3n/MDA3n
4
Programmable LED Output /Management Interface Address Input
PLED4n
2
Programmable LED Output
PLED5n
63
Programmable LED Output
ANEG
30
AutoNegotiation Input
COL
12
Collision Output
DPLX
29
Full/Half Duplex Select Input
RESETn
44
Reset Input
RPTR
24
Repeater Mode Enable Input
SPEED
28
Speed Select Input
Miscellaneous
Pinouts and Package Drawings
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-35
Draft 6/5/00
Table 6.16
L80223 Pin List (by Signal Category) (Cont.)
Pin Name
Pin
Number
Description
Power
VDD1
56
VDD2
57
VDD3
7
VDD4
8
VDD5
25
VDD6
32
Positive Supply. 3.3V 5% Volts
Ground
GND1
52
GND2
60
GND3
6
GND4
41
GND5
23
GND6
31
Ground
No Connection
6-36
NC
1
NC
5
NC
15
NC
16
NC
17
NC
33
NC
43
NC
45
NC
46
NC
47
NC
49
NC
48
NC
64
No Connection
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
.
Table 6.17
Pin
Number
L80223 Pin List (by Pin Number)
Pin Name
Description
1
NC
No Connection
2
PLED4n
Programmable LED Output
3
PLED2n/MDA2n
Programmable LED Output /Management Interface Address Input
4
PLED3n/MDA3n
Programmable LED Output /Management Interface Address Input
5
NC
No Connect
6
GND3
Ground
7
VDD3
Positive Supply. 3.3V 5% Volts
8
VDD4
Positive Supply. 3.3V 5% Volts
9
MDINTn/MDA4n
Management Interface (MI) Data Input/Output
10
MDC
Management Interface (MI) Clock Input
11
MDIO
Management Interface (MI) Data Input/Output
12
COL
Collision Output
13
CRS
Carrier Sense Output
14
RX_DV
Receive Data Valid Output
15
NC
No Connect
16
NC
No Connect
17
NC
No Connect
18
RX_ER/RXD4
Receive Error Output/Fifth Receive Data Bit Output
19
RXD3
Receive Data Output
20
RXD2
Receive Data Output.
21
RXD1
Receive Data Output.
22
RXD0
Receive Data Output.
23
GND5
Ground
24
RPTR
Repeater Mode Enable Input
25
VDD5
Positive Supply. 3.3V 5% Volts
26
RX_CLK
Receive Clock Output
27
RX_EN/JAMn
Receive Enable Input
Pinouts and Package Drawings
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-37
Draft 6/5/00
Table 6.17
Pin
Number
6-38
L80223 Pin List (by Pin Number) (Cont.)
Pin Name
Description
28
SPEED
Speed Select Input
29
DPLX
Full/Half Duplex Select Input
30
ANEG
AutoNegotiation Input
31
GND6
Ground
32
VDD6
Positive Supply. 3.3V 5% Volts
33
NC
No Connect
34
TX_CLK
Transmit Clock Output
35
TXD0
Transmit Data Input.
36
TXD1
Transmit Data Input.
37
TXD2
Transmit Data Input.
38
TXD3
Transmit Data Input
39
TX_ER/TXD4
Transmit Error Input/Fifth Transmit Data Bit Input
40
TX_EN
Transmit Enable Input
41
GND4
Ground
42
OSCIN
Clock Oscillator Input
43
NC
No Connect
44
RESETn
Reset Input
45
NC
No Connect
46
NC
No Connect
47
NC
No Connect
48
NC
No Connect
49
NC
No Connect
50
REXT
Transmit Current Set
51
SD_THR
Signal Detect Input Threshold Level Set
52
GND1
Ground
53
SD/FXDISn
Signal Detect/FX Interface Disable
54
TPO+/FXI-
Twisted Pair Transmit Output, Positive/Fiber Pair Transmit Input,
Negative
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Table 6.17
L80223 Pin List (by Pin Number) (Cont.)
Pin
Number
Pin Name
Description
55
TPO-/FXI+
Twisted Pair Transmit Output, Negative/Fiber Pair Transmit Input,
Positive
56
VDD1
Positive Supply. 3.3V 5% Volts
57
VDD2
Positive Supply. 3.3V 5% Volts
58
TPI+/FXO-
Twisted Pair Receive Input, Positive/Fiber Pair Transmit Output,
Negative
59
TPI -/FXO+
Twisted Pair Receive Input, Negative/Fiber Pair Transmit Output,
Positive
60
GND2
Ground
61
PLED0n/MDA0n
Programmable LED Output /Management Interface Address Input.
62
PLED1n/MDA1n
Programmable LED Output /Management Interface Address Input
63
PLED5n
Programmable LED Output
64
NC
No Connect
Pinouts and Package Drawings
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-39
Draft 6/5/00
6.5.2 L80223 Pin Layout
Figure 6.21 shows the pin layout for the L80223 package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
L80223
64-Pin LQFP
Top View
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
NC
NC
NC
RESETn
NC
OSCIN
GND4
TX_EN
TX_ER/TXD4
TXD3
TXD2
TXD1
TXD0
TX_CLK
NC
NC
RX_ER/RXD4
RXD3
RXD2
RXD1
RXD0
GND5
RPTR
VDD5
RX_CLK
RX_EN/JAMn
SPEED
DPLX
ANEG
GND6
VDD6
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
PLED4n
PLED2n/MDA2n
PLED3n/MDA3n
NC
GND3
VDD3
VDD4
MDINTn/MDA4n
MDC
MDIO
COL
CRS
RX_DV
NC
NC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
NC
PLED5n
PLED1n/MDA1n
PLED0n/MDA0n
GND2
TPI−FXO+
TPI+FXO−
VDD2
VDD1
TPO−/FXI+
TPO+/FXI−
SD/FXDISn
GND1
SD_THR
REXT
NC
Figure 6.21 L80223 64-Pin LQFP, Top View
1. NC pins are not connected.
6-40
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
6.6 Mechanical Drawing
This section contains the mechanical drawing for the L80223 64-pin
LQFP package.
Mechanical Drawing
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
6-41
Draft 6/5/00
Figure 6.22 64-Pin LQFP Mechanical Drawing
ccc
A
D
Pin 1
Dimension Table
See
Detail A
See b
Detail B
Symbol
b
e
ccc
ddd
D
E
L
L1
R
R1
A
A1
A2
c
D1
E1
@
@1
@2
E
e
D1
E1
@
R
ddd
@1
L
b
L1
@2
c
R1
Detail B
A2
A1
A
Note:
2. All Dimensions are in millimeters.
3. Dimensions do not include mold flash. Maximum allowable
flash is 0.25.
4. All leads are coplanar to a tolerance of 0.08 (ccc). Bent
leads to a tolerance of 0.08 (ddd).
Important:
6-42
Detail B
This drawing may not be the latest version.
Specifications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Dimensions
0.17 – 0.27
0.50 Basic
Max. 0.08
Max. 0.08
11.85 – 12.15
11.85 – 12.15
0.45 – 0.75
1.0 Ref
0.08 – 0.20
Min. 0.08
Max. 1.60
0.05 – 0.15
1.292 – 1.508
0.09 – 0.20
9.90 – 10.10
9.90 – 10.10
0˚ – 7˚
Min. 0˚
12˚
Draft 6/5/00
Appendix A
Application Information
This chapter contains application information for the device. It contains
the following sections:
•
Section A.1, “Example Schematics”
•
Section A.2, “TP Transmit Interface”
•
Section A.3, “TP Receive Interface”
•
Section A.4, “TP Transmit Output Current Set”
•
Section A.5, “Cable Selection”
•
Section A.6, “Transmitter Droop”
•
Section A.7, “Automatic JAM”
•
Section A.8, “FX Interface”
•
Section A.9, “MII Controller Interface”
•
Section A.10, “FBI Controller Interface”
•
Section A.11, “Serial Port”
•
Section A.12, “Oscillator”
•
Section A.13, “LED Drivers”
•
Section A.14, “Repeater Applications”
•
Section A.15, “Power Supply Decoupling”
A.1 Example Schematics
A typical example schematic of the L80223 used in an network interface
adapter card application is shown in Figure A.1; a hub application is
shown in Figure A.2; and an external PHY application is shown in
Figure A.3.
L80223 10BASE-T/100BASE-TX/FX Ethernet PHY
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
A-1
Draft 6/5/00
Figure A.1
Typical Network Interface Adapter Card Schematic Using the L80223
VDD [6:1]
LSI
L80C300
or Equivalent
System
Bus
Bus
Interface
50
1%
TX_CLK
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_ER
COL
RX_CLK
RXD3
RXD2
RXD1
RXD0
CRS
RX_DV
RX_ER
MDC
MDIO
10/100 Mbits/s
Ethernet
Controller
50
1%
1:1
TPO+
RJ45
TPO−
2
Optional
To system
Reset or Float
1:1
TPI+
25
1%
6
25
1%
6X
Optional
0.01
MDINTn
RX_EN/JAMn
500
6
75
25
1%
RESETn
LED
PLED5n
PLED4n
PLED3n
PLED2n
PLED1n
PLED0n
25
1%
TPI−
REXT
OSCIN
10 KΩ
1%
25 MHz
SPEED
Pinstrap to
VDD or GND
DPLX
ANEG
GND [6:1]
A-2
4
5
7
8
3
75
L80223
Optional
1
Application Information
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
75
0.01
2 KV
75
Draft 6/5/00
Figure A.2
Typical Switching Port Schematic Using L80223
VDD [6:1]
LSI
L84C300
or Equivalent
10/100 Mbits/s
Ethernet
Controller
Switch
Fabric
Optional
Optional
To system
Reset or Float
500
6
LED
4X
Optional
4
50K
1:1
1
RJ45
TPO−
2
4
5
7
8
3
75
1:1
TPI+
25
1%
6
25
1%
L80223
0.01
MDINTn
75
75
75
RX_EN/JAMn
25
1%
PLED5n
PLED4n
PLED3n
PLED2n
PLED1n
PLED0n
LA_LEDn
CD_LEDn
FD_LEDn
L_LEDn
500
50
1%
TPO+
RESETn
LED
6X
Optional
50
1%
TX_CLK
TXD
TXD2
TXD1
TXD0
TX_EN
TX_ER
COL
RX_CLK
RXD3
RXD2
RXD1
RXD0
CRS
RX_DV
RX_ER
MDC
MDIO
0.01
2 KV
25
1%
TPI−
REXT
10 KΩ
1%
SPEED
Pinstrap to
VDD or GND
DPLX
ANEG
25 MHz
System Clock
OSCIN
GND [6:1]
Example Schematics
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
A-3
Draft 6/5/00
Figure A.3
Typical External PHY Schematic Using L80223
1.5 KΩ
5%
24.9
1%
VDD [6:1]
50
1%
TX_CLK
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_ER
COL
RX_CLK
RXD3
RXD2
RXD1
RXD0
CRS
RX_DV
RX_ER
MDC
MDIO
MII
Connectors
Optional
Optional
Optional
LED
6X
Optional
500
6
50
1%
1:1
TPO+
1
RJ45
TPO−
2
1:1
TPI+
25
1%
6
25
1%
L80223
0.01
MDINTn
75
25
1%
RESETn
PLED5n
PLED4n
PLED3n
PLED2n
PLED1n
PLED0n
25
1%
TPI−
OSCIN
25 MHz
System
Clock
10 KΩ
1%
SPEED
DPLX
ANEG
GND [6:1]
A-4
75
RX_EN/JAMn
REXT
Pinstrap to
VDD or GND
4
5
7
8
3
75
Application Information
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
0.01
2 KV
75
Draft 6/5/00
A.2 TP Transmit Interface
The interface between the TP outputs on TPO± and the twisted pair
cable is typically transformer coupled and terminated with the two
resistors as shown in Figure A.1 through Figure A.3.
The transformer for the transmitter should have a winding ratio of 1:1 with
a center tap on the primary winding tied to VDD, as shown in Figure A.1
through Figure A.3. The specifications for the transformer are shown in
Table A.1. Sources for the transformer are listed in Table A.2.
Table A.1
TP Transformer Specification
Specification
Parameter
Transmit
Receive
1:1 CT
1:1
350
350
0.05–0.15
0.0–0.2
Capacitance (pF Max)
15
15
DC Resistance (Ω Max)
0.4
0.4
Turns Ratio
Inductance, ( HMin)
Leakage Inductance, ( H)
Table A.2
TP Transformer Sources
Vendor
Part Number
PULSE
H1089, H1102
BEL
S558-5999-J9
HALO
TG22-3506ND TG110-S050N2
The transmit output must be terminated with two external termination
resistors to meet the output impedance and return loss requirements of
IEEE 802.3. These two external resistors must be connected between
VDD and each of the TPO± outputs. Their value should be chosen to
provide the correct termination impedance when looking back through
the transformer from the twisted-pair cable, as shown in Figure A.1
TP Transmit Interface
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
A-5
Draft 6/5/00
through Figure A.3. The value of these two external termination resistors
depends on the type of cable the device drives. Refer to Section A.5,
“Cable Selection,” page A-8 for more details.
To minimize common mode output noise and to aid in meeting radiated
emissions requirements, it may be necessary to add a common mode
choke on the transmit outputs as well as add common mode bundle
termination. The qualified transformers mentioned in Table A.2 all contain
common mode chokes along with the transformers on both the transmit
and receive sides, as shown in Figure A.1 through Figure A.3. Common
mode bundle termination may be needed and can be achieved when the
unused pairs in the RJ45 connector are connected to chassis ground
through 75 ohm resistors and a 0.01 µF capacitor, as shown in
Figure A.1 through Figure A.3.
To minimize noise pickup into the transmit path in a system or on a PCB,
the loading on TPO± should be minimized and both outputs should
always be loaded equally.
A.3 TP Receive Interface
Receive data is typically transformer coupled into the receive inputs on
TPI± and terminated with external resistors as shown in Figure A.1
through Figure A.3.
The transformer for the receiver should have a winding ratio of 1:1, as
shown in Figure A.1 through Figure A.3. The specifications for this
transformer are shown in Table A.1 and sources for the transformer are
listed in Table A.2.
The receive input must be terminated with the correct termination
impedance to meet the input impedance and return loss requirements of
IEEE 802.3. In addition, the receive TP inputs must be attenuated. Both
the termination and attenuation is accomplished with four external
resistors in series across the TPI± inputs, as shown in Figure A.1 through
Figure A.3. Each resistor should be 25% of the total series resistance,
and the total series resistance should be equal to the characteristic
impedance of the cable (100 Ω for UTP, 150 Ω for STP). It is also
recommended that a 0.01 Fcapacitor be placed between the center of
the series resistor string and VDD to provide an AC ground for attenuating
A-6
Application Information
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
common mode signal at the input. This capacitor is also shown in
Figure A.1 through Figure A.3.
To minimize common mode input noise and to aid in meeting
susceptibility requirements, it may be necessary to add a common mode
choke on the receive input as well as add common mode bundle
termination. The qualified transformers mentioned in Table A.2 all contain
common mode chokes along with the transformers on both the transmit
and receive sides, as shown in Figure A.1 through Figure A.3. Common
mode bundle termination may be needed and can be achieved when the
receive secondary center tap and the unused pairs in the RJ45
connector are connected to chassis ground through 75 Ω resistors and
a 0.01 Fcapacitor, as shown in Figure A.1 through Figure A.3.
To minimize noise pickup into the receive path in a system or on a PCB,
loading on TPI should be minimized and both inputs should be loaded
equally.
A.4 TP Transmit Output Current Set
The TPO± output current level is set with an external resistor connected
between the REXT pin and GND. This output current is determined from
the following equation, where R is the value of REXT:
Iout
= (10K/R)
Iref
Where
Iref
= 40 mA (100 Mbits/s, UTP)
= 32.6 mA (100 Mbits/s, STP)
= 100 mA (10 Mbits/s, UTP)
= 81.6 mA (10 Mbits/s, STP)
REXT should typically be a 10 kΩ 1% resistor to meet IEEE 802.3
specified levels. Once REXT is set for the 100 Mbits/s and UTP modes
as shown by the equation above, Iref is then automatically changed inside
the device when the 10 Mbits/s mode or UTP120/STP150 modes are
selected.
TP Transmit Output Current Set
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
A-7
Draft 6/5/00
Keep REXT as close to the REXT and GND pins as possible to reduce
noise pickup into the transmitter.
Because the TP output is a current source, capacitive and inductive
loading can reduce the output voltage from the ideal level. Thus, in actual
application, it might be necessary to adjust the value of the output
current to compensate for external loading. One way to adjust the TP
output level is to change the value of the external resistor connected to
REXT.
A better way to adjust the TP output level is to use the Transmit Level
Adjust register bits (TLVL[3:0]) accessed through the MI serial port
Configuration 1 register. These four bits can adjust the output level by
−14% to +16% in 2% steps as described in Table 2.6.
A.5 Cable Selection
The L80223 can drive two different cable types:
•
100 Ohm unshielded twisted-pair, Category 5, or
•
150 Ohm shielded twisted-pair.
The L80223 must be properly configured for the type of cable to meet
the return loss specifications in IEEE 802.3. This configuration requires
appropriately setting the Cable Type Select (CABLE) bit in the MI serial
port Configuration 1 register and setting the value of some external
resistors, as described in Table A.3.
Table A.3
Cable Configuration
RTERM (Ohms)
CABLE
Bit
TPO
TPI
100 Ohm UTP, Cat. 5
UTP
50
100
150 Ohm STP
STP
75
150
Cable Type
The CABLE bit sets the output current level for the cable type. RTERM
in Table A.3 is the value of the termination resistors needed to meet the
level and return loss requirements. The value for RTERM on the TPO
outputs is for the two external termination resistors connected from VDD
A-8
Application Information
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
to TPO .Each value for RTERM on the TPI inputs is for the sum of the
four series resistors across TPI ,as shown in Figure A.1–Figure A.3.
These resistors should be 1% tolerance. Also note that some output level
adjustment may be necessary due to parasitics as described in Section
A.4, “TP Transmit Output Current Set,” page A-7.
IEEE 802.3 specifies that 10BASE-T and 100BASE-TX operate over
twisted-pair cable lengths of between 0–100 meters. The squelch levels
can be reduced by 4.5 dB if the Receive Input Level Adjust bit (RLVL0)
is set in the MI serial port Configuration 1 register. This allows the
L80223 to operate with up to 150 meters of twisted-pair cable. The
equalizer is already designed to accommodate between 0–125 meters of
cable.
A.6 Transmitter Droop
The IEEE 802.3 specification has a transmit output droop requirement for
100BASE-TX. Because the L80223 TP output is a current source, it has
no perceptible droop by itself. However, the inductance of the transformer
added to the device transmitter output as shown in Figure A.1 through
Figure A.3 causes droop to appear at the transmit interface to the TP
wire. If the transformer connected to the L80223 outputs meets the
requirements of Table A.1, the transmit interface to the TP cable then
meets the IEEE 802.3 droop requirements.
A.7 Automatic JAM
The L80223 has an automatic JAM generation feature that automatically
transmits a JAM packet when receive activity is detected. This feature is
primarily designed to give the user a means to easily implement
half-duplex flow control. In a typical application, a watermark signal from
a system FIFO or memory is be tied directly to the JAMn pin. When the
system FIFO is nearly full and more data is being received, the device
automatically transmits a JAM packet and creates a collision, which
causes the far end device to back off, allowing time for the system FIFO
to empty itself.
Transmitter Droop
A-9
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
The JAM generation feature requires that the RX_EN/JAMn pin be
programmed for JAM. To do this, set the R/J_CFG bit in the MI serial
port Configuration 2 register.
A-10
Application Information
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
A.8 FX Interface
The FX interface has differential PECL inputs (FXI+/−) and outputs
(FXO+/−) that are typically connected to an external fiber optic
transceiver. The FX interface outputs are designed to drive 100-ohm
differential loads. The FX interface can be directly coupled to either
3.3 V or 5 V fiber optic transceivers with minimum external components,
as described in the following sections.
A.8.1 Connection to 3.3 V Transceivers
The schematic for a typical connection of the device to an external 3.3 V
fiber optic transceiver is shown in Figure A.4.
The 70- and 173-ohm resistors on FXO+/− are used for 100 ohm
termination and for biasing the device FXO+/− outputs to match the input
range on the 3.3 V fiber optic transceiver inputs. Place these resistors as
close as possible on the PCB to the fiber optic transceiver inputs. In
addition, keep the parasitic loading on FXO+ and FXO− to a minimum
and matched as well as possible.
The 127 and 83 ohm resistors on FXI+/− and SD/FXDISn are used for
100-ohm termination and for biasing the 3.3 V fiber optic transceiver
outputs to match the input range on the device FX inputs. Place these
resistors as close as possible on the PCB to the device FX inputs. In
addition, keep the parasitic loading on FXI+ and FXI− to a minimum and
matched as well as possible.
In the 3.3 V transceiver application, the SD_THR pin must be tied to
GND, as shown in Figure A.4. The SD_THR pin determines the
SD/FXDISn internal buffer ECL trip level. The SD/FXDISn internal buffer
trip level needs to be set to VDD − 1.3 V and must be referenced to the
3.3 V supply. Connecting SD_THR to GND causes the device to
internally set the ECL trip point on the SD/FXDISn input to VDD − 1.3 and
references it to the common 3.3 V supply.
FX Interface
A-11
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Figure A.4
Connection to 3.3 V Fiber Optic Transceivers
3.3 V
3.3 V
3.3 V
VDD
VDD
70Ω
TXO+
FXO+
3.3 V
L80223
PHY
173Ω
70Ω
FXO−
TXO−
173Ω 3.3 V
127Ω
FXI+
RX+
3.3 V
3.3 V Fiber
Optic
Transceiver
Fiber
83Ω
127Ω
FXI−
RX−
83Ω 3.3 V
127Ω
SD/FXDISn
83Ω
Signal
Detect
Output
SD_THR
GND
REXT
10 KΩ
GND
A.8.2 Connection to 5 V Transceivers
The schematic for a typical connection of the device to an external 5 V
transceiver is shown in Figure A.5.
A-12
Application Information
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Figure A.5
Connection to 5 V Fiber Optic Transceivers
3.3 V
5V
5V
VDD
VDD
62Ω
TX+
FXO+
263Ω
5V
L80223
PHY
62Ω
FXO−
TX−
263Ω 5 V
83Ω
RX+
FXI+
57Ω
5V
5 V Fiber
Optic
Transceiver
Fiber
83Ω
83Ω
57Ω
FXI−
83Ω
RX−
5V
83Ω
57Ω
SD/FXDISn
5V
Signal
Detect
Output
83Ω
15 KΩ
GND
SD_THR
10 KΩ
REXT
10 KΩ
GND
The 62- and 263-ohm resistors on FXO+/− are used for 100-ohm
termination and for biasing the 3.3 V device FXO+/− outputs to match
the input range on the 5V fiber optic transceiver inputs. Place these
resistors as closely as possible on the PCB to the fiber optic transceiver
inputs. In addition, keep the parasitic loading on FXO+ and FXO− to a
minimum and matched as well as possible.
FX Interface
A-13
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
The 83-, 57-, and 68-ohm resistors on FXI+/− and SD/FXDISn are used
for 100-ohm termination and for biasing the 5V fiber optic transceiver
outputs to match the input range on the 3.3V device FX inputs. Place
these resistors as closely as possible on the PCB to the device FX
inputs. In addition, keep the parasitic loading on FXI+ and FXI− to a
minimum and matched as well as possible.
In the 5 V transceiver application, the SD_THR pin needs to be tied to
VDD − 1.3 V, which can be done with an external resistor divider as
shown in Figure A.5. The voltage on the SD_THR pin determines the
SD/FXDISn internal buffer ECL trip level. The SD/FXDISn internal buffer
trip level needs to be set to VDD − 1.3 V and must be referenced to the
fiber optic transceiver 5 V supply. Using a resistor divider from the fiber
optic transceiver 5 V supply to generate the voltage for the SD_THR pin
references the SD/FXDISn ECL trip level to the transceiver 5 V supply.
This allows the device SD/FXDISn internal buffer ECL trip level to track
the supply variations of the fiber optic transceiver, allowing direct
connection of the fiber optic transceiver signal detect output to the device
SD/FXDISn input, as shown in Figure A.5.
A.8.3 Disabling the FX Interface
Connecting the SD/FXDISn pin to GND disables the FX interface. When
the FX interface is disabled, the TP interface is enabled, and vice versa.
A-14
Application Information
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
A.9 MII Controller Interface
The MII controller interface allows the L80223 to connect to any external
Ethernet controller without any glue logic, provided the external Ethernet
controller has an MII interface that complies with IEEE 802.3, as shown
in Figure A.1 through Figure A.3.
A.9.1 Clocks
Standard Ethernet controllers with an MII use TX_CLK to clock data in
on TXD[3:0]. TX_CLK is specified in IEEE 802.3 and on the L80223 to
be an output. If a non-standard controller or other digital device is used
to interface to the L80223, there might be a need to clock TXD[3:0] into
the L80223 on the edges of an external master clock. The master clock,
in this case, would be an input to the L80223. To do this, use OSCIN as
the master clock input. Because OSCIN generates TX_CLK inside the
L80223, data on TXD[3:0] can be clocked into the L80223 on edges of
output clock TX_CLK or input clock OSCIN. In the case where OSCIN is
used as the input clock, a crystal is no longer needed on OSCIN, and
TX_CLK can be left open or used for some other purpose.
A.9.2 Output Drive
The digital outputs on the L80223 controller signals meet the MII driver
characteristics specified in IEEE 802.3 and shown in Figure A.6 if
external 24.9 Ω 1% termination resistors are added. These termination
resistors are only needed if the outputs must drive an MII cable or other
transmission line type load, such as in the external PHY application
shown in Figure A.3. If the L80223 is used in embedded applications,
such as adapter cards and switching hubs (see Figure A.1 and
Figure A.2), these termination resistors are not needed.
MII Controller Interface
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
A-15
Draft 6/5/00
Figure A.6
MII Output Driver Characteristics
Voh
Vol
VDD
I2
Rol min = 40 ohm
V4
V2
I4
I1
V1
Rol min = 40 ohm
V3
I3
loh
lol
I–V
I (mA)
V (Volts)
I1, – V1
−20
1.10
I2, – V2
−4
2.40
I3, – V3
4
0.40
I4, – V4
43
3.05
A.9.3 MII Disable
Setting the MII disable bit (MII_DIS) in the MI serial port Control register
places the MII outputs in the high-impedance state and the disables the
MII inputs. When this bit is set to the disable state, the TP outputs are
also disabled and transmission is inhibited. The default value of this bit
when the device powers up or is reset is dependent on the physical
device address. If the device address latched into MDA[4:0] at reset is
0b11111, it is assumed that the device is being used in applications
where there maybe more than one device sharing the MII bus, such as
in the use of external PHYs or adapter cards. In this case, the device
powers up with the MII interface disabled. If the device address latched
into MDA[4:0] at reset is not 0b11111, it is assumed that the device is
being used in application where it is the only device on the MII bus, such
A-16
Application Information
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
as in the use of hubs, so the device powers up with the MII interface
enabled.
A.9.4 Receive Output Enable
The receive output enable pin, RX_EN, forces the receive and collision
MII/FBI outputs into the high-impedance state. More specifically, when
RX_EN is deasserted, the RX_CLK, RXD[3:0], RX_DV, RX_ER, and
COL pins are placed in a high-impedance state.
RX_EN can be used to “wire OR” the outputs of many L80223 devices
in multiport applications where only one device may be receiving at a
time, such as in a repeater application. Monitoring the CRS pin from
each individual port enables the repeater to assert RX_EN only to that
L80223 device that is receiving data. The method reduces, by eight per
device, the number of pins and PCB traces a repeater core IC requires.
Clear the R/J Configuration select bit (R/J_CFG) in the MI serial port
Configuration 2 register to enable the RX_EN function. When this bit is
cleared, the RX_EN/JAMn pin becomes RX_EN.
A.10 FBI Controller Interface
The FBI (Five Bit Interface) controller interface has the same
characteristics as that of the MII except that the data path is five bits wide
instead of 4 bits wide. The five bit wide data path is automatically
enabled when the 4B5B encoder is bypassed. Because the
encoder/decoder is bypassed, the FBI is used primarily for repeaters or
other applications where the full PHY is not needed. For more details
about the FBI, see Section A.14, “Repeater Applications,” page A-22.
FBI Controller Interface
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
A-17
Draft 6/5/00
A.11 Serial Port
The L80223 uses an MI serial port to access the device registers. Any
external device that has a IEEE 802.3 compliant MI interface can connect
directly to the L80223 without any glue logic, as shown in Figure A.1
through Figure A.3.
As described earlier, the MI serial port consists of eight signals: MDC,
MDIO, MDINTn, and MDA[4:0]n. However, only two signals, MDC and
MDIO, are needed to shift data in and out. MDA[4:0]n are not needed,
but are provided for convenience only.
Note that the MDA[4:0]n addresses are inverted inside the L80223 before
going to the MI serial port block. This means that the MDAn[4:0] pins
would have to be pin strapped to 0b11111 externally to successfully
match the MI physical address of 0b0000 on the PHYAD[4:0] bits
internally.
A.11.1 Polling and Interrupt
The device status bits can be monitored in one of two ways:
•
Polling the serial port, or
•
Responding to interrupts
The polling method reads the registers at regular intervals and compares
the status bits to their previous values to determine any changes. To
make polling simpler, all the registers can be accessed in a single read
or write cycle. To do this, set the register address bits REGAD[4:0] to
0b11111 and add enough clocks to read out all the bits (provided the
multiple register access feature has been enabled).
The interrupt feature detects changes in the status output bits without
register polling. When the device asserts an interrupt, it indicates that
one or more of the status output bits has changed since the last read
cycle. There are three interrupt output indicators on the device:
A-18
•
MDINTn pin assertion
•
Interrupt pulse on MDIO
•
INT bit set in the MI serial port Status Output register.
Application Information
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
An external device can use the interrupt indications to initiate a read
cycle. When an interrupt is detected, the individual registers (or multiple
registers) can be read out and the status bits compared against their
previous values to determine any changes. After the interrupt bits have
been read out, the interrupt signals are automatically deasserted.
A mask register bit exists for every status output bit in the MI serial port
Interrupt Mask register so that the interrupt bits can be individually
programmed for each application.
A.11.2 Multiple Register Access
If the MI serial port needs to be constantly polled in order to monitor
changes in status output bits, or if it is desired that all registers be read
or written in a single serial port access cycle, multiple register access
mode can be used. Multiple register access allows access to all registers
in a single MI serial port access cycle. When multiple register access is
enabled, all the registers are read or written when the register address
REGAD[4:0] = 0b11111. This eliminates the need to read or write
registers individually. Multiple register access mode is normally disabled.
To enable it, set the Multiple Register Access Enable (MREG) bit in the
MI serial port Configuration 2 register.
A.11.3 Serial Port Addressing
Tying the MDA[4:0]n pins to the desired value selects the device address
for the MI serial port. MDA[4:0]n share the same pins as the LED
outputs, as shown in Figure A.7a. At powerup or reset, the output drivers
are 3-stated for an interval called the power-on reset time. During the
power-on reset interval, the value on these pins is latched into the
device, inverted, and used as the MI serial port address. The LED
outputs are open-drain with internal pullup to VDD.
If an LED is to be connected on an LED output, an LED and resistor are
tied to VDD as shown in Figure A.6b. If a HIGH address is desired, the
LED to VDD automatically makes the latched address value a HIGH. If a
LOW value for the address is desired, a 50 KΩ resistor to GND must be
added as shown in Figure A.6b.
If no LEDs are needed on the LED outputs, the selection of addresses
can be done as shown in Figure A.6c. If a HIGH address is desired, the
pin should be left floating and the internal pullup pulls the pin HIGH
Serial Port
A-19
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
during power-on reset time and latches in a HIGH address value. If a
LOW address is desired, the LED and MDINTn output pins should be
tied either directly to GND or through an optional 50 KΩ resistor to GND.
The LED or MDINTn outputs should always be tied through a 50 KΩ
resistor to GND since they have both pullup and pulldown capability.
The optional 50K resistor also allows the MDINTn and PLED[3:0] pins to
be used as digital outputs under normal conditions.
Figure A.7
Serial Device Port Address Selection
a. Output Driver/Input Address Correspondence
MDA4n
MDA3n
MDA2n
MDA1n
MDA0n
MDINTn
PLED3n
PLED2n
PLED1n
PLED0n
b. Setting Address with LEDs
High
Low
LED
LED
500
500
MDINTn
PLED3n
PLED2n
PLED1n
PLED0n
50K
MDINTn
PLED3n
PLED2n
PLED1n
PLED0n
c. Setting Address without LEDs
High
Float
A-20
Low
MDINTn
PLED3n
PLED2n
PLED1n
PLED0n
50K
MDINTn
PLED3n
PLED2n
PLED1n
PLED0n
Application Information
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
A.12 Oscillator
The L80223 requires a 25 MHz reference frequency for internal signal
generation. This 25 MHz reference frequency can be generated from an
external 25 MHz crystal connected between OSCIN and GND or from
applying an external 25 MHz clock to OSCIN.
If the crystal oscillator is used, it needs only a crystal; no other external
capacitors or other components are required. The crystal must have the
characteristics shown in Table A.4. The crystal must be placed as close
as possible to the OSCIN and GND pins so that parasitics on OSCIN are
kept to a minimum.
Table A.4
Crystal Specifications
Parameter
Spec
Type
Parallel Resonant
Frequency
25 MHz ± 0.01%
Equivalent Series Resistance
40 Ω max
Load Capacitance
18 pF typical
Case Capacitance
7 pF maximum
Power Dissipation
1 mW maximum
A.13 LED Drivers
The LED outputs can all drive LEDs tied to VDD as shown in Figure A.1
through Figure A.3. The outputs can drive LEDs tied to either VDD or
GND. See Section 2.2.14, “LED Drivers,” page 2-37 for more details on
LED operation.
Oscillator
A-21
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
A.14 Repeater Applications
This section describes how to set up the L80223 to act as a repeater.
A.14.1 MII-Based Repeaters
Using the standard MII as the interface to the repeater core, the L80223
can be used as the physical interface for MII-based repeaters. For most
repeaters, it is necessary to disable the internal CRS loopback. To do
this, set the TXEB_CRS bit in the MI serial port Configuration 1 register.
For some particular types of repeaters, it may be desirable to either
enable or disable AutoNegotiation, force Half-Duplex operation, and
enable either 100 Mbits/s or 10 Mbits/s operation. To configure any of
these modes, set the appropriate bits in the MI serial port Control
register or appropriately assert or deassert the SPEED, DUPLX, and
ANEG pins on the device.
The L80223 has a RPTR pin that, when asserted, automatically
configures the device for one common type of repeater application. When
the RPTR pin is asserted:
•
TX_EN to CRS loopback is disabled
•
AutoNegotiation is disabled
•
Half-Duplex operation is selected
•
100 Mbits/s operation is selected
The MII requires 16 signals between the L80223 and a repeater core.
The MII signal count to a repeater core is 16 multiplied by the number of
ports, which can be quite large. The signal count between the L80223
and the repeater core can be reduced by 8 per device if the receive
output pins are shared and the RX_EN pin is used to enable only that
port where CRS is asserted. Refer to Section A.9, “MII Controller
Interface,” page A-15 for more details about using the RX_EN pin.
A.14.2 Non-MII Based Repeaters
The FBI interface available on the L80223 can be used to connect to
non-MII based repeaters that employ the industry popular five bit wide
interface.
A-22
Application Information
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
Because the FBI is a 5-bit interface, it requires that the 4B5B
encoder/decoder be bypassed. The FBI is automatically selected on the
L80223 when the 4B5B encoder/decoder is bypassed. To bypass the
4B5B encoder/decoder, set the BYP_ENC bit in the MI serial port
Configuration 1 register. Some applications may also require the
scrambler/descrambler to be bypassed. To bypass the
scrambler/descrambler, set the BYP_SCR bit in the MI serial port
Configuration 1 register.
For most repeaters, it is necessary to disable the internal CRS loopback.
To do this, set the TX_EN to CRS loopback disable bit (TXEN_CRS) in
the MI serial port Configuration 1 register.
For some particular types of repeaters, it may be desirable to either
enable or disable AutoNegotiation, force Half Duplex operation, and
enable either 100 Mbits/s or 10 Mbits/s operation. To configure any of
these modes, set the appropriate bits in the MI serial port Control
register.
The FBI requires 16 signals between the L80223 and a repeater core.
The FBI signal count to a repeater core is be 16 multiplied by the number
of ports, which can be quite large. The signal count between the L80223
and repeater core can be reduced by 8 per device if the receive output
pins are shared and RX_EN is used to enable only that port where CRS
is asserted. Refer to Section A.9, “MII Controller Interface,” page A-15 for
more details about using the RX_EN pin.
A.14.3 Clocks
Normally, transmit data over the MII is clocked into the L80223 on the
edge of the transmit output clock (TX_CLK). It may be desirable or
necessary in some repeater applications to clock in the transmit data
from a master clock generated at the repeater core. This requires that
transmit data (TXD[3:0]) be clocked into the device on edges of the
OSCIN input clock.
Notice from the timing diagrams that OSCIN generates TX_CLK, and
TXD[3:0] data is clocked into the L80223 on TX_CLK edges. This means
that TXD data is also clocked in on OSCIN edges as well. Thus, an
external clock driving the OSCIN input can also be used as the clock for
TXD[3:0].
Repeater Applications
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
A-23
Draft 6/5/00
A.15 Power Supply Decoupling
There are six VDD pins on the L80223 and six GND pins.
All the VDD pins should be connected together as closely as possible to
the device with a large VDD plane. If the VDD pins vary in potential by
even a small amount, noise and latchup can result. The VDD pins should
be kept to within 50 mV of each other.
All the GND pins should also be connected together as closely as
possible to the device with a large ground plane. If the GND pins vary in
potential by even a small amount, noise and latchup can result. The VDD
pins should be kept to within 50 mV of each other.
A 0.01–0.1 Fdecoupling capacitor should be connected between each
VDD/GND set as closely as possible to the device pins, preferably within
0.5 inches. The value should be chosen based on whether the noise
from VDD-GND is high- or low-frequency. A conservative approach would
be to use two decoupling capacitors on each VDD/GND set, one 0.1 ffor
low-frequency and one 0.001 ffor high-frequency noise on the power
supply.
The VDD connection to the transmit transformer center tap shown in
Figure A.1 through Figure A.3 has to be well decoupled to minimize
common mode noise injection from the supply into the twisted-pair cable.
It is recommended that a 0.01 Fdecoupling capacitor be placed between
the center tap VDD and the GND plane. This decoupling capacitor should
be physically placed as close as possible to the transformer center tap,
preferably within 0.5"
The PCB layout and power supply decoupling discussed above should
provide sufficient decoupling to achieve the following when measured at
the device:
A-24
•
The resultant AC noise voltage measured across each VDD/GND set
should be less than 100 mV p-p
•
All VDD pins should be within 50 mV p-p of each other
•
All GND pins should be within 50 mV p-p of each other.
Application Information
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
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Copyright © 2000 by LSI Logic Corporation. All rights reserved.
Draft 6/5/00
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Rev. letter
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
U.S. Distributors
by State
A. E.
Avnet Electronics
http://www.hh.avnet.com
B. M.
Bell Microproducts,
Inc. (for HAB’s)
http://www.bellmicro.com
I. E.
Insight Electronics
http://www.insight-electronics.com
W. E.
Wyle Electronics
http://www.wyle.com
Alabama
Daphne
I. E.
Tel: 334.626.6190
Huntsville
A. E.
Tel: 256.837.8700
B. M.
Tel: 256.705.3559
I. E.
Tel: 256.830.1222
W. E. Tel: 800.964.9953
Alaska
A. E.
Tel: 800.332.8638
Arizona
Phoenix
A. E.
Tel: 480.736.7000
B. M.
Tel: 602.267.9551
W. E. Tel: 800.528.4040
Tempe
I. E.
Tel: 480.829.1800
Tucson
A. E.
Tel: 520.742.0515
Arkansas
W. E. Tel: 972.235.9953
California
Agoura Hills
B. M.
Tel: 818.865.0266
Granite Bay
B. M.
Tel: 916.523.7047
Irvine
A. E.
Tel: 949.789.4100
B. M.
Tel: 949.470.2900
I. E.
Tel: 949.727.3291
W. E. Tel: 800.626.9953
Los Angeles
A. E.
Tel: 818.594.0404
W. E. Tel: 800.288.9953
Sacramento
A. E.
Tel: 916.632.4500
W. E. Tel: 800.627.9953
San Diego
A. E.
Tel: 858.385.7500
B. M.
Tel: 858.597.3010
I. E.
Tel: 800.677.6011
W. E. Tel: 800.829.9953
San Jose
A. E.
Tel: 408.435.3500
B. M.
Tel: 408.436.0881
I. E.
Tel: 408.952.7000
Santa Clara
W. E. Tel: 800.866.9953
Woodland Hills
A. E.
Tel: 818.594.0404
Westlake Village
I. E.
Tel: 818.707.2101
Colorado
Denver
A. E.
Tel: 303.790.1662
B. M.
Tel: 303.846.3065
W. E. Tel: 800.933.9953
Englewood
I. E.
Tel: 303.649.1800
Idaho Springs
B. M.
Tel: 303.567.0703
Illinois
North/South
A. E.
Tel: 847.797.7300
Tel: 314.291.5350
Chicago
B. M.
Tel: 847.413.8530
W. E. Tel: 800.853.9953
Schaumburg
I. E.
Tel: 847.885.9700
Connecticut
Cheshire
A. E.
Tel: 203.271.5700
I. E.
Tel: 203.272.5843
Wallingford
W. E. Tel: 800.605.9953
Indiana
Fort Wayne
I. E.
Tel: 219.436.4250
W. E. Tel: 888.358.9953
Indianapolis
A. E.
Tel: 317.575.3500
Delaware
North/South
A. E.
Tel: 800.526.4812
Tel: 800.638.5988
B. M.
Tel: 302.328.8968
W. E. Tel: 856.439.9110
Iowa
W. E. Tel: 612.853.2280
Cedar Rapids
A. E.
Tel: 319.393.0033
Florida
Altamonte Springs
B. M.
Tel: 407.682.1199
I. E.
Tel: 407.834.6310
Boca Raton
I. E.
Tel: 561.997.2540
Bonita Springs
B. M.
Tel: 941.498.6011
Clearwater
I. E.
Tel: 727.524.8850
Fort Lauderdale
A. E.
Tel: 954.484.5482
W. E. Tel: 800.568.9953
Miami
B. M.
Tel: 305.477.6406
Orlando
A. E.
Tel: 407.657.3300
W. E. Tel: 407.740.7450
Tampa
W. E. Tel: 800.395.9953
St. Petersburg
A. E.
Tel: 727.507.5000
Georgia
Atlanta
A. E.
Tel: 770.623.4400
B. M.
Tel: 770.980.4922
W. E. Tel: 800.876.9953
Duluth
I. E.
Tel: 678.584.0812
Hawaii
A. E.
Tel: 800.851.2282
Idaho
A. E.
W. E.
Tel: 801.365.3800
Tel: 801.974.9953
Kansas
W. E. Tel: 303.457.9953
Kansas City
A. E.
Tel: 913.663.7900
Lenexa
I. E.
Tel: 913.492.0408
Kentucky
W. E. Tel: 937.436.9953
Central/Northern/ Western
A. E.
Tel: 800.984.9503
Tel: 800.767.0329
Tel: 800.829.0146
Louisiana
W. E. Tel: 713.854.9953
North/South
A. E.
Tel: 800.231.0253
Tel: 800.231.5775
Maine
A. E.
W. E.
Tel: 800.272.9255
Tel: 781.271.9953
Maryland
Baltimore
A. E.
Tel: 410.720.3400
W. E. Tel: 800.863.9953
Columbia
B. M.
Tel: 800.673.7461
I. E.
Tel: 410.381.3131
Massachusetts
Boston
A. E.
Tel: 978.532.9808
W. E. Tel: 800.444.9953
Burlington
I. E.
Tel: 781.270.9400
Marlborough
B. M.
Tel: 800.673.7459
Woburn
B. M.
Tel: 800.552.4305
Michigan
Brighton
I. E.
Tel: 810.229.7710
Detroit
A. E.
Tel: 734.416.5800
W. E. Tel: 888.318.9953
Clarkston
B. M.
Tel: 877.922.9363
Minnesota
Champlin
B. M.
Tel: 800.557.2566
Eden Prairie
B. M.
Tel: 800.255.1469
Minneapolis
A. E.
Tel: 612.346.3000
W. E. Tel: 800.860.9953
St. Louis Park
I. E.
Tel: 612.525.9999
Mississippi
A. E.
Tel: 800.633.2918
W. E. Tel: 256.830.1119
Missouri
W. E. Tel: 630.620.0969
St. Louis
A. E.
Tel: 314.291.5350
I. E.
Tel: 314.872.2182
Montana
A. E.
Tel: 800.526.1741
W. E. Tel: 801.974.9953
Nebraska
A. E.
Tel: 800.332.4375
W. E. Tel: 303.457.9953
Nevada
Las Vegas
A. E.
Tel: 800.528.8471
W. E. Tel: 702.765.7117
New Hampshire
A. E.
Tel: 800.272.9255
W. E. Tel: 781.271.9953
New Jersey
North/South
A. E.
Tel: 201.515.1641
Tel: 609.222.6400
Mt. Laurel
I. E.
Tel: 856.222.9566
Pine Brook
B. M.
Tel: 973.244.9668
W. E. Tel: 800.862.9953
Parsippany
I. E.
Tel: 973.299.4425
Wayne
W. E. Tel: 973.237.9010
New Mexico
W. E. Tel: 480.804.7000
Albuquerque
A. E.
Tel: 505.293.5119
U.S. Distributors
by State
(Continued)
New York
Hauppauge
I. E.
Tel: 516.761.0960
Long Island
A. E.
Tel: 516.434.7400
W. E. Tel: 800.861.9953
Rochester
A. E.
Tel: 716.475.9130
I. E.
Tel: 716.242.7790
W. E. Tel: 800.319.9953
Smithtown
B. M.
Tel: 800.543.2008
Syracuse
A. E.
Tel: 315.449.4927
North Carolina
Raleigh
A. E.
Tel: 919.859.9159
I. E.
Tel: 919.873.9922
W. E. Tel: 800.560.9953
North Dakota
A. E.
Tel: 800.829.0116
W. E. Tel: 612.853.2280
Ohio
Cleveland
A. E.
Tel: 216.498.1100
W. E. Tel: 800.763.9953
Dayton
A. E.
Tel: 614.888.3313
I. E.
Tel: 937.253.7501
W. E. Tel: 800.575.9953
Strongsville
B. M.
Tel: 440.238.0404
Valley View
I. E.
Tel: 216.520.4333
Oklahoma
W. E. Tel: 972.235.9953
Tulsa
A. E.
Tel: 918.459.6000
I. E.
Tel: 918.665.4664
Oregon
Beaverton
B. M.
Tel: 503.524.1075
I. E.
Tel: 503.644.3300
Portland
A. E.
Tel: 503.526.6200
W. E. Tel: 800.879.9953
Pennsylvania
Mercer
I. E.
Tel: 412.662.2707
Philadelphia
A. E.
Tel: 800.526.4812
B. M.
Tel: 877.351.2355
W. E. Tel: 800.871.9953
Pittsburgh
A. E.
Tel: 412.281.4150
W. E. Tel: 440.248.9996
Rhode Island
A. E.
800.272.9255
W. E. Tel: 781.271.9953
South Carolina
A. E.
Tel: 919.872.0712
W. E. Tel: 919.469.1502
South Dakota
A. E.
Tel: 800.829.0116
W. E. Tel: 612.853.2280
Tennessee
W. E. Tel: 256.830.1119
East/West
A. E.
Tel: 800.241.8182
Tel: 800.633.2918
Texas
Arlington
B. M.
Tel: 817.417.5993
Austin
A. E.
Tel: 512.219.3700
B. M.
Tel: 512.258.0725
I. E.
Tel: 512.719.3090
W. E. Tel: 800.365.9953
Dallas
A. E.
Tel: 214.553.4300
B. M.
Tel: 972.783.4191
W. E. Tel: 800.955.9953
El Paso
A. E.
Tel: 800.526.9238
Houston
A. E.
Tel: 713.781.6100
B. M.
Tel: 713.917.0663
W. E. Tel: 800.888.9953
Richardson
I. E.
Tel: 972.783.0800
Rio Grande Valley
A. E.
Tel: 210.412.2047
Stafford
I. E.
Tel: 281.277.8200
Utah
Centerville
B. M.
Tel: 801.295.3900
Murray
I. E.
Tel: 801.288.9001
Salt Lake City
A. E.
Tel: 801.365.3800
W. E. Tel: 800.477.9953
Vermont
A. E.
Tel: 800.272.9255
W. E. Tel: 716.334.5970
Virginia
A. E.
Tel: 800.638.5988
W. E. Tel: 301.604.8488
Haymarket
B. M.
Tel: 703.754.3399
Springfield
B. M.
Tel: 703.644.9045
Washington
Kirkland
I. E.
Tel: 425.820.8100
Maple Valley
B. M.
Tel: 206.223.0080
Seattle
A. E.
Tel: 425.882.7000
W. E. Tel: 800.248.9953
West Virginia
A. E.
Tel: 800.638.5988
Wisconsin
Milwaukee
A. E.
Tel: 414.513.1500
W. E. Tel: 800.867.9953
Wauwatosa
I. E.
Tel: 414.258.5338
Wyoming
A. E.
Tel: 800.332.9326
W. E. Tel: 801.974.9953
Sales Offices and Design
Resource Centers
LSI Logic Corporation
Corporate Headquarters
1551 McCarthy Blvd
Milpitas CA 95035
Tel: 408.433.8000
Fax: 408.433.8989
Fort Collins
2001 Danfield Court
Fort Collins, CO 80525
Tel: 970.223.5100
Fax: 970.206.5549
New Jersey
Red Bank
125 Half Mile Road
Suite 200
Red Bank, NJ 07701
Tel: 732.933.2656
Fax: 732.933.2643
NORTH AMERICA
Florida
Boca Raton
Cherry Hill - Mint Technology
California
Irvine
2255 Glades Road
Suite 324A
Boca Raton, FL 33431
Tel: 561.989.3236
Fax: 561.989.3237
Tel: 856.489.5530
Fax: 856.489.5531
Georgia
Alpharetta
New York
Fairport
2475 North Winds Parkway
Suite 200
Alpharetta, GA 30004
550 Willowbrook Office Park
Fairport, NY 14450
18301 Von Karman Ave
Suite 900
Irvine, CA 92612
♦ Tel: 949.809.4600
Fax: 949.809.4444
Pleasanton Design Center
5050 Hopyard Road, 3rd Floor
Suite 300
Pleasanton, CA 94588
Tel: 925.730.8800
Fax: 925.730.8700
Tel: 770.753.6146
Fax: 770.753.6147
Illinois
Oakbrook Terrace
215 Longstone Drive
Cherry Hill, NJ 08003
Tel: 716.218.0020
Fax: 716.218.9010
North Carolina
Raleigh
Phase II
4601 Six Forks Road
Suite 528
Raleigh, NC 27609
Tel: 630.954.2234
Fax: 630.954.2235
Tel: 919.785.4520
Fax: 919.783.8909
Kentucky
Bowling Green
Oregon
Beaverton
1551 McCarthy Blvd
Sales Office
M/S C-500
Milpitas, CA 95035
1262 Chestnut Street
Bowling Green, KY 42101
15455 NW Greenbrier Parkway
Suite 235
Beaverton, OR 97006
Fax: 408.954.3353
Maryland
Bethesda
7585 Ronson Road
Suite 100
San Diego, CA 92111
Tel: 858.467.6981
Fax: 858.496.0548
Silicon Valley
♦ Tel: 408.433.8000
Design Center
M/S C-410
Tel: 408.433.8000
Fax: 408.433.7695
Wireless Design Center
11452 El Camino Real
Suite 210
San Diego, CA 92130
Tel: 858.350.5560
Fax: 858.350.0171
Colorado
Boulder
4940 Pearl East Circle
Suite 201
Boulder, CO 80301
♦ Tel: 303.447.3800
Fax: 303.541.0641
Colorado Springs
Tel: 270.793.0010
Fax: 270.793.0040
6903 Rockledge Drive
Suite 230
Bethesda, MD 20817
Tel: 301.897.5800
Fax: 301.897.8389
Massachusetts
Waltham
200 West Street
Waltham, MA 02451
♦ Tel: 781.890.0180
Fax: 781.890.6158
Tel: 503.645.0589
Fax: 503.645.6612
Texas
Austin
9020 Capital of TX Highway North
Building 1
Suite 150
Austin, TX 78759
Tel: 512.388.7294
Fax: 512.388.4171
Plano
500 North Central Expressway
Suite 440
Plano, TX 75074
♦ Tel: 972.244.5000
Burlington - Mint Technology
Fax: 972.244.5001
77 South Bedford Street
Burlington, MA 01803
Houston
Tel: 781.685.3800
Fax: 781.685.3801
20405 State Highway 249
Suite 450
Houston, TX 77070
4420 Arrowswest Drive
Colorado Springs, CO 80907
Minnesota
Minneapolis
Tel: 719.533.7000
Fax: 719.533.7020
8300 Norman Center Drive
Suite 730
Minneapolis, MN 55437
♦ Tel: 612.921.8300
Fax: 612.921.8399
260 Hearst Way
Suite 400
Kanata, ON K2L 3H1
♦ Tel: 613.592.1263
Fax: 613.592.3253
Two Mid American Plaza
Suite 800
Oakbrook Terrace, IL 60181
San Diego
Canada
Ontario
Ottawa
Tel: 281.379.7800
Fax: 281.379.7818
INTERNATIONAL
France
Paris
LSI Logic S.A.
Immeuble Europa
53 bis Avenue de l'Europe
B.P. 139
78148 Velizy-Villacoublay
Cedex, Paris
♦ Tel: 33.1.34.63.13.13
Fax: 33.1.34.63.13.19
Germany
Munich
LSI Logic GmbH
Orleansstrasse 4
81669 Munich
♦ Tel: 49.89.4.58.33.0
Fax: 49.89.4.58.33.108
Stuttgart
Mittlerer Pfad 4
D-70499 Stuttgart
♦ Tel: 49.711.13.96.90
Fax: 49.711.86.61.428
Italy
Milan
LSI Logic S.P.A.
Centro Direzionale Colleoni Palazzo
Orione Ingresso 1
20041 Agrate Brianza, Milano
♦ Tel: 39.039.687371
Fax: 39.039.6057867
Japan
Tokyo
LSI Logic K.K.
Rivage-Shinagawa Bldg. 14F
4-1-8 Kounan
Minato-ku, Tokyo 108-0075
♦ Tel: 81.3.5463.7821
Fax: 81.3.5463.7820
Osaka
Crystal Tower 14F
1-2-27 Shiromi
Chuo-ku, Osaka 540-6014
♦ Tel: 81.6.947.5281
Fax: 81.6.947.5287
Sales Offices and Design
Resource Centers
(Continued)
Korea
Seoul
LSI Logic Corporation of
Korea Ltd
10th Fl., Haesung 1 Bldg.
942, Daechi-dong,
Kangnam-ku, Seoul, 135-283
Tel: 82.2.528.3400
Fax: 82.2.528.2250
The Netherlands
Eindhoven
LSI Logic Europe Ltd
World Trade Center Eindhoven
Building ‘Rijder’
Bogert 26
5612 LZ Eindhoven
Tel: 31.40.265.3580
Fax: 31.40.296.2109
Singapore
Singapore
LSI Logic Pte Ltd
7 Temasek Boulevard
#28-02 Suntec Tower One
Singapore 038987
Tel: 65.334.9061
Fax: 65.334.4749
Sweden
Stockholm
LSI Logic AB
Finlandsgatan 14
164 74 Kista
♦ Tel: 46.8.444.15.00
Fax: 46.8.750.66.47
Taiwan
Taipei
LSI Logic Asia, Inc.
Taiwan Branch
10/F 156 Min Sheng E. Road
Section 3
Taipei, Taiwan R.O.C.
Tel: 886.2.2718.7828
Fax: 886.2.2718.8869
United Kingdom
Bracknell
LSI Logic Europe Ltd
Greenwood House
London Road
Bracknell, Berkshire RG12 2UB
♦ Tel: 44.1344.426544
Fax: 44.1344.481039
♦ Sales Offices with
Design Resource Centers
International Distributors
Australia
New South Wales
Reptechnic Pty Ltd
Hong Kong
Hong Kong
AVT Industrial Ltd
3/36 Bydown Street
Neutral Bay, NSW 2089
Unit 608 Tower 1
Cheung Sha Wan Plaza
833 Cheung Sha Wan Road
Kowloon, Hong Kong
♦ Tel: 612.9953.9844
Fax: 612.9953.9683
Belgium
Acal nv/sa
Lozenberg 4
1932 Zaventem
Tel: 32.2.7205983
Fax: 32.2.7251014
China
Beijing
LSI Logic International
Services Inc.
Beijing Representative
Office
Room 708
Canway Building
66 Nan Li Shi Lu
Xicheng District
Beijing 100045, China
Tel: 86.10.6804.2534 to 38
Fax: 86.10.6804.2521
France
Rungis Cedex
Azzurri Technology France
22 Rue Saarinen
Sillic 274
94578 Rungis Cedex
Tel: 33.1.41806310
Fax: 33.1.41730340
Germany
Haar
EBV Elektronik
Tel: 852.2428.0008
Fax: 852.2401.2105
Serial System (HK) Ltd
2301 Nanyang Plaza
57 Hung To Road, Kwun Tong
Kowloon, Hong Kong
Tel: 852.2995.7538
Fax: 852.2950.0386
India
Bangalore
Spike Technologies India
Private Ltd
951, Vijayalakshmi Complex,
2nd Floor, 24th Main,
J P Nagar II Phase,
Bangalore, India 560078
♦ Tel: 91.80.664.5530
Fax: 91.80.664.9748
Macnica Corporation
Tel: 44.1628.826826
Fax: 44.1628.829730
Hakusan High-Tech Park
1-22-2 Hadusan, Midori-Ku,
Yokohama-City, 226-8505
Milton Keynes
Ingram Micro (UK) Ltd
Tel: 81.45.939.6140
Fax: 81.45.939.6141
The Netherlands
Eindhoven
Acal Nederland b.v.
Japan
Tokyo
Daito Electron
Tel: 49.89.4600980
Fax: 49.89.46009840
Munich
Avnet Emg GmbH
Global Electronics
Corporation
Stahlgruberring 12
81829 Munich
Nichibei Time24 Bldg. 35 Tansu-cho
Shinjuku-ku, Tokyo 162-0833
Tel: 49.89.45110102
Fax: 49.89.42.27.75
Tel: 81.3.3260.1411
Fax: 81.3.3260.7100
Technical Center
Tel: 81.471.43.8200
Tel: 81.3.5778.8662
Fax: 81.3.5778.8669
Shinki Electronics
Myuru Daikanyama 3F
3-7-3 Ebisu Minami
Shibuya-ku, Tokyo 150-0022
Tel: 81.3.3760.3110
Fax: 81.3.3760.3101
Tel: 44.1908.260422
Swindon
EBV Elektronik
Tel: 31.40.2.502602
Fax: 31.40.2.510255
12 Interface Business Park
Bincknoll Lane
Wootton Bassett,
Swindon, Wiltshire SN4 8SY
Switzerland
Brugg
LSI Logic Sulzer AG
Mattenstrasse 6a
CH 2555 Brugg
14F, No. 145,
Sec. 2, Chien Kuo N. Road
Taipei, Taiwan, R.O.C.
Tel: 886.2.2516.7303
Fax: 886.2.2505.7391
Lumax International
Corporation, Ltd
7th Fl., 52, Sec. 3
Nan-Kang Road
Taipei, Taiwan, R.O.C.
Tel: 886.2.2788.3656
Fax: 886.2.2788.3568
Prospect Technology
Corporation, Ltd
4Fl., No. 34, Chu Luen Street
Taipei, Taiwan, R.O.C.
Tel: 886.2.2721.9533
Fax: 886.2.2773.3756
Marubeni Solutions
1-26-20 Higashi
Shibuya-ku, Tokyo 150-0001
Garamonde Drive
Wymbush
Milton Keynes
Buckinghamshire MK8 8DF
Beatrix de Rijkweg 8
5657 EG Eindhoven
Taiwan
Taipei
Avnet-Mercuries
Corporation, Ltd
Tel: 81.3.3264.0326
Fax: 81.3.3261.3984
Tel: 49.2957.79.1692
Fax: 49.2957.79.9341
16 Grove Park Business Estate
Waltham Road
White Waltham
Maidenhead, Berkshire SL6 3LW
11 Rozanis Street
P.O. Box 39300
Tel Aviv 61392
Tel: 972.3.6458777
Fax: 972.3.6458666
United Kingdom
Maidenhead
Azzurri Technology Ltd
Tel: 81.45.474.9037
Fax: 81.45.474.9065
Tel: 41.32.3743232
Fax: 41.32.3743233
Sogo Kojimachi No.3 Bldg
1-6 Kojimachi
Chiyoda-ku, Tokyo 102-8730
Graf-Zepplin-Str 14
D-33181 Wuennenberg-Haaren
2-15-10 Shin Yokohama
Kohoku-ku
Yokohama-City, 222-8580
Israel
Tel Aviv
Eastronics Ltd
Hans-Pinsel Str. 4
D-85540 Haar
Wuennenberg-Haaren
Peacock AG
Yokohama-City
Innotech
Wintech Microeletronics
Co., Ltd
7F., No. 34, Sec. 3, Pateh Road
Taipei, Taiwan, R.O.C.
Tel: 886.2.2579.5858
Fax: 886.2.2570.3123
Tel: 44.1793.849933
Fax: 44.1793.859555
♦ Sales Offices with
Design Resource Centers