CY292510 200-MHz, Ten-output Zero Delay Buffer/PLL Features Description • • • • • • • • Output frequency range: 25 MHz to 200 MHz 10 LVCMOS outputs One feedback output Output-to-output skew < 100 ps Cycle-to cycle jitter < 100 ps ± 125-ps static phase error: 66 MHz to 166 MHz Spread-Spectrum-compatible Integrated series damping resistors specifically designed for registered SDRAM DIMM applications – JEDEC-JC42.5-compliant • Externally controllable output delay • Output enable/disable control • 24-pin TSSOP package The CY292510 is a 3.3V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. It is ideal for use in SDRAM memory applications, and conforms to the JEDEC JC40/JC42.5 specification supporting SDRAM DIMM applications. The CY292510 has one bank of outputs with output enable control. Input-to-output skew can be adjusted by varying load/delay on feedback path. When OE is low, clock outputs are forced low. VDDA can be strapped low to force device into test mode. See Table 4. Table 1. Function Table[1] FBOUT 1Y0 1Y1 VDDA 1Y(0:9) Outputs FBOUT LOW REF HIGH REF REF Pin Configuration Block Diagram FBIN REF OE LOW 1Y2 1Y3 PLL 1 MUX 0 SEL 1Y4 1Y5 1Y6 1Y7 1Y8 1Y9 VSSA VDD 1Y0 1Y1 1Y2 VSS VSS 1Y3 1Y4 VDD OE FBOUT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 REF VDDA VDD 1Y9 1Y8 VSS VSS 1Y7 1Y6 1Y5 VDD FBIN OE Note: 1. See Table 4 for additional logic configurations. REF is fixed frequency input. Cypress Semiconductor Corporation Document #: 38-07472 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised October 11, 2002 CY292510 Pin Description Pin Name I/O Description 24 REF I Input reference pin. 12 FBOUT O Feedback Output. Not affected by the OE pin. 13 FBIN I This pin is to be connected to the FBOUT pin. A timing delay may be inserted to change the delay through the device. 11 OE I Output Enable clock (high active). OE low places CLK(0:9) into low state. See Block Diagram. 2, 10, 14, 22 VDD PWR 3.3V supply for core logic, inputs and outputs. 23 VDDA PWR Power for internal analog circuitry. This supply should have separate de coupling. For test purposes, when VDDA is strapped to ground the internal PLL is shut off and bypassed and REF is buffered directly to device outputs( see Table 4). 3, 4, 5, 8, 9, 15, 1Y(0:9) 16, 17, 20, 21 O Low skew clock outputs. Outputs enabled by OE in high state. 6, 7, 18, 19 VSS PWR Ground pins for the core logic and I/Os. 1 VSSA PWR Ground pin for analog circuitry. Table 2. Absolute Maximum Ratings[2] Parameter VDD, VDDA VI [3] VO[3] Description Commercial Unit Supply Voltage Range –0.5 to +4.6 V Input Voltage Range –0.5 to VDD + 0.5 V Voltage range applied to any output in the high or low state –0.5 to VDD+0.5 V IIK (VI<0) Input clamp current –50 mA IOK (VO<0 or VO>VDD Terminal voltage with respect to VSS (inputs VIH2.5, VIL2.5 ±50 mA IO (VO = 0 to VDD) Continuous Output Current ±50 mA VDD or VSS Continuous Current ±100 mA TA = 50°C (in still air)[4] Maximum power dissipation Storage Temperature Range TSTG 0.7 W –65°C to +150°C °C Table 3. Capacitance[5] Min. Typ. Max. Unit CIN Parameter Input Capacitance VIN = VDD or VSS Description – 5 – pF CO Output Capacitance VO = VDD or VSS – 6 – pF Table 4. Test Mode Table (VDDA = 0V) INPUTS OE OUTPUTS REF 1Y(0:9) FBOUT LOW LOW LOW LOW LOW HIGH LOW HIGH HIGH LOW LOW LOW HIGH HIGH HIGH HIGH Notes: 2. Stresses beyond those listed under “ absolute maximum ratings” may cause permanent damage to the device. These are stresses rating only and functional operation of the device at these or any other conditions beyond those indicated under “ recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 4. The maximum package power dissipation is calculated using a junction temperature or 150°C and board trace length of 750 mils. 5. Unused inputs must be held high or low to prevent them from floating. Document #: 38-07472 Rev. ** Page 2 of 6 CY292510 Table 5. Recommended Operating Conditions Min. Typ. Max. Unit VDD Parameter Supply voltage Description 3.0 3.3 3.6 V VDDA Analog supply voltage 3.0 3.3 VIN Voltage applied to input pins 0 IOH High level output current – IOL Low level output current – TA Operating free-air temperature 0 3.6 V VDD V – –12 mA – 12 mA – 85 °C Table 6. DC Parameters (VDD = VDDA = 3.3V ±10%, TA = 0°C to +85°C) Parameter Description VIH HIGH Level input voltage VIL LOW level input voltage VOH HIGH level output voltage VOL LOW level output voltage IOH HIGH level output current IOL LOW level output current VIK Clamp voltage Test Conditions Max. IOH = –100 µA VDD–0.2 VDD = 3V IOH = –12 mA 2.1 VDD = 3V IOH = -6 mA 2.4 Min. to Max. IOL =100 µA 0.2 VDD = 3V IOL = 12 mA 0.8 VDD = 3V IOL= 6 mA VDD = 3.135V VO = 1V VDD = 3.3V VO = 1.65V VDD = 3.465V VO = 3.135V VDD = 3.135V VO = 1.95V VDD = 3.3V VO = 1.65V VDD = 3.465V VO = 0.4V VDD = 3V IIN = –18 mA Input leakage current per pin VDD = 3.6V PLL supply current Min. to Max. IDDQ Quiescent supply current VDD = 3.6V V 0.55 –32 mA –36 –12 34 mA 40 14 –1.2 VI = VDD or VSS 2.3 Outputs loaded at 133 MHz V ±5 µA 3.5 mA 5 mA 500 µA IO = 0 VIN = VDD or VSS VDD = 3.6V V V Change in quiescent current VDD = 3.3 V to 3.6V One input at VDD – 0.6V, other inputs at VDD or VSS Dynamic supply current Unit V 0.8 Min. to Max. II IDD Typ. 2.0 IDDA ∆IDDQ Min. 200 mA Table 7. AC Parameters (VDD = VDDA = 3.3V ±10%, TA = 0°C to +85°C) [6, 7, 8, 9, 10] VDD = 3.3V ± 0.3V Parameter Fin From Input/Condition To Output Reference Clock Duty Cycle Reference Clock Fout Output Operating Frequency Min. 25 Typ. Max. Unit 200 MHz % 40 60 30-pF load 25 185 25-pF load 25 200 –125 125 45 55 tPHASE error[11], static REF = 66 to 166 MHz offset (normalized) FBIN Duty Cycle Any clock out or FBOUT MHz pS % Notes: 6. Parameters are guaranteed by design and characterization and are not 100% production tested. 7. The tSK(0) specification is only valid for equal loading of all outputs (30 pF//500Ω) for Fout < 185 MHz and (25 pF//500Ω) for Fout > 185 MHz. 8. The test load is 30 pF//500Ω for Fout < 185 MHz and 25 pF//500Ω for Fout > 185 MHz. 9. See Figure 2. 10. OE = VDD. 11. Uses the averaging feature of the scope to remove the jitter component. Document #: 38-07472 Rev. ** Page 3 of 6 CY292510 Table 7. AC Parameters (VDD = VDDA = 3.3V ±10%, TA = 0°C to +85°C) (continued)[6, 7, 8, 9, 10] tsk(o)[6,7,9] Skew, Output to Output Any clock out Jitter(cycle-to-cycle) Any clock out or FBOUT tR[13] Any clock out or FBOUT 0.5 tF[13] Any clock out or FBOUT 0.5 tPD (propagation delay REF - bypass mode) Any clock out or FBOUT TSTABIL [12] FBOUT Stabilization time 100 pS 2.2 nS 2.2 nS 75 pS 3 ns 1 mS Parameter Measurement Information From Output Under Test 30 pF 500 Ohm 2V Output 0.4 V 50% VDD tr Load Circuit for Outputs 25 pF load w hen Fout > 185 MHz VOH 2V 0.4 V VOL tf Output Rise/Fall Time Figure 1. Load Circuit and Voltage Waveforms[14, 15, 16] CLKIN FBIN tphase error FBOUT Any Y tsk(o) Any Y Any Y tsk(o) Figure 2. Phase Error and Skew Calculations Notes: 12. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew and jitter parameters given in the switching characteristics table are not applicable. 13. tR/tF are measured at 0.4V to 2.0V. 14. CL includes probe and jig capacitance. 15. All input pulses are supplied by generators having the following characteristics: input frequency ≤ 100 MHz, Zo = 50Ω, tr ≤ 1.2 ns, tf < 1.2 ns. 16. The outputs are measured one at a time with one transition per measurement. Document #: 38-07472 Rev. ** Page 4 of 6 CY292510 Ordering Information Part Number Package Type Production Flow CY292510ZC 24-pin TSSOP Commercial, 0°C to +85°C CY292510ZCT 24-pin TSSOP–Tape and Reel Commercial, 0°C to +85°C Package Drawing and Dimension 24-lead Thin Shrunk Small Outline Package (4.40-mm Body) Z24 51-85119-** All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07472 Rev. ** Page 5 of 6 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY292510 Document History Page Document Title: CY292510 200-MHz, Ten-output Zero Delay Buffer/PLL Document Number: 38-07472 Rev. ECN No. Issue Date Orig. of Change ** 118946 10/14/02 RGL Document #: 38-07472 Rev. ** Description of Change New Data Sheet Page 6 of 6