CY2302 Frequency Multiplier and Zero Delay Buffer Features Table 1. Configuration Options • 90ps typical jitter OUT2 FBIN • 200ps typical jitter OUT1 OUT1 0 0 2 X REF REF OUT1 1 0 4 X REF 2 X REF OUT1 0 1 REF REF/2 OUT1 1 1 8 X REF 4 X REF OUT2 0 0 4 X REF 2 X REF OUT2 1 0 8 X REF 4 X REF OUT2 0 1 2 X REF REF OUT2 1 1 16 X REF 8 X REF • 65ps typical output-to-output skew • 90ps typical propagation delay • Voltage range: 3.3V±5%, or 5V±10% • Output frequency range: 5MHz-133MHz • Two outputs • Configuration options allow various multiplications of the reference frequency—refer to Table 1 to determine the specific option which meets your multiplication needs FS0 FS1 OUT1 OUT2 • Available in 8-pin SOIC package Block Diagram Pin Configuration SOIC External feedback connection to OUT1 or OUT2, not both FBIN FS0 FS1 IN Reference Input ÷Q Phase Detector FBIN 1 8 OUT2 IN 2 7 VDD GND 3 6 OUT1 FS0 4 5 FS1 Charge Pump Loop Filter Output Buffer OUT1 Output Buffer OUT2 VCO ÷2 Cypress Semiconductor Corporation Document #: 38-07154 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised August 29, 2005 CY2302 Pin Definitions Pin No. Pin Type IN 2 I Reference Input: The output signals will be synchronized to this signal. FBIN 1 I Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to ensure proper functionality. If the trace between FBIN and the output pin being used for feedback is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the REF signal input (IN). OUT1 6 O Output 1: The frequency of the signal provided by this pin is determined by the feedback signal connected to FBIN, and the FS0:1 inputs (see Table 1). OUT2 8 O Output 2: The frequency of the signal provided by this pin is one-half of the frequency of OUT1. See Table 1. VDD 7 P Power Connections: Connect to 3.3V or 5V. This pin should be bypassed with a 0.1-µF decoupling capacitor. Use ferrite beads to help reduce noise for optimal jitter performance. GND 3 P Ground Connection: Connect all grounds to the common system ground plane. FS0:1 4, 5 I Function Select Inputs: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per Table 1. Pin Name Pin Description Overview sheet titled “How to Implement Zero Delay,” and “Inserting Other Devices in Feedback Path.” The CY2302 is a two-output zero delay buffer and frequency multiplier. It provides an external feedback path allowing maximum flexibility when implementing the Zero Delay feature. This is explained further in the sections of this data The CY2302 is a pin-compatible upgrade of the Cypress W42C70-01. The CY2302 addresses some application dependent problems experienced by users of the older device. CA Ferrite Bead G V+ 10 µF Power Supply Connection C8 G 0.01 µF FBIN IN GND FS0 OUT 2 1 8 7 2 3 OUTPUT 2 C9 = 0.1 µF G OUT 1 G 4 VDD 22Ω 6 5 22Ω OUTPUT 1 FS1 Figure 1. Schematic/Suggested Layout Document #: 38-07154 Rev. *A Page 2 of 7 CY2302 How to Implement Zero Delay Typically, Zero Delay Buffers (ZDBs) are used because a designer wants to provide multiple copies of a clock signal in phase with each other. The whole concept behind ZDBs is that the signals at the destination chips are all going HIGH at the same time as the input to the ZDB. In order to achieve this, layout must compensate for trace length between the ZDB and the target devices. The method of compensation is described below. External feedback is the trait that allows for this compensation. The PLL on the ZDB will cause the feedback signal to be in phase with the reference signal. When laying out the board, match the trace lengths between the output being used for feedback and the FBIN input to the PLL. If it is desirable to either add a little delay, or slightly precede the input signal, this may also be implemented by either making the trace to the FBIN pin a little shorter or a little longer than the traces to the devices being clocked. Inserting Other Devices in Feedback Path Another nice feature available due to the external feedback is the ability to synchronize signals to the signal coming from some other device. This implementation can be applied to any device (ASIC, multiple output clock buffer/driver, etc.) that is put into the feedback path. Referring to Figure 2, if the traces between the ASIC/Buffer and the destination of the clock signal(s) (A) are equal in length to the trace between the buffer and the FBIN pin, the signals Document #: 38-07154 Rev. *A at the destination(s) device will be driven HIGH at the same time the Reference clock provided to the ZDB goes HIGH. Synchronizing the other outputs of the ZDB to the outputs from the ASIC/Buffer is more complex however, as any propagation delay from the ZDB output to the ASIC/Buffer output must be accounted for. Reference Signal Zero Delay Buffer Feedback Input ASIC/ Buffer A Figure 2. Six Output Buffer in the Feedback Path Phase Alignment In cases where OUT1 (i.e., the higher frequency output) is connected to FBIN input pin the output OUT2 rising edges may be either 0 or 180° phase aligned to the IN input waveform (as set randomly when the input and/or power is supplied). If OUT2 is desired to be rising-edge aligned to the IN input’s rising edge, then connect the OUT2 (i.e., the lowest frequency output) to the FBIN pin. This set-up provides a consistent input-output phase relationship. Page 3 of 7 CY2302 Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condi- tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. . Parameter Description Rating Unit VDD, VIN Voltage on Any Pin with Respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TA Operating Temperature 0 to +70 °C TB Ambient Temperature under Bias –55 to +125 °C PD Power Dissipation 0.5 W DC Electrical Characteristics: TA = 0°C to 70°C or –40° to 85°C, VDD = 3.3V ±5% Parameter Description Min. Typ. Max. Unit — 17 35 mA Input Low Voltage — — 0.8 V VIH Input High Voltage 2.0 — IDD Supply Current VIL Test Condition Unloaded, 100 MHz V VOL Output Low Voltage IOL = 12 mA — — 0.4 V VOH Output High Voltage IOH = -12 mA 2.4 — — V IIL Input Low Current VIN = 0V –40 — 5 µA IIH Input High Current VIN = VDD — — 5 µA Min. Typ. Max. Unit — 37 50 mA 0.8 V DC Electrical Characteristics: TA = 0°C to 70°C or –40° to 85°C, VDD = 5V ±10% Parameter Description Test Condition IDD Supply Current Unloaded, 100 MHz VIL Input Low Voltage — — VIH Input High Voltage 2.0 — V VOL Output Low Voltage IOL = 12 mA — — VOH Output High Voltage IOH = -12 mA 2.4 — IIL Input Low Current VIN = 0V –80 — 5 µA IIH Input High Current VIN = VDD — 5 µA Document #: 38-07154 Rev. *A 0.4 V V Page 4 of 7 CY2302 AC Electrical Characteristics: TA = 0°C to +70°C or –40° to 85°C, VDD = 3.3V ±5%[3] Parameter Description Test Condition Min. Typ. Max. Unit 5 — 133 MHz fIN Input Frequency[1] fOUT Output Frequency OUT1 15-pF load 10 — 133 MHz tR Output Rise Time 0.8V to 2.0V, 15-pF load — — 3.5 ns tF Output Fall Time 2.0V to 0.8V, 15-pF load — — 2.5 ns tICLKR Input Clock Rise Time[2] — — 10 ns tICLKF Input Clock Fall Time[2] — — 10 ns 40 50 60 % [5] tD Duty Cycle 15-pF load tLOCK PLL Lock Time Power supply stable — — 1.0 ms tJC Jitter, Cycle-to-Cycle OUT1, fOUT >30 MHz — 200 300 ps OUT2, fOUT >30 MHz — 90 300 ps 100 — — Clock Cycles — 65 250 ps –350 90 350 ps tDC tSKEW tPD Die Out Time[6] Output-output Propagation Skew[4] Delay[4] AC Electrical Characteristics: TA = 0°C to +70°C or –40° to 85°C, VDD = 5.0V ±10%[3] Parameter Description Test Condition Min. Typ. Max. Unit 133 MHz fIN Input Frequency[1] fOUT Output Frequency OUT1 15-pF load 10 — 133 MHz tR Output Rise Time 0.8V to 2.0V, 15-pF load — — 2.5 ns tF Output Fall Time 2.0V to 0.8V, 15-pF load — — 1.5 ns tICLKR Input Clock Rise Time[2] — — 10 ns tICLKF Input Clock Fall Time[2] — — 10 ns tD Duty Cycle 15-pF load[5, 7] 40 50 60 % tLOCK PLL Lock Time Power supply stable — — 1.0 ms tJC Jitter, Cycle-to-Cycle OUT1, fOUT >30 MHz — 200 300 ps OUT2, fOUT >30 MHz — 90 300 ps 100 — — clock cycles — 65 250 ps –350 90 350 ps tDC Die out time[6] tSKEW Output-output Skew[4] tPD Propagation Delay[4] 5 Notes: 1. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration). 2. Longer input rise and fall time will degrade skew and jitter performance. 3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V. 4. Skew is measured at 1.4V on rising edges. 5. Duty cycle is measured at 1.4V. 6. 33 MHz reference input suddenly stopped (0 MHz). Number of cycles provided prior to output falling to <16 MHz. 7. Duty Cycle measured at 120 MHz. For 133 MHz, degrades to 35/65 worst case. Document #: 38-07154 Rev. *A Page 5 of 7 CY2302 Ordering Information Ordering Code Package Type Temperature Grade CY2302SC-1 8 pin SOIC Commercial CY2302SC-1T 8 pin SOIC - Tape and Reel Commercial CY2302SI-1 8 pin SOIC Industrial CY2302SI-1T 8 pin SOIC - Tape and Reel Industrial CY2302SXC-1 8 pin SOIC Commercial CY2302SXC-1T 8 pin SOIC - Tape and Reel Commercial CY2302SXI-1 8 pin SOIC Industrial CY2302SXI-1T 8 pin SOIC - Tape and Reel Industrial Lead-free Package Diagram 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07154 Rev. *A Page 6 of 7 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2302 Document History Page Document Title: CY2302 Frequency Multiplier and Zero Delay Buffer Document Number: 38-07154 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110264 12/18/01 SZV Change from Spec number: 38-00794 to 38-07154 *A 394695 See ECN RGL Added typical char data Added lead-free devices Added phase alignment paragraph Document #: 38-07154 Rev. *A Page 7 of 7