CY2V995 2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer Features • • • • • • • • • • • • • • Description 2.5V or 3.3V operation Split output bank power supplies Output frequency range: 6 MHz to 200 MHz Output-output skew: < 150 ps Cycle-cycle jitter: < 100 ps Selectable positive or negative edge synchronization 8 LVTTL outputs driving 50Ω terminated lines LVCMOS/LVTTL over-voltage tolerant reference input Selectable phase-locked loop (PLL) frequency range and lock indicator (1-6,8,10,12)x multiply and (1/2,1/4)x divide ratios Spread-Spectrum-compatible Power-down mode Industrial temperature range: –40°C to +85°C 44-pin TQFP package Block Diagram The CY2V995 is a low-voltage, low-power, eight output, 200-MHz clock driver. It features function necessary to optimize the timing of high-performance computer and communication systems. The user can program the frequency of the output banks through nF[0:1] and DS[0:1] pins. Any one of the outputs can be connected to feedback input to achieve different reference frequency multiplication and divide ratios and zero input-output delay. The device also features split output bank power supplies which enable the user to run two banks (1Qn and 2Qn) at a power supply level different from that of the other two banks (3Qn and 4Qn). Additionally, the PE pin controls the synchronization of the output signals to either the rising or the falling edge of the reference clock. Pin Configuration TEST PE FS VDDQ1 LOCK PLL 3 3 4F1 DS1:0 1Q0 1F1:0 1Q1 2Q0 2F1:0 3F1:0 2Q1 3Q0 3 3 /K sOE# PD# PE VDDQ4 VDDQ4 4Q1 4Q0 VSS VSS VSS 3Q1 VDDQ3 4F1:0 4Q0 3 3 /M 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2122 CY2V995 33 32 31 30 29 28 27 26 25 24 23 1F0 DS1 DS0 LOCK VDDQ1 VDDQ1 1Q0 1Q1 VSS VSS VSS VSS 3Q1 3Q0 VDDQ3 VDDQ3 FB VDD VDDQ1 2Q1 2Q0 VSS FB /N FS VDD REF VSS TEST 2F1 2F0 1F1 3 4F0 3 REF 3F1 3F0 PD# 4Q1 VDDQ4 sOE# Cypress Semiconductor Corporation Document #: 38-07435 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 19, 2004 CY2V995 Pin Description Pin I/O[1] Name 39 REF 17 FB 37 TEST 2 sOE# 4 PE I Type Description LVTTL/ LVCMOS Reference Clock Input. I LVTTL Feedback Input. I 3-Level When MID or HIGH, disables PLL (except for conditions of note 3). REF goes to all outputs. Set LOW for normal operation. I, PD LVTTL Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H or M) – 2Q0 and 2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE# is high, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set sOE# LOW for normal operation. I, PU LVTTL Selects Positive or Negative Edge Control and High or Low output drive strength. When LOW / HIGH the outputs are synchronized with the negative/positive edge of the reference clock, respectively. Please see Table 8. 34, 33, 36, 35, nF[1:0] 43, 42, 1, 44 I 3-Level Select frequency of the outputs. Please see Tables 3, 4, 5, and 7. 41 FS I 3-Level Selects VCO operating frequency range. Please see Table 6. 26,27,20,21, 13,14,7,8 nQ[1:0] O LVTTL Four banks of two outputs. Please see Table 5 for frequency settings. 32, 31 DS[1:0] I 3-Level Select feedback divider. Please see Table 1. 3 PD# I, PU LVTTL Power-down and reference divider control. When LOW, shuts off entire chip. Please see Table 2 for settings. 30 LOCK O LVTTL PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the input. 5,6 VDDQ4[2] PWR Power Power supply for Bank 4 output buffers. Please see Table 8 for supply level constraints 15,16 VDDQ3 [2] PWR Power Power supply for Bank 3 output buffers. Please see Table 8 for supply level constraints 19,28 VDDQ1[2] PWR Power Power supply for Bank 1 and Bank 2 output buffers. Please see Table 8 for supply level constraints 18,40 VDD[2] PWR Power Power supply for the internal circuitry. Please see Table 8 for supply level constraints PWR Power Ground 9-12, 22-25, 38 VSS Device Configuration The outputs of the CY2V995 can be configured to run at frequencies ranging from 6 MHz to 200 MHz. The feedback input divider is controlled by the 3-level DS[0:1] pins as indicated in Table 1. Table 1. Feedback Divider Settings DS[1:0] LL LM LH ML MM MH HL HM HH N-Feedback Input Divider 2 3 4 5 1 6 8 10 12 Permitted Output Divider Connected to FB[4] 1 or 2 1 1,2 or 4 1 or 2 1,2 or 4 1 or 2 1 or 2 1 1 Notes: 1. ‘PD’ indicates an internal pull-down and ‘PU’ indicates an internal pull-up. 2. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces. 3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless nF[1:0] = LL. 4. Permissible output division ratios connected to FB. The frequency of the REF input will be FNOM/N when the part is configured for frequency multiplication by using an undivided output for FB and setting DS[1:0] to N (N = 1-6, 8, 10, 12). Document #: 38-07435 Rev. *A Page 2 of 10 CY2V995 Table 2. Power-down Mode Table 6. Frequency Range Select PD# CY2V995 FS PLL Frequency Range H Enabled L 24 to 50 MHz L Power Down M 48 to 100 MHz H 96 to 200 MHz In addition to the feedback dividers, the CY2V995 includes output dividers on Bank3 and Bank4, which are controlled by 3F[1:0] and 4F[1:0] as indicated in Table 3 and 4, respectively. Table 3. Output Divider Settings – Bank 3 3F[1:0] K – Bank3 Output Divider LL[5] 2 The PE pin determines Whether the outputs synchronize to the rising or the falling edge of the reference signal, as indicated in Table 7. Table 7. PE Settings PE Synchronization HH 4 L Negative Other 1 H Positive Table 4. Output Divider Settings – Bank 4 4F[1:0] M – Bank4 Output Divider LL[5] 2 HH Inverted[6] Other 1 Table 8. Power Supply Constraints The divider settings, output frequencies, and possible configurations of connecting FB to ANY output are summarized in Table 5. Table 5. Output Frequency Settings Configuration FB Input Connected to 3Q[0:1] VDD VDDQ1[8] VDDQ3[8] VDDQ4[8] 3.3V 3.3V or 2.5V 3.3V or 2.5V 3.3V or 2.5V 2.5V 2.5V 2.5V 2.5V Governing Agencies Output Frequency 1Q[0:1] and 2Q[0:1][7] The CY2V995 features split power supply buses for Banks 1 and 2, Bank 3 and Bank 4, which enables the user to obtain both 3.3V and 2.5V output signals from one device. The core power supply (VDD) must be set a level which is equal or higher than that on any one of the output power supplies. 4Q[0:1] 1Qn or 2Qn N x FREF 3Qn N x K x FREF N x FREF 4Qn N x M x FREF N x (M / K) x N x FREF FREF N /x (1 / K) x N x (1 / M) x FREF FREF N x (K / M) x FREF The 3-level FS control pin setting determines the nominal operating frequency range of the divide-by-one outputs of the device. The CY2V995 PLL operating frequency range that corresponds to each FS level is given in Table 6. The following agencies provide specifications that apply to the CY2V995. The agency name and relevant specification is listed below. Agency Name Specification JEDEC JESD 51 (Theta JA) JESD 65 (Skew, Jitter) IEEE 1596.3 (Jiter Specs) UL-194_V0 94 (Moisture Grading) MIL 883E Method 1012.1 (Therma Theta JC) Notes: 5. LL disables outputs if TEST = MID and sOE# = HIGH. 6. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE = HIGH or MID, sOE# disables them LOW when PE = LOW. 7. These outputs are undivided copies of the VCO clock. Therefore, the formulas in this column can be used to calculate the VCO operating frequency (FNOM) at a given reference frequency (FREF) and divider and feedback configuration. The user must select a configuration and a reference frequency that will generate a VCO frequency that is within the range specified by FS pin. Please see Table 6. 8. VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g. VDD = 3.3V, VDDQ1 = 3.3V, VDDQ3 = 2.5V and VDDQ4 = 2.5V. Document #: 38-07435 Rev. *A Page 3 of 10 CY2V995 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Operating Voltage Functional @ 2.5V ± 5% 2.25 2.75 V VDD Operating Voltage Functional @ 3.3V ± 10% 2.97 3.63 V VIN(MIN) Input Voltage Relative to VSS VSS – 0.3 – V VIN(MAX) Input Voltage Relative to VDD – VDD + 0.3 V VREF(MAX) Reference Input Voltage VDD = 3.3V 5.5 V VREF(MAX) Reference Input Voltage VDD = 2.5V 4.6 V TS Temperature, Storage Non Functional –65 +150 °C TA Temperature, Operating Ambient Functional –40 +85 °C TJ Temperature, Junction Functional – 155 °C ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 42 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) 74 °C/W UL-94 Flammability Rating @1/8 in. MSL Moisture Sensitivity Level FIT Failure in Time V–0 1 Manufacturing Testing 10 ppm DC Specifications @ 2.5V Parameter Description Conditions VDD 2.5 Operating Voltage 2.5V ± 5% VIL Input LOW Voltage REF, FB, PE, PD#, and sOE# Inputs VIH Input HIGH Voltage VIHH[9] Input HIGH Voltage VIMM[9] Input MID Voltage VILL[9] Input LOW Voltage IIL Input Leakage Current I3 3-Level Input DC Current Min. Max. Unit 2.375 2.625 V – 0.7 V 1.7 – 3-Level Inputs VDD– – (TEST, FS, nF[1:0], DS[1:0]) –0.4 (These pins are normally wired to VDD,GND or uncon- V /2 – V /2 + DD DD nected) 0.2 0.2 VIN = VDD/GND,VDD = Max (REF and FB inputs) HIGH, VIN = VDD MID, VIN = VDD/2 3-Level Inputs (TEST, FS, nF[1:0], DS[1:0]) V V V – 0.4 V –5 5 µA – 200 µA –50 50 µA –200 – µA –25 – µA VIN = VDD, VDD = Max, (sOE#) – 100 µA IOL = 12mA, (nQ[0:1]) – 0.4 V LOW, VIN = VSS IPU Input Pull-up Current VIN = VSS, VDD = Max IPD Input Pull-down Current VOL Output LOW Voltage VOH Output HIGH Voltage IOL = 2mA (LOCK) 0.4 IOH = –12mA,(nQ[0:1]) 2.0 IOH = –2mA (LOCK) 2.0 IDDQ Quiescent Supply Current VDD = Max, TEST = MID, REF = LOW, sOE# = LOW, Outputs not loaded IDDPD Power-down Current PD#, sOE# = LOW Test,nF[1:0],DS[1:0] = HIGH VDD = Max IDD Dynamic Supply Current @100 MHz CIN Input Pin Capacitance – V V – 2 mA 10(typ.) 25 µA 150 mA 4 pF Note: 9. These Inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. Document #: 38-07435 Rev. *A Page 4 of 10 CY2V995 DC Specifications @ 3.3V Parameter Description Condition VDD 3.3 Operating Voltage 3.3V ± 10% VIL Input LOW Voltage REF, PE, PD#, FB and sOE# Inputs VIH Input HIGH Voltage VIHH[9] Input HIGH Voltage VIMM[9] Input MID Voltage VILL[9] Input LOW Voltage IIL Input Leakage Current I3 3-Level Input DC Current 3-Level Inputs (TEST, FS, nF[1:0], DS[1:0]) (These pins are normally wired to VDD,GND or unconected VIN = VDD/GND,VDD = Max (REF and FB inputs) HIGH, VIN = VDD MID, VIN = VDD/2 LOW, VIN = VSS IPU Input Pull-Up Current VIN = VSS, VDD = Max 3-Level Inputs (TEST, FS,nF[1:0], DS[1:0]) Min. Max. Unit 2.97 3.63 V – 0.8 V 2.0 – V VDD–-0.6 – V VDD/2–0.3 VDD/2+0.3 V – 0.6 V –5 5 µA – 200 µA –50 50 µA –200 – µA –25 – µA IPD Input Pull-Down Current VIN = VDD, VDD = Max, (sOE#) – 100 µA VOL Output LOW Voltage IOL = 12mA, (nQ[0:1]) – 0.4 V VOH Output HIGH Voltage IOH = –12mA,(nQ[0:1]) 2.4 IOH = –2mA (LOCK) 2.4 Quiescent Supply Current VDD = Max, TEST = MID, REF = LOW, sOE# = LOW, Outputs not loaded Power-down Current PD#, sOE# = LOW Test,nF[1:0],DS[1:0] = HIGH VDD = Max IDD Dynamic Supply Current @100 MHz CIN Input Pin Capacitance IOL = 2mA (LOCK) IDDQ IDDPD 0.4 – V – 2 mA 10(typ.) 25 µA 230 mA 4 pF AC Input Specifications Parameter Description Condition Min. Max. Unit TR,TF Input Rise/Fall Time 0.8V – 2.0V – 10 ns/V TPWC Input Clock Pulse HIGH or LOW 2 – ns TDCIN Input Duty Cycle FREF Reference Input Frequency FS = LOW 10 90 % 2 50 MHz FS = MID 4 100 FS = HIGH 8 200 Min. Max. Switching Characteristics Parameter Description FOR Output frequency range VCOLR VCO Lock Range VCOLBW VCO Loop Bandwidth tSKEWPR Matched-Pair Skew[10] Condition Skew between the earliest and the latest output transitions within the same bank. Unit 6 200 MHz 200 400 MHz 0.25 3.5 MHz – 150 ps Note: 10. Test Load = 20 pF, terminated to VCC/2. All outputs are equally loaded. Document #: 38-07435 Rev. *A Page 5 of 10 CY2V995 Switching Characteristics (continued) Parameter Condition Min. Max. Unit Skew between the earliest and the latest output transitions among all outputs. – 200 ps tSKEW1 Skew between the earliest and the latest output transitions among all same class outputs. – 200 ps tSKEW2 Skew between the nominal output rising edge to the inverted output falling edge – 500 ps tSKEW3 Skew between non-inverted outputs running at different frequencies – 500 ps tSKEW4 Skew between nominal to inverted outputs running at different frequencies – 500 ps tSKEW5 Skew between nominal outputs at different power supply levels – 650 ps Skew between the outputs of any two devices under identical settings and conditions (VDDQ,VDD,temp,air flow, frequency, etc) – 750 ps tSKEW0 Description Output-Output Skew[10] tPART Part-Part Skew tPD0 Ref to FB Propagation Delay[11] –250 +250 ps tODCV Output Duty Cycle Measured at VDD/2 45 55 % tPWH Output High Time Deviation from 50% Measured at 2.0V for VDD = 3.3V and at 1.7V for VDD = 2.5V. – 1.5 ns tPWL Output Low Time Deviation from 50% Measured at 0.8V for VDD = 3.3V and at 0.7V for VDD = 2.5V. – 2.0 ns tR/tF Output Rise/Fall Time Measured at 0.8V-2.0V for VDD = 3.3V and 0.7V–1.7V for VDD = 2.5V 0.15 1.5 ns tLOCK PLL lock time[12, 13] tCCJ Cycle-Cycle Jitter – 0.5 ms Divide by 1 output frequency, FS = L, FB = divide by any – 100 ps Divide by 1 output frequency, FS = M/H, FB = divide by any – 150 ps Notes: 11. tPD is measured at 1.5V for VDD = 3.3V and at 1.25V for VDD = 2.5V with REF rise/fall times of 0.5 ns between 0.8V–2.0V. 12. tLOCK is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits. 13. Lock detector circuit may be unreliable for input frequencies lower than 4MHz, or for input signals which contain significant jitter. Document #: 38-07435 Rev. *A Page 6 of 10 CY2V995 AC Timing Definitions tREF tPWL tPWH REF tPD t0DCV t0DCV FB tCCJ1-12 Q tSKEWPR tSKEW0,1 tSKEWPR tSKEW0,1 OTHER Q tSKEW1 tSKEW1 INVERTED Q tSKEW3 tSKEW3 tSKEW3 REF DIVIDED BY 2 tSKEW1,3,4 tSKEW1,3,4 REF DIVIDED BY 4 Document #: 38-07435 Rev. *A Page 7 of 10 CY2V995 AC Test Loads and Waveforms VDDQ Output 150Ω 20pF Output 20pF 150Ω For Lock Output For All Other Outputs Figure 1. tORISE tORISE tOFALL tPWH 2.0V tOFALL tPWH 1.7V VTH =1.25V VTH =1.5V tPWL 0.8V tPWL 0.7V 2.5V LVTTL OUTPUT WAVEFORM 3.3V LVTTL OUTPUT WAVEFORM Figure 2. ≤ 1ns ≤ 1ns ≤ 1ns ≤ 1ns 2.5V 3.0V 1.7V 2.0V VTH =1.25V VTH =1.5V 0.7V 0V 0.8V 0V 2.5V LVTTL INPUT TEST WAVEFORM 3.3V LVTTL INPUT TEST WAVEFORM Figure 3. Ordering Information Part Number Package Type Product Flow CY2V995AC 44 TQFP Commercial, 0° to 70°C CY2V995ACT 44 TQFP – Tape and Reel Commercial, 0° to 70°C CY2V995AI 44 TQFP Industrial,–40° to 85°C CY2V995AIT 44 TQFP – Tape and Reel Industrial,–40° to 85°C Document #: 38-07435 Rev. *A Page 8 of 10 CY2V995 Package Drawing and Dimensions 44-lead Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A44SB 51-85155-*A All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07435 Rev. *A Page 9 of 10 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2V995 Document History Page Document Title:CY2V995 2.5/3.3V 200-MHz Multi-output Zero Delay Buffer Document Number: 38-07435 REV. ECN No. Issue Date Orig. of Change ** 122627 01/13/03 RGL New Data Sheet *A 200501 See ECN RGL Changed Pin 5 from VDD to VDDQ4, Pin 16 from VDD to VDDQ3 and Pin 29 from VDD to VDDQ1 Document #: 38-07435 Rev. *A Description of Change Page 10 of 10