FastEdge™ Series CY2DP3120 PRELIMINARY 1:20 Differential Clock Buffer/Driver Features Description • Twenty ECL/PECL differential outputs • Two ECL-/PECL-/HSTL-compatible differential clock inputs • Hot-swappable/-insertable • 50-ps output-to-output skew • 500-ps device-to-device skew • Less than 10-ps intrinsic jitter • < 500-ps propagation delay (typical) • Operation from DC to 1.5 GHz • PECL mode supply range: VCC = 2.375V to 3.465V with VEE = 0V • ECL mode supply range: VEE = –2.375V to –3.465V with VCC = 0V • Industrial temperature range: –40°C to 85°C • 52-pin 1.4-mm TQFP package • Temperature compensation like 100K ECL The CY2DP3120 is a low-skew, low propagation delay 1-to-20 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz. The device is fully differential and features two reference input buffers. The CY2DP3120 may function not only as a differential clock buffer but also as a signal level translator and fanout distributing a single-ended signal to twenty ECL/PECL differential loads. An external bias pin, VBB, is provided for an ECL/PECL/HSTL single-ended or differential. In such an application, the VBB pin should be connected to either one of the CLKA# or CLKB# inputs and bypassed to VCC via a 0.01-µF capacitor. Traditionally, in ECL, it is used to provide the reference level to a receiving single ended input that might have a different self bias point. Since the CY2DP3120 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2DP3120 delivers consistent, guaranteed performance over differing platforms. Block Diagram VCCO Q5# Q5 Q4# Q4 Q3# Q3 Q2# Q2 7 33 Q9 CLKB# 8 32 Q9# VEE Q19# 9 31 Q10 10 30 Q10# Q19 11 29 Q11 Q18# 12 28 Q11# 3901 North First Street CY2DP3120 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 VCCO • Q1# Q8# CLKB Q18 Cypress Semiconductor Corporation Document #: 38-07514 Rev. *A Q1 34 • San Jose, CA 95134 VCCO Q12 VEE 6 Q12# VBB CLK_SEL Q8 VBB Q13 VEE 35 Q13# VEE 5 Q14 Q19 Q19# Q7# CLKA# Q14# 1 Q7 36 Q15 CLKB CLKB# Q6# 4 Q15# VCC Q6 CLKA Q16 VEE VEE CLK_SEL Q16# CLKA# VCC 52 51 50 49 48 47 46 45 44 43 42 41 40 39 1 38 2 37 3 Q17 0 VCCO Q17# Q0 Q0# VCC CLKA Q0# Q0 Pin Configuration • 408-943-2600 Revised April 16, 2003 PRELIMINARY FastEdge™ Series CY2DP3120 Pin Description Pin 4,5 Name I/O CLKA, CLKA# I,PD[1] Type Description ECL/PECL Default differential clock input pair I,PC 7,8 CLKB, CLKB# I,PD I,PC HSTL Alternate differential clock input pair 3 CLK_SEL I,PD ECL/PECL CLK – Mux select 52,50,48,46,44,42,39,3 Q[0-19] 7,35,33,31,29,26,24,22 ,20,18,16,13,11 O,OS ECL/PECL True output 51,49,47,45,43,41,38,3 Q#[0-19] 6,34,32,30,28,25,23,21 ,19,17,15,12,10 O,OS ECL/PECL Complement output 6 VBB[3] O Bias Reference voltage output for single-ended ECL or PECL operation 9 VEE[2] -PWR Power Power supply, negative connection 2 VCC +PWR Power Power supply, positive connection 1,14,27,40 VCCO +PWR Power Power supply, positive connection Governing Agencies The following agencies provide specifications that apply to the CY2DP3120. The agency name and relevant specification is listed below. Agency Name JEDEC Specification JESD 51 (Theta JA) JESD 8–2 (ECL) JESD 65–A (Skew,Jitter) JESD 8-6 (HSTL) IEEE 1596.3 (Jitter Specs) UL 94 (Moisture Grading) Mil–Spec 883E Method 1012.1 (Thermal Theta JC) Notes: 1. In the I/O column, the following notation is used: I = Input, O = Output, PD = Pull-down, PU = Pull-up, PC = Pull Center, O = Output, OS = Open Source, PWR = Power. 2. in ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND(0V). In PECL mode (positive power supply mode), VEE is connected to GND(0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are between VCC and VEE. 3. VBB is available for use for single ended bias mode when VCC is +3.3V. Document #: 38-07514 Rev. *A Page 2 of 11 FastEdge™ Series CY2DP3120 PRELIMINARY Absolute Maximum Conditions Parameter Description Condition Vcc Supply Voltage Non-functional Vcc Operating Voltage Functional VBB Output Reference Voltage Relative to VCC IBB Output Reference Current Relative to VBB VTT Output Termination Voltage VTT = 0V for VCC = 2.5V VIN Input Voltage Relative to VCC VOUT Output Voltage Relative to VCC Min. Max. Unit –0.3 3.6 VDC 2.5 – 5% 3.3 + 5% VDC VCC–1.525 Vcc–1.325 VDC 200 uA VCC–2 VDC –0.3 VCC+0.3 VDC –0.3 VCC+0.3 VDC LUI Latch-up Immunity Functional TS Temperature, Storage Non-functional –65 TA Temperature, Operating Ambient Functional –40 +85 °C TJ Temperature, Junction Functional 10 +110 °C ØJc Dissipation, Junction to Case Functional TBD °C/W ØJa Dissipation, Junction to Ambient Functional TBD °C/W ESDh ESD Protection (Human Body Model) 2000 V MSL Moisture Sensitivity Level TBD N.A. GATES Total Functional Gate Count Assembled Die 50 Ea. UL–94 Flammability Rating @1/8 in V–0 N.A. FIT Failure in Time Manufacturing Test TBD PPM 300 mA +150 °C PECL DC Electrical Specifications Parameter Description Max. Unit VCC–1.945 VCC–1.625 V Input Voltage, High Define VCC and Load Current VCC–1.165 VCC–0.880 V Input Current[4] VIN = VIL or VIN = VIH 200 uA VIL Input Voltage, Low VIH IIN Condition Min. Clock input pair CLKA, CLKA#,CLKB, CLKB# (PECL Differential Signals) VPP Differential Input Voltage[5] Differential Operation 0.1 1.3 V VCMR Differential Cross Point Voltage[6] Differential Operation 1.2 VCC V 200 uA IIN Input Current [4] VIN = VIL or VIN = VIH PECL Outputs Q0-Q19, (Q0-Q19)#(PECL Differential Signals) VOH Output High Voltage IOH = –30 mA[9], 50Ω Load VCC–1.145 VOL Output Low Voltage VCC = 3.3V ±5%VCC = 2.5V ±5% IOL = –5 ma[9],50Ω Load VCC–1.945 VCC –1.945 VCC–0.895 V VCC–1.695 VCC–1.695 V 1.9 V Clock Input Pair CLKA, CLKA#,CLKB, CLKB# (HSTL Differential Signals) VDIF Differential Input Voltage[7] VX Differential Cross Point IIN Input Current 0.4 Voltage[8] 0.68 Vin = Vx ± 0.2V 0.9 V 200 uA Notes: 4. Input have internal pullup / pulldown or biasing resistors which affect the input current. 5. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 6. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 7. VDIF (DC) is the amplitude of the differential HSTL input voltage swing required for device functionality. 8. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operations is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. 9. Equivalent to a termination of 50 Ω to VTT. Document #: 38-07514 Rev. *A Page 3 of 11 PRELIMINARY FastEdge™ Series CY2DP3120 PECL DC Electrical Specifications (continued) Parameter Description Condition Min. Max. Unit 130 mA VCC–1.325 V Supply Current and VBB IEE Maximum Quiescent Supply Current without Output Termination Current[10] VEE Pin VBB Output Reference Voltage IBB = 200 uA Ipup Internal Pull-up Current TBD TBD mA. Ipdwn Internal Pull-down Current TBD TBD mA. CIN Input Pin Capacitance COUT Output Pin Capacitance LIN Pin Inductance ZOUT Output Impedance VCC–1.525 TBD TBD pF Q0–Q19, (Q0–Q19)# TBD TBD pF TBD TBD nH Q0–Q19, (Q0–Q19)# TBD TBD Ω Condition Min. Max. Unit ECL DC Electrical Specifications Parameter Description VIL Input Voltage, Low –1.945 –1.625 V VIH Input Voltage, High –1.165 –0.880 V 200 uA IIN Input Current[11] VIN = VIL or VIN = VIH Clock input pair CLKA, CLKA#,CLKB, CLKB# (ECL Differential Signals) VPP Differential Input Voltage[12] Differential Operation 0.1 1.3 V VCMR Differential Cross Point Voltage[13] Differential Operation VEE+1.2 0 V 200 uA –1.145 –0.895 V –1.945 –1.945 –1.695 –1.695 V 130 mA –1.325 V IIN Input Current[11] VIN = VIL or VIN = VIH ECL Outputs Q0-Q19, (Q0-Q19)# (ECL Dfferential Signals) VOH VOL Output High Voltage Output Low Voltage VEE = –3.3V ±5% VEE = –2.5V ±5% IOH = –30 mA[14] IOL = –5 ma[14] Supply Current and VBB IEE Maximum Quiescent Supply Current without Output Termination Current[15] VEE Pin VBB Output Reference Voltage IBB = 200 uA –1.525 Notes: 10. ICC calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE or ICC = (number of differential output pairs used) x (VOH – VTT)/Rload + (VOL – VTT)/Rload +IEE. 11. Input have internal pull-up/pull-down or biasing resistors which affect the input current. 12. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 13. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 14. Equivalent to a termination of 50Ω to VTT. 15. ICC Calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE or ICC = (number of differential output pairs used) x (VOH – VTT)/Rload + (VOL – VTT)/Rload +IEE. Document #: 38-07514 Rev. *A Page 4 of 11 PRELIMINARY FastEdge™ Series CY2DP3120 AC Electrical Specifications Parameter Description Condition Min. Max. Unit Differential Operation 0.1 1.3 V VEE+1.2 Clock Input Pair CLKA, CLKA (PECL or ECL Differential Signals) VPP Differential Input Voltage[17] [18] VCMR Differential Cross Point Voltage Differential Operation FCLK Input Frequency[19] 50% Duty Cycle Standard Load TPD Propagation Delay CLKA or CLKB to Q0–Q9 Pair 660 MHz 50% Duty Cycle Standard Load Differential Operation 0 V 1,500 MHz 400 750 ps Clock Input Pair CLKB, CLKB (HSTL Differential Signals) VPP Differential Input Voltage[17] Differential Operation 0.1 1.3 V VCMR Differential Cross Point Voltage[18] Differential Operation VEE+1.2 0 V 1,500 MHz 750 ps [19] FCLK Input Frequency TPD Propagation Delay CLKA or CLKB to Q0–Q9 Pair 50% Duty Cycle Standard Load 660 MHz 50% Duty Cycle Standard Load Differential Operation 400 ECL/PECL Clock Outputs (Q0–19, Q#0–19) (Differential) Vo(P-P) Differential Output Voltage (Peak-to-Peak) Differential PRBS fo < 50 MHz fo < 0.8 GHz fo < 1.0 GHz tsk(O) Output-to-Output skew 660-MHz 50% Duty Cycle Standard Load Differential Operation 50 ps tsk(PP) Output-to-output skew (part-to-part) 660-MHz 50% Duty Cycle Standard Load Differential Operation 500 ps Tjitt(cc) Output cycle-to-cycle jitter (Intrinsic) 660-MHz 50% Duty Cycle Standard Load Differential Operation 10 ps r.m.s tsk(P) Output pulse skew[21] 660-MHz 50% Duty Cycle Standard Load Differential Operation TF, TF Output Rise/Fall time 660-MHz 50% Duty Cycle Differential 20% to 80% TTB Total Timing Budget 660-MHz 50% Duty Cycle Standard Load 0.45 0.4 0.375 V ps 0.3 ns ps Notes: 16. AC characteristics apply for parallel output termination of 50Ω to VTT. 17. VPP (AC) is the minimum differential ECL/PECL input swing required to maintain AC characteristics including tpd and device-to-device skew. 18. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR(AC) range and the input swing lies within the VPP(AC) specification. Violation of VCMR(AC) or VPP(AC) impacts the device propagation delay, device and part-to-part skew. 19. The CY2DP3120 is fully operation up to 1.5 GHz. 20. VX(AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX(AC) range and the input swing lies within the VDIF(AC) specification. Violation of VX(AC) or VDIF(AC) impacts the device propagation delay, device and part-to-part skew. 21. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |. Document #: 38-07514 Rev. *A Page 5 of 11 FastEdge™ Series CY2DP3120 PRELIMINARY Test Configurations Standard test load using a differential pulse generator and differential measurement instrument. VTT VTT R T = 50 ohm R T = 50 ohm 5" Pulse G enerator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm 5" DUT CY2DP3120 R T = 50 ohm R T = 50 ohm VTT VTT Figure 1. CY2DP3120 AC Test Reference Timing Definitions VCC VCC = 3.3V VCM R M ax = VCC VIH VPP VPP range 0.1V - 1.3V VCM R VIL VCM R M in = 1.2V VEE = 0.0V VEE Figure 2. PECL Waveform Definitions VCC V C C = 0 .0 V VCM R m ax = 0 V IH VPP VCMR V P P r a n g e = 0 .1 to 1 .3 V V IL V C M R m in V E E - 1 .2 V VEE V E E = -2 .5 V o r - 3 .3 V Figure 3. PECL Waveform Definitions Document #: 38-07514 Rev. *A Page 6 of 11 FastEdge™ Series CY2DP3120 PRELIMINARY tr, tf, 20-80% VO(p-p) Figure 4. ECL/LVPECL Output VPP / V D IF TPD VOD Figure 5. TPD Propagation Delay of Both CLKA or CLKB to (Q0–Q19),Q0#–Q0#19 Pair PECL/ECL/HSTL to PECL/ECL VPP / V D IF tP L H tP H L V O (P -P ) ts k (P ) O u tp u t p u ls e s k e w = | tP L H - tP H L | Figure 6. Output Pulse Skew Document #: 38-07514 Rev. *A Page 7 of 11 FastEdge™ Series CY2DP3120 PRELIMINARY VPP / V D IF Qn V O (P -P ) t s k (0 ) Q n+m V O (P -P ) Figure 7. Output to Output Skew Applications Information Termination Examples 1 .3 V CY2DP3120 V C C = 3 .3 V R T = 50 ohm 5" Zo = 50 ohm 5" R T = 50 ohm 1 .3 V VEE = 0V Figure 8. Standard LVPECL – PECL Output Termination Document #: 38-07514 Rev. *A Page 8 of 11 FastEdge™ Series CY2DP3120 PRELIMINARY -2 V C Y2DP3120 V C C = 0 .0 V RT = 50 ohm 5" Zo = 50 ohm 5" RT = 50 ohm -2 V V E E = -3 .3 V Figure 9. Standard ECL Output Termination VTT CY2DP3120 R T = 50 ohm VCC 5" Zo = 50 ohm 5" VTT R T = 50 ohm VBB VEE Figure 10. Driving a PECL/ECL Single-Ended Input 3 .3 V CY2DP3120 V C C = 3 .3 V 120 ohm LVDS 5" Zo = 50 ohm 33 ohm ( 2 p la c e s ) 5" 120 ohm 3 .3 V VEE = 0V 51 ohm ( 2 p la c e s ) L V P E C L to LVDS Figure 11. Low-Voltage Positive Emitter-Coupled Logic (LVPECL) to a Low-Voltage Differential Signaling (LVDS) Interface Document #: 38-07514 Rev. *A Page 9 of 11 PRELIMINARY FastEdge™ Series CY2DP3120 Ordering Information Part Number Package Type Product Flow CY2DP3120AI 52-pin TQFP Industrial, –40° to 85°C CY2DP3120AIT 52-pin TQFP – Tape and Reel Industrial, –40° to 85°C Package Diagram 52-lead Thin Plastic Quad Flat Pack (10 × 10 × 1.4 mm) A52 51-85131-** FastEdge is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07514 Rev. *A Page 10 of 11 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. FastEdge™ Series CY2DP3120 PRELIMINARY Document History Page Document Title: CY2DP3120 FastEdge™ Series 1:20 Differential Clock Buffer/Driver Document Number: 38-07514 REV. ECN NO. Issue Date Orig. of Change ** 122438 12/05/02 RGL New data sheet *A 125457 04/17/03 RGL Corrected typo Q14 to Q4 in pin 44 in the pin configuration diagram Changed pin #s 1,14,27 and 40 from VCC to VCCO Changed title to FastEdge™ Series 1:20 Differential Clock Buffer/Driver Document #: 38-07514 Rev. *A Description of Change Page 11 of 11