FastEdge™ Series CY2PP3220 PRELIMINARY Dual 1:10 Differential Fanout Buffer Features • • • • • • • • • • • • • Description Two sets of ten ECL/PECL differential outputs Two ECL-/PECL-differential inputs Hot-swappable/-insertable 50-ps output-to-output skew < 500-ps device-to-device skew Less than 10-ps intrinsic jitter 500-ps propagation delay (typical) Operation from DC to 1.5 GHz PECL supply range: VCC = 2.375V to 3.465V with VEE = 0V ECL mode supply range: VEE = –2.375V to –3.465V with VCC = 0V Industrial temperature range: –40°C to 85°C 52-pin 1.4-mm TQFP package Temperature compensation like 100K ECL The CY2PP3220 is a low-skew, low propagation delay, dual 1-to-10 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz. The device features two differential input paths which are differential internally. The CY2PP3220 may function not only as a differential clock buffer but also as a signal level translator and fanout ECL/PECL single-ended or differential signals to twenty ECL/PECL differential loads. An external bias pin, VBB, is provided for distributing a single-ended signal. In such an application, the VBB pin should be connected to either one of the CLKA# or CLKB# inputs and bypassed to VCC via a 0.01-µF capacitor. Traditionally, in ECL, it is used to provide the reference level to a receiving single ended input that might have a different self bias point. Since the CY2PP3220 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high-frequency, high-precision clocks across backplanes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2PP3220 delivers consistent, guaranteed performance over differing platforms. VCCO QA5# QA5 QA4# QA4 QA3# QA3 QA2# QA2 34 QA8# 33 QA9 CY2PP3220 8 32 QA9# VEE QB9# 9 31 QB0 10 30 QB0# QB9 11 29 QB1 QB8# 12 28 QB1# 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 VCCO 3901 North First Street • San Jose, CA 95134 QB2 7 CLKB# QB2# CLKB VCCO • QA1 6 QB8 Cypress Semiconductor Corporation Document #: 38-07513 Rev.*A QA0# QA8 VBB QB3 VBB 35 QB4 QB9 QB9# VEE 5 QB3# VEE QA7# CLKA# QB4# CLKB# QA7 36 QB5 VCC QA6# 4 QB6 QB0 QB0# VEE QA6 CLKA QB5# QA9 QA9# VCC 52 51 50 49 48 47 46 45 44 43 42 41 40 39 1 38 2 37 3 QB6# VEE VEE CLKB QA0 VCCO CLKA# QB7 CLKA QA0 QA0# QB7# VCC QA1# Pin Configuration Block Diagram • 408-943-2600 Revised April 15, 2003 PRELIMINARY FastEdge™ Series CY2PP3220 Pin Description Pin 4,5 Name I/O CLKA, CLKA# I,PD[1] Type Description ECL/PECL Default Differential clock input pair I,PC 7,8 CLKB, CLKB# I,PD I,PC ECL/PECL Alternate Differential clock input pair 52,50,48,46,44,42,39,3 QA(0:9) 7,35,33 O,OS ECL/PECL True output 51,49,47,45,43,41,38,3 QA#(0:9) 6,34,32 O,OS ECL/PECL Complement output 31,29,26,24,22,20,18,1 QB(0:9) 6,13,11 O,OS ECL/PECL True output 30,28,25,23,21,19,17,1 QB#(0:9) 5,12,10 O,OS ECL/PECL Complement output 6 VBB[3] 3,9 VEE[2] –PWR Power Power supply, negative connection 2 VCC +PWR Power Power supply, positive connection 1,14,27,40 VCCO +PWR Power Power supply, positive connection O Bias Reference voltage output for single ended ECL or PECL operation Governing Agencies The following agencies provide specifications that apply to the CY2PP3220. The agency name and relevant specification is listed below. Agency Name JEDEC Specification JESD 51 (Theta JA) JESD 8–2 (ECL) JESD 65–A (skew,jitter) IEEE 1596.3 (Jitter specs) UL 94 (Flammability) Mil–Spec 883E Method 1012.1 (Thermal Theta JC) Notes: 1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-down, PU for Pull-up, PC for Pull Center, O for output, OS for open source and PWR for Power. 2. In ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are between VCC and VEE. 3. VBB is available for use for single ended bias mode when VCC is +3.3V. Document #: 38-07513 Rev.*A Page 2 of 11 FastEdge™ Series CY2PP3220 PRELIMINARY Absolute Maximum Conditions Parameter Description Condition VCC Supply Voltage Non-functional VCC Operating Voltage Functional VBB Output Reference Voltage Relative to VCC IBB Output Reference Current Relative to VBB Min. Max. Unit –0.3 4.6 VDC 2.5 – 5% 3.3 + 5% VDC VCC–1.525 VCC–1.325 VDC 200 uA VTT Output Termination Voltage VTT = 0V for VCC = 2.5V VIN Input Voltage Relative to VCC –0.3 VCC–2 VDC VCC+0.3 VDC VOUT Output Voltage Relative to VCC –0.3 LUI Latch Up Immunity Functional VCC+0.3 VDC TS Temperature, Storage Non-Functional –65 150 °C TA Temperature, Operating Ambient Functional –40 85 °C ØJc Dissipation, Junction to Case Functional TBD TBD °C/W ØJa Dissipation, Junction to Ambient Functional 40 60 °C/W ESDh ESD Protection (Human Body Model) 2000 V MSL Moisture Sensitivity Level TBD N.A. GATES Total Functional Gate Count Assembled Die UL–94 Flammability Rating At 1/8 in. FIT Failure in Time Manufacturing test 300 mA 50 Ea. V–0 N.A. 1 ppm PECL DC Electrical Specifications Parameter Description Condition Min. VCC2.5V 2.5 Operating Voltage 2.5V ± 5%, VEE = 0.0V 2.375 VCC3.3V 3.3 Operating Voltage 3.3V ± 5%, VEE = 0.0V 3.135 VIL Input Voltage, Low VIH Input Voltage, High Define VCC and load current IIN Input Current[4] VIN = [VILmin=2.406V or VIH–ax=1.655V] at VCC=3.6V Max. Unit 2.625 V 3.465 V VCC–1.945 VCC–1.625 V VCC–1.165 VCC–0.880 V 200 uA Clock Input Pair CLKA, CLKA#, CLKB1, CLKB1#(PECL Differential Signals) VPP Differential input voltage[5] Differential operation 0.1 1.3 V VCMR Differential cross point voltage[6] Differential operation 1.2 VCC V 200 uA IIN Input Current [4] VIN = VIL or VIN = VIH PECL Outputs QA((0:9),#),QB((0:9),#)(PECL Differential Signals) VOH VOL Output High Voltage IOH = –30 mA[7] (50Ω Load) VCC–1.145 VCC–0.895 V Output Low Voltage VCC = 3.3V ± 5% VCC = 2.5V ± 5% ma[7] (50Ω VCC–1.945 VCC–1.945 VCC–1.695 VCC–1.695 V – 260 mA IOL = –5 Load) Supply Current and VBB IEE Maximum Quiescent Supply Current without output termination current[7] VEE pin IBB = 200 uA VBB Output reference voltage VCC–1.525 VCC–1.325 V IPUP Internal Pull-up Current TBD TBD mA IPDWN Internal Pull-down Current TBD TBD mA. Notes: 4. Input have internal pullup / pulldown or biasing resistors which affect the input current. 5. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 6. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 7. Equivalent to a termination of 50 Ω to VTT. Document #: 38-07513 Rev.*A Page 3 of 11 FastEdge™ Series CY2PP3220 PRELIMINARY PECL DC Electrical Specifications (continued) Min. Max. Unit CIN Parameter Input pin capacitance Description Condition TBD TBD pF COUT Output pin capacitance TBD TBD pF LIN Pin Inductance TBD TBD nH ZOUT Output impedance TBD TBD Ω ECL DC Electrical Specifications Min. Max. Unit VEE Parameter –2.5 Negative Power Supply Description –2.5V ± 5%, VEE = 0.0V Condition –2.375 –2.625 V VEE –3.3 Negative Power Supply –3.3V ± 5%, VEE = 0.0V –3.135 –3.465 V VIL Input Voltage, Low –1.945 –1.625 V VIH Input Voltage, High Define VCC and load current –1.165 –0.880 V IIN Input Current[4] VIN = VIL or Vin = VIH 200 uA 1.3 V Clock Input Pair CLKA,CLKA#,CLKB,CLKB# (ECL Differential Signals) VPP Differential input voltage[5] VCMR Differential cross point IIN Input Current[4] voltage[6] Differential operation 0.1 Differential operation VEE+1.2 VIN = VIL or VIN = VIH 0 V 200 uA ECL Outputs QA((0:9),#),QB((0:9),#) (ECL Differential Signals) VOH Output High Voltage IOH = –30 mA[7] –1.145 –0.895 V VOL Output Low Voltage VEE = –3.3V ± 5% VEE = –2.5V ± 5% IOL = –5 ma[7] –1.945 –1.945 –1.695 –1.3 V 130 mA –1.325 V Supply Current and VBB IEE Maximum Quiescent Supply Current without output termination current [8] VEE pin VBB Output reference voltage IBB=200 uA –1.525 AC Electrical Specifications Parameter Description Condition Min. Max. Unit Differential Operation 0.1 1.3 V Differential Operation VEE+1.2 Clock input pair CLKA, CLKA#, CLKB,CLKB# (PECL or ECL differential signals) VPP Differential input voltage[10] voltage[11] VCMR Differential cross point FIN Input Frequency[12] 50% Duty Cycle Standard load TPD Propagation Delay CLKA or CLKB to QA((0:4),#),QB((0:4),#) pairs 660-MHz 50% Duty Cycle Standard Load Differential Operation 0 V 1500 MHz 400 750 ps 0.45 0.4 0.375 – V VCC–1.425 V Clock Outputs QA((0:9),#),QB((0:9),#) Vo(P-P) Differential output voltage (peak-to-peak) VCMR Common Voltage Range Differential PRBS fo < 50 MHz fo < 0.8 GHz fo < 1.0 GHz Notes: 8. ICC Calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE or ICC = (number of differential output pairs used) x (VOH –VTT)/Rload + (VOL –VTT)/Rload +IEE. 9. AC characteristics apply for parallel output termination of 50Ω to VTT. 10. VPP (AC) is the minimum differential ECL/PECL input swing required to maintain AC characteristics including tpd and device-to-device skew. 11. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR(AC) range and the input swing lies within the VPP(AC) specification. Violation of VCMR(AC) or VPP(AC) impacts the device propagation delay, device and part-to-part skew. 12. The CY2PP3220 is fully operation up to 1.5 GHz. Document #: 38-07513 Rev.*A Page 4 of 11 FastEdge™ Series CY2PP3220 PRELIMINARY AC Electrical Specifications (continued) Min. Max. Unit tsk(O) Parameter Output-to-output skew Description 660-MHz 50% duty cycle Standard load Differential Operation Condition – 50 ps tsk(PP) Output-to-output skew (part-to-part) 660-MHz 50% duty cycle Standard load Differential Operation – 500 ps tCCJ Output cycle-to-cycle jitter (Intrinsic) 660-MHz 50% duty cycle Standard load Differential Operation TBD TBD ps tsk(P) Output pulse skew [13] 660-MHz 50% duty cycle Standard load Differential Operation TBD TBD ps TR,TF Output Rise/Fall time 660-MHz 50% duty cycle Differential 20% to 80% – 0.3 ns TTB Total Timing Budget 660-MHz 50% duty cycle Standard load TBD TBD ps DJ Deterministic/Intrinsic Jitter 660-MHz 50% duty cycle Standard load – 10 ps r.m.s. Timing Definitions VC C V C C = 2.5V or 3 .3V V C M R M ax = V C C V IH VPP V P P ran g e 0.1 V - 1.3V VCMR V IL V C M R M in = 1.2V G N D = 0.0 V GND Figure 1. PECL Waveform Definitions VCC V C C = 0 .0 V VCM R m ax = 0 V IH VPP VCMR V P P r a n g e = 0 .1 to 1 .3 V V IL V C M R m in = V E E -1 .2 V VEE V E E = -2 .5 V o r - 3 .3 V Figure 2. ECL Differential Waveform Definitions Note: 13. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |. Document #: 38-07513 Rev.*A Page 5 of 11 FastEdge™ Series CY2PP3220 PRELIMINARY tr, tf, 20-80% VO(p-p) Figure 3. Rise and Fall Time with Reference to the Output V PP / V DIF TPD VO D Figure 4. TPD Propagation Delay of Both CLKA or CLKA to QA((0:9),#),QB((0:9),#) Pair ECL/PECL to ECL/PECL VPP / VDIF tPLH tPHL VO(P-P) tsk(P) Output pulse skew = | tPLH - tPHL | Figure 5. Output Pulse Skew Document #: 38-07513 Rev.*A Page 6 of 11 FastEdge™ Series CY2PP3220 PRELIMINARY VPP / VDIF Qn VO(P-P) tsk(0) Qn+m VO(P-P) Figure 6. Output-to-Output Skew Test Configurations Standard test load using a differential pulse generator and differential measurement instrument. VTT VTT R T = 50 ohm R T = 50 ohm Pulse G enerator Z = 50 ohm 5" Zo = 50 ohm Zo = 50 ohm 5" R T = 50 ohm DUT CY2PP3220 R T = 50 ohm VTT VTT Figure 7. CY2PP3220 AC Test Reference Document #: 38-07513 Rev.*A Page 7 of 11 PRELIMINARY FastEdge™ Series CY2PP3220 Applications Information Document #: 38-07513 Rev.*A Page 8 of 11 FastEdge™ Series CY2PP3220 PRELIMINARY Termination Examples 1 .3 V CY2PP3220 V C C = 3 .3 V R T = 50 ohm 5" Zo = 50 ohm 5" R T = 50 ohm 1 .3 V VEE = 0V Figure 8. Standard LVPECL – PECL Output Termination VTT CY2PP3220 R T = 50 ohm VCC 5" Zo = 50 ohm 5" VTT R T = 50 ohm VBB VEE Figure 9. Driving a PECL Single-Ended Input 3 .3 V CY2PP3220 V C C = 3 .3 V 120 ohm LVDS 5" Zo = 50 ohm 33 ohm ( 2 p la c e s ) 5" 120 ohm 3 .3 V VEE = 0V 51 ohm ( 2 p la c e s ) L V P E C L to LVDS Figure 10. Low-Voltage Positive Emitter-coupled Logic (LVPECL) to a Low-Voltage Differential Signaling (LVDS) Interface Document #: 38-07513 Rev.*A Page 9 of 11 PRELIMINARY FastEdge™ Series CY2PP3220 Ordering Information Part Number Package Type Product Flow CY2PP3220AI 52-pin TQFP Industrial, –40° to 85°C CY2PP3220AIT 52-pin TQFP – Tape and Reel Industrial, –40° to 85°C Package Drawing and Dimensions 52-lead Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm) A52 51-85131-** FastEdge is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07513 Rev.*A Page 10 of 11 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. FastEdge™ Series CY2PP3220 PRELIMINARY Document History Page Document Title: CY2PP3220 FastEdge™ Series Dual 1:10 Differential Fanout Buffer Document Number: 38-07513 REV. ECN NO. Issue Date Orig. of Change ** 122437 02/13/03 RGL New Data Sheet *A 125459 04/16/03 RGL Interchanged Pin 30 and 31 from QB0 /QB0# to QB0#/QB0 Changed the title to FastEdge™ Series Dual 1:10 Differential Fanout Buffer Document #: 38-07513 Rev.*A Description of Change Page 11 of 11