FastEdge™ Series CY2PP326 PRELIMINARY 2 x 2 Clock and Data Switch Buffer Features Six LVPECL differential outputs grouped in two banks Two LVPECL differential inputs Hot-swappable/-insertable 50-ps output-to-output skew < 500-ps device-to-device skew (typical) Less than < 3-ps intrinsic jitter 400-ps propagation delay (typical) Operation up to 1.20 GHz LVPECL mode supply range: VCC = 2.375V to 3.465V Industrial temperature range: –40°C to 85°C 32-pin 1.4-mm TQFP package Temperature compensation like 100K ECL The CY2PP326 is a low-skew, low propagation delay 2 x 2 differential clock, data switch, and fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low-signal skews at operating frequencies of up to 1.20 GHz. The device features two differential input paths which are multiplexed internally to six outputs grouped in two banks. The muxes are controlled by SEL(0:1) control inputs. The CY2PP326 may function as 1:6 or 2x 1:3 clock/data buffer and as a clock/data repeater or multiplexer. Since the CY2PP326 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems and for switching data signals between different channels. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2PP326 delivers consistent, guaranteed performance over differing platforms. QA1 QA1# QB2 QB2# QA2 4 21 CLK0 CLK1# 5 20 CLK0# OEB# 6 19 SEL0 GND 7 18 GND VCC 8 17 VCC CY2PP326 QB0# OEA# OEB# QA2# CLK1 9 SEL0 SEL1 VCC 23 22 GND SEL1 2 3 VCC OEA# 10 11 12 13 14 15 16 QB2 1 QB1 QB1# GND QB2# 0 QB0 QB0# 32 31 30 29 28 27 26 25 24 VCC Bank B CLK1 CLK1# 1 QB1 VCC VCC QB1# QA2 QA2# VCC 1 QA1 0 QA1# QA0 QA0# CLK0 CLK0# VCC QA0# Bank A VCC QA0 Pin Configuration Block Diagram QB0 • • • • • • • • • • • • Description Sync Cypress Semiconductor Corporation Document #: 38-07506 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised September 8, 2003 FastEdge™ Series CY2PP326 PRELIMINARY Pin Description Name I/O[1] Type[2] 19,3 SEL0,SEL1 I LVCMOS Clock/Data Switch Select. 22,6 OEA#,OEB# I LVCMOS Output Enable. 21,4 CLK(0:1) I LVPECL True Differential Inputs. 20,5 CLK(0:1)# I LVPECL Complement Differential Inputs. 31,28,25 32,29,26 QA(0:2) QA(0:2)# O LVPECL Differential Outputs – Bank A. 10,13,16 9,12,15 QB(0:2) QB(0:2)# O LVPECL Differential Outputs – Bank B. 2,7,18,23, GND –PWR GND 1,8,11,14,17,24,27,30 VCC +PWR POWER Pin Description Ground. Positive Power Supply. Table 1. Function Table Control Default 0 1 OEA# 0 QA(0–2), QA(0–2)# are active. Deassertion of QA(0–2), QA(0–2)# are disabled and held at their OEA# can by asynchronous to the reference clock last valid state. Assertion of OEA# can by without generation of output runt pulses. asynchronous to the reference clock without generation of output runt pulses. OEB# 0 QB(0–2), QB(0–2)# are active. Deassertion of QB(0–2), QB(0–2)# are disabled and held at their OEB# can by asynchronous to the reference clock last valid state. Assertion of OEB# can by without generation of output runt pulses. asynchronous to the reference clock without generation of output runt pulses. SEL0,SEL1 00 See Table 2 Table 2. Clock Select Control SEL0 SEL1 CLK0 Routed to CLK1 Routed to 0 0 QA(0:2) and QB(0:2) – 1:6 fanout of CLK0 Application Mode 0 1 – QA(0:2) and QB(0:2) 1:6 fanout of CLK0 1 0 QA(0:2) QB(0:2) Dual 1:3 buffer 1 1 QB(0:2) QA(0:2) Dual 1:3 buffer crossed Governing Agencies The following agencies provide specifications that apply to the CY2PP326. The agency name and relevant specification is listed below. Agency Name Specification JEDEC JESD 51 (Theta JA)JESD 8-6 (HSTL) JESD 8–2 (ECL) JESD 65–A (skew,jitter) IEEE 1596.3 (Jitter specs) UL 94 (Flammability rating) Mil–Spec 883E Method 1012.1 (Thermal Theta JC) Notes: 1. In the I/O column, the following notation is used: I for input, O for output, PD for pull-down, PU for pull-up, PC for pull-center, OS for open source, and PWR for power. 2. In ECL mode (negative power supply mode), GND is either –3.3V or–2.5V and VCC is connected to (0V). In PECL mode (positive power supply mode), GND is connected to (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are between VCC and VEE. Document #: 38-07506 Rev. *B Page 2 of 10 FastEdge™ Series CY2PP326 PRELIMINARY Absolute Maximum Conditions Parameter Description Condition VCC Supply Voltage Non-functional VCC Operating Voltage Functional VTT Output Termination Voltage VTT = 0V for VCC = 2.5V VIN Input Voltage VOUT LUI Min. Max. Unit –0.3 4.6 VDC 2.5 – 5% 3.3 + 5% VDC VCC – 2 VDC Relative to VCC –0.3 VCC+0.3 VDC Output Voltage Relative to VCC –0.3 VCC+0.3 VDC Latch Up Immunity Functional TS Temperature, Storage Non-functional –65 +150 °C TA Temperature, Operating Ambient Functional –40 +85 °C ØJc Dissipation, Junction to Case Functional 40 60 °C/W ØJa Dissipation, Junction to Ambient Functional 40 100 °C/W ESDh ESD Protection (Human Body Model) MSL Moisture Sensitivity Level GATES Total Functional Gate Count FLM Flammability Rating FIT Failure in Time 300 2000 Volts 2 N.A. Assembled Die Manufacturing test mA 50 Each V0 N.A. TBD ppm PECL DC Electrical Specifications Parameter Description Condition Min. VCC2.5V 2.5 Operating Voltage 2.5V ± 5%, VEE = 0.0V 2.375 VCC3.3V 3.3 Operating Voltage 3.3V ± 5%, VEE = 0.0V 3.135 VIL Input Voltage, Low VIH Input Voltage, High Define VCC and load current IIN Input Current[3] VIN = [Vilmin = 2.406V or VIH – max = 1.655V] at VCC = 3.6V Max. Unit 2.625 V 3.465 V VCC–1.945 VCC–1.625 V VCC–1.165 VCC–0.880 V l150l uA Clock Input Pair CLK0, CLK0#, CLK1, CLK1#(PECL Differential Signals) VPP Differential Input Voltage[4] Differential operation 0.1 1.3 V VCMR Differential Cross Point Voltage[5] Differential operation 1.2 VCC V l150l uA IIN Input Current[3] VIN = [Vilmin = 2.406V or VIHmax = 1.655V] at VCC = 3.6V PECL Outputs QA((0:2),#),QB((0:2),#)(PECL Differential Signals) VOH Output High Voltage IOH = –30 mA[6] VOL Output Low Voltage VCC = 3.3V ± 5% VCC = 2.5V ± 5% IOL = –5 ma[6] VCC–1.2 VCC–0.7 V VCC–1.945 VCC –1.945 VCC–1.5 VCC–1.3 V Supply Current and VBB IPUP Internal Pull-up Current TBD TBD mA. IPDWN Internal Pull-down Current TBD TBD mA. CIN Input Pin Capacitance TBD TBD pF COUT Output Pin Capacitance TBD TBD pF LIN Pin Inductance TBD 1 nH ZOUT Output Impedance TBD TBD Ω Notes: 3. Input have internal pull-up/pull-down or biasing resistors which affect the input current. 4. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 5. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 6. Equivalent to a termination of 50 Ω to VTT. Document #: 38-07506 Rev. *B Page 3 of 10 FastEdge™ Series CY2PP326 PRELIMINARY Table 3. Jitter 0000 0101 0100 1100 1100 1100 0111 0001 1100 0111 0101 PRBS 44 bit (9 44-bit Binary streams before loopback) Freq (MHz) Neg Max (ps) Pos Max (ps) Peak-Peak (ps) R.M.S (ps) 270.00 –0.117 0.16 0.277 0.116 333.00 –0.471 0.44 0.911 0.101 500.00 –0.261 0.276 0.537 0.065 550.00 –0.26 0.232 0.492 0.61 500 –0.136 0.245 0.059 CLOCK 0.109 AC Electrical Specifications [7] Parameter Description Condition Min. Max. Unit Differential operation 0.1 1.3 V Differential operation VEE+1.2 Clock input pair CLK0, CLK0#, CLK1,CLK1# (PECL Differential Signals) VPP Differential input voltage[8] [9] VCMR Differential cross point voltage FIN Input Frequency[10] TPD Propagation Delay CLK0 or CLK1 to QA, 660 MHz 50% duty cycle QB pairs Standard load Differential Operation 0 V 1200 MHz 400 1.2 ns 0.45 0.4 0.375 – – – V V V 50% duty cycle Standard load PECL Clock Outputs QA((0:2),#),QB((0:2),#) Vo(P-P) Differential output voltage (peak-to-peak) Differential PRBS fo < 50 MHz fo < 0.8 GHz fo < 1.0 GHz VCMR Common Voltage Range tsk(O) Output-to-output skew 660-MHz 50% duty cycle Standard load Differential Operation – 50 ps tsk(PP) Output-to-output skew (part-to-part) 660-MHz 50% duty cycle Standard load Differential Operation – 500 ps tsk(P) Output pulse skew[11] 660-MHz 50% duty cycle Standard load Differential Operation TBD 75 ps TR,TF Output Rise / Fall time 660-MHz 50% duty cycle Differential 2 0% to 80% – 0.3 ns TTB Total Timing Budget 660-MHz 50% duty cycle Standard load TBD 250 ps DJ Deterministic / Intrinsic Jitter 660-MHz 50% duty cycle Standard load – 3 ps r.m.s. tPDLf Output disable time T = CLK period VCC–1.425 2.5T + tPD V 3.5T + tPD ns tPLDg Output enable time T = CLK period 3.0T + tPD 4.0T + tPD ns Notes: 7. AC characteristics apply for parallel output termination of 50 W to VTT. 8. VPP (AC) is the minimum differential ECL/PECL input swing required to maintain AC characteristics including tpd and device-to-device skew. 9. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR(AC) range and the input swing lies within the VPP(AC) specification. Violation of VCMR(AC) or VPP(AC) impacts the device propagation delay, device and part-to-part skew. 10. The CY2PP326 is fully operation up to 1.20 GHz. 11. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |. Document #: 38-07506 Rev. *B Page 4 of 10 FastEdge™ Series CY2PP326 PRELIMINARY VCC VCC = 3.3V VCM R M ax VCC-0.3 VIH VPP VPP range 0.1V - 1.3V VCM R VIL VCM R M in 1.0V GND = 0.0V G ND Figure 1. PECL Waveform Definitions tr, tf, 20-80% VO(p-p) Figure 2. LVPECL Output VP P / V D IF TP D VOD Figure 3. TPD Propagation Delay of Both CLK0 or CLK1 Output Pairs PECL to PECL Document #: 38-07506 Rev. *B Page 5 of 10 FastEdge™ Series CY2PP326 PRELIMINARY VP P / V D IF tP LH tPH L V O (P -P ) tsk(P) O utput pulse skew = | tP LH - tP H L | Figure 4. Output Pulse Skew VPP / VDIF Qn VO(P-P) tsk(0) Qn+m VO(P-P) Figure 5. Output-to-Output Skew Document #: 38-07506 Rev. *B Page 6 of 10 FastEdge™ Series CY2PP326 PRELIMINARY CLKX CLKX 1 2 3 2 1 3 50% OEX tPDL(OE[X] to Q[X} tPLD(OE[X] to Q[X} Q[X] Q[X]# Figure 6. Output Disable/Enable Timing Test Configurations Standard test load using a differential pulse generator and differential measurement instrument. VTT VTT R T = 50 ohm R T = 50 ohm Pulse Generator Z = 50 ohm 5" Zo = 50 ohm Zo = 50 ohm 5" DUT CY2PP326 R T = 50 ohm R T = 50 ohm VTT VTT Figure 7. CY2PP326 AC Test Reference Applications Information Termination Examples 1 .3 V CY2PP326 V C C = 3 .3 V RT = 50 ohm 5" Zo = 50 ohm 5" RT = 50 ohm 1 .3 V VEE = 0V Figure 8. Standard LVPECL – PECL Output Termination Document #: 38-07506 Rev. *B Page 7 of 10 FastEdge™ Series CY2PP326 PRELIMINARY 3 .3 V CY2PP326 V C C = 3 .3 V 120 ohm LVDS 5" Zo = 50 ohm 33 ohm ( 2 p la c e s ) 5" 120 ohm 3 .3 V 51 ohm ( 2 p la c e s ) L V P E C L to LVDS VEE = 0V Figure 9. Low-voltage Positive Emitter-Coupled Logic (LVPECL) to a Low-voltage Differential Signaling (LVDS) Interface Evaluation Material Figure 10. Demonstration PCB Ordering Information Part Number Package Type Product Flow CY2PP326AI 32-pin TQFP Industrial, –40° to 85°C CY2PP326AIT 32-pin TQFP – Tape and Reel Industrial, –40° to 85°C Document #: 38-07506 Rev. *B Page 8 of 10 PRELIMINARY FastEdge™ Series CY2PP326 Package Drawing and Dimensions 32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14 51-85088-*B FastEdge and ComLink are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07506 Rev. *B Page 9 of 10 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. FastEdge™ Series CY2PP326 PRELIMINARY Document History Page Document Title: CY2PP326 FastEdge™ Series 2 x 2 Clock and Data Switch Buffer Document Number: 38-07506 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 122361 02/12/03 RGL New Data Sheet *A 129269 09/09/03 RGL Changed ComLink to FastEdge Added tPLDg and tPDLf specs in the AC specs table Added the Output disable/enabling timing diagram Deleted the output reference voltage in the absolute max. conditions Fixed the AC/DC Electrical specs to match the EROS *B 131346 11/20/03 RGL Posted to external web Document #: 38-07506 Rev. *B Page 10 of 10