FastEdge™ Series CY2PP3210 PRELIMINARY Dual 1:5 Differential Fanout Buffer Features • • • • • • • • • • • • • Description Dual sets of five ECL/PECL differential outputs Two ECL/PECL differential inputs Hot-swappable/insertable <50-ps output-to-output skew <500-ps device-to-device skew Less than 10-ps intrinsic jitter 500-ps propagation delay (typical) Operation up to 1.5 GHz PECL mode supply range: VCC = 2.375V to 3.465V with VEE = 0V ECL mode supply range: VEE = –2.375V to –3.465V with VCC = 0V Industrial temperature range: –40°C to 85°C 32-pin 1.4-mm TQFP package Temperature compensation as 100K ECL The CY2PP3210 is a low-skew, low propagation delay dual 1-to-5 differential fanout buffer targeted to meet the requirements of high performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz. The device features two differential input paths that are differential internally. The CY2PP3210 may function not only as a differential clock buffer but also as a signal level translator and fanout distributing a single-ended signal. An external bias pin, VBB, is provided for an ECL/PECL single-ended or differential signal to 10 ECL/PECL differential loads. In such an application, the VBB pin should be connected to either one of the CLKA# or CLKB# inputs and bypassed to VCC via a 0.01µF capacitor. Traditionally, in ECL, it is used to provide the reference level to a receiving single-ended input that might have a different self bias point. Since the CY2PP3210 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high-frequency, high-precision clocks across back-planes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2PP3210 delivers consistent, guaranteed performance over different platforms. Pin Configuration Block Diagram VCCO QA0 QA0# QA1 QA1# QA2 QA2# VCCO QA0 QA0# QA1 QA1# VCC QA2 QA2# CLKA# QA3 QA3# QA4 QA4# 1 2 3 4 5 6 7 8 VCC N.C. CLKA CLKA# VBB CLKB CLKB# VEE CY2PP3210 24 23 22 21 20 19 18 17 QA3 QA3# QA4 QA4# QB0 QB0# QB1 QB1# 9 10 11 12 13 14 15 16 QB0 QB0# 32 31 30 29 28 27 26 25 CLKA VCCO QB4# QB4 QB3# QB3 QB2# QB2 VCCO CLKB QB1 QB1# VCC QB2 QB2# CLKB# QB3 QB3# QB4 QB4# VBB Cypress Semiconductor Corporation Document #: 38-07508 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised March 31, 2003 FastEdge™ Series CY2PP3210 PRELIMINARY Pin Description Pin 3,4 Name I/O Type CLKA, CLKA# I,PD[1] ECL/PECL Description Default Differential clock input pair I,PC 6,7 CLKB, CLKB# 2 I,PD I,PC ECL/PECL Alternate Differential clock input pair O,OS ECL/PECL True output N.C. No connect. Pad only 31,29,27,24,22 QA(0:4) 30,28,26,23,21 QA#(0:4) O,OS ECL/PECL Complement output 20,18,15,13,11 QB(0:4) O,OS ECL/PECL True output 19,17,14,12,10 ECL/PECL Complement output QB#(0:4) O,OS 5 VBB[3] O 8 VEE[2] –PWR Power Power supply, negative connection 1 VCC +PWR Power Power supply, positive connection VCCO +PWR Power Power supply, positive connection 9,16,25,32 Bias Reference voltage output for single ended ECL or PECL operation Governing Agencies The following agencies provide specifications that apply to the CY2PP3210. The agency name and relevant specification is listed below. Agency Name Specification JEDEC JESD 51 (Theta JA) JESD 8–2 (ECL) JESD 65–A (skew,jitter) IEEE 1596.3 (Jitter specs) UL 94 (Moisture Grading) Mil–Spec 883E Method 1012.1 (Thermal Theta JC) Notes: 1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull Down, PU for Pull Up, PC for Pull Center, O for output, OS for open source and PWR for Power. 2. In ECL mode (negative power supply mode), VEE is either –3.3V or–2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are between VCC and VEE. 3. VBB is available for use for single ended bias mode when VCC is +3.3V. Document #: 38-07508 Rev. *A Page 2 of 11 FastEdge™ Series CY2PP3210 PRELIMINARY . Absolute Maximum Conditions Parameter Description Condition VCC Supply Voltage Non-functional VCC Operating Voltage Functional VBB Output Reference Voltage Relative to VCC IBB Output Reference Current Relative to VBB Min. Max. Unit –0.3 4.6 VDC 2.5 – 5% 3.3+5% VDC VCC–1.525 Vcc–1.325 VDC 200 uA VTT Output Termination Voltage VTT = 0V for VCC = 2.5V VIN Input Voltage Relative to VCC –0.3 VCC–2 VDC VCC+0.3 VDC VOUT Output Voltage Relative to VCC –0.3 LUI Latch Up Immunity Functional VCC+0.3 VDC TS Temperature, Storage Non-functional –65 +150 °C TA Temperature, Operating Ambient Functional –40 +85 °C ØJc Dissipation, Junction to Case Functional TBD TBD °C/W ØJa Dissipation, Junction to Ambient Functional 40 60 °C/W ESDh ESD Protection (Human Body Model) MSL Moisture Sensitivity Level 300 mA 2000 TBD GATES Total Functional Gate Count Assembled Die UL–94 Flammability Rating At 1/8 in. FIT Failure in Time Manufacturing test Volts TBD N.A. 50 Each V–0 N.A. 1 ppm PECL DC Electrical Specifications Parameter Description Condition VCC2.5V 2.5 Operating Voltage 2.5V ± 5%, VEE = 0.0V VCC3.3V 3.3 Operating Voltage 3.3V ± 5%, VEE = 0.0V VIL Input Voltage, Low VIH Input Voltage, High Define VCC and load current IIN Input Current[4] Vin = [VILmin = 2.406V or VIHmax= 1.655V] at VCC = 3.6V Min. Max. Unit 2.375 2.625 V 3.135 3.465 V VCC–1.945 VCC–1.625 V VCC–1.165 VCC–0.880 V 200 uA Clock input pair CLKA, CLKA#, CLKB1, CLKB1#(PECL Differential signals) VPP Differential input voltage[5] Differential operation 0.1 1.3 V VCMR Differential cross point voltage[6] Differential operation 1.2 VCC V IIN Input Current[4] VIN = VIL or VIN = VIH 200 uA VCC–1.145 VCC–0.895 V VCC–1.945 VCC –1.945 VCC–1.695 VCC–1.695 V PECL Outputs QA((0:4),#),QB((0:4),#)(PECL Differential signals) VOH VOL Output High Voltage Output Low Voltage VCC = 3.3V ± 5% VCC = 2.5V ± 5% IOH = –30 mA[7] IOL = –5 ma[7] Notes: 4. Input have internal pullup / pulldown or biasing resistors which affect the input current. 5. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality 6. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 7. Equivalent to a termination of 50 Ω to VTT. Document #: 38-07508 Rev. *A Page 3 of 11 FastEdge™ Series CY2PP3210 PRELIMINARY PECL DC Electrical Specifications(continued) Parameter Description Condition Min. Max. Unit 130 mA VCC–1.525 VCC–1.325 V Supply Current and VBB IEE Maximum Quiescent Supply Current without output termination current[8] VEE pin VBB Output reference voltage IBB = 200 uA IPUP Internal Pull-up Current TBD TBD mA IPDWN Internal Pull-down Current TBD TBD mA CIN Input pin capacitance TBD TBD pF COUT Output pin capacitance TBD TBD pF LIN Pin Inductance TBD TBD nH ZOUT Output impedance TBD TBD Ω Min. Max. Unit ECL DC Electrical Specifications Parameter Description Condition VEE –2.5 Negative Power Supply –2.5V ± 5%, VEE = 0.0V –2.375 –2.625 V VEE –3.3 Negative Power Supply –3.3V ± 5%, VEE = 0.0V –3.135 –3.465 V VIL Input Voltage, Low –1.945 –1.625 V VIH Input Voltage, High –1.165 –0.880 V 200 uA V IIN Input Current Define VCC and load current [4] VIN = VIL or Vin = VIH Clock input pair CLKA,CLKA#,CLKB,CLKB# (ECL Differential signals) VPP Differential input voltage[5] VCMR Differential cross point voltage IIN Input Current[4] [6] Differential operation 0.1 1.3 Differential operation VEE+1.2 –0.3 V 150 uA –1.145 –0.895 V –1.945 –1.945 –1.695 –1.695 V 125 mA –1.325 V VIN = VIL or VIN = VIH ECL Outputs QA((0:4),#),QB((0:4),#) (ECL Differential signals) VOH VOL Output High Voltage Output Low Voltage VEE = –3.3V ± 5% VEE = –2.5V ± 5% IOH = –30 mA [7] IOL = –5 ma [7] Supply Current and VBB IEE Maximum Quiescent Supply Current without output termination current [8] VEE pin VBB Output reference voltage IBB = 200 uA –1.525 AC Electrical Specifications[9] Parameter Description Condition Min. Max. Unit Clock input pair CLKA, CLKA#, CLKB,CLKB# (PECL or ECL differential signals) VPP Differential input voltage[10] Differential Operation 0.1 1.3 V VCMR Differential cross point voltage[11] Differential Operation VEE+1.2 0 V FIN Input Frequency[12] 50% Duty Cycle Standard Load 3,500 MHz TPD Propagation Delay CLKA or CLKB to 660-MHz 50% Duty Cycle Standard Load DifferQA((0:4),#),QB((0:4),#) pairs ential Operation 750 ps 280 Notes: 8. ICC Calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE or ICC = (number of differential output pairs used) x (VOH –VTT)/Rload + (VOL –VTT)/Rload +IEE. 9. AC characteristics apply for parallel output termination of 50W to VTT. 10. VPP (AC) is the minimum Differential ECL/PECL input swing required to maintain AC characteristics including tpd and device-to-device skew. 11. VCMR (AC) is the crosspoint of the Differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR(AC) range and the input swing lies within the VPP(AC) specification. Violation of VCMR(AC) or VPP(AC) impacts the device propagation delay, device and part-to-part skew. 12. The CY2PP3210 is fully operation up to 1.5 GHz. Document #: 38-07508 Rev. *A Page 4 of 11 FastEdge™ Series CY2PP3210 PRELIMINARY AC Electrical Specifications[9](continued) Parameter Description Condition Min. Max. Unit 0.45 0.4 0.375 – V ECL Clock Outputs QA((0:4),#),QB((0:4),#) Vo(P-P) Differential output voltage (peak-to-peak) VMCR Common Voltage Range VCC–1.425 V tsk(O) Output-to-output skew 660-MHz 50% Duty Cycle Standard Load Differential Operation – 50 ps tsk(PP) Output-to-output skew (part-to-part) 660-MHz 50% Duty Cycle Standard Load Differential Operation – 500 ps tCCJ Output cycle-to-cycle jitter (Intrinsic) 660-MHz 50% Duty Cycle Standard Load Differential Operation TBD TBD ps tsk(P) Output pulse skew [13] 660-MHz 50% Duty Cycle Standard Load Differential Operation TBD TBD ps TR,TF Output Rise/Fall time 660-MHz 50% Duty Cycle Differential 20% to 80% – 0.3 ns TTB Total Timing Budget 660-MHz 50% Duty Cycle Standard Load TBD TBD ps DJ Deterministic/Intrinsic Jitter 660-MHz 50% Duty Cycle Standard Load – 10 ps r.m.s. Differential PRBS fo < 50 MHz fo < 0.8 GHz fo < 1.0 GHz Timing Definitions V CC VC C = 3.3V VCM R M ax = VCC VIH VP P V PP range 0.1V - 1.3V V CM R VIL V CM R M in = 1.2V G ND = 0.0V G ND Figure 1. PECL Waveform Definitions VCC V C C = 0 .0 V VCM R m ax = 0 V IH VPP VCMR V P P r a n g e = 0 .1 to 1 .3 V V IL V C M R m in V E E -1 .0 V VEE V E E = -2 .5 V o r - 3 .3 V Figure 2. ECL Differential Waveform Definitions Note: 13. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |. Document #: 38-07508 Rev. *A Page 5 of 11 FastEdge™ Series CY2PP3210 PRELIMINARY tr, tf, 20-80% VO(p-p) Figure 3. Rise and Fall Time with Reference to the Output V PP / V DIF TPD VO D Figure 4. TPD Propagation Delay of Both CLKA or CLKA to QA((0:4),#),QB((0:4),#) Pair PECL/ECL to PECL/ECL VPP / VDIF tPLH tPHL VO(P-P) tsk(P) Output pulse skew = | tPLH - tPHL | Figure 5. Output Pulse Skew Document #: 38-07508 Rev. *A Page 6 of 11 FastEdge™ Series CY2PP3210 PRELIMINARY VPP / VDIF Qn VO(P-P) tsk(0) Qn+m VO(P-P) Figure 6. Output-to-Output Skew Test Configurations Standard test load using a differential pulse generator and differential measurement instrument. VTT VTT R T = 50 ohm R T = 50 ohm Pulse G enerator Z = 50 ohm 5" Zo = 50 ohm Zo = 50 ohm 5" R T = 50 ohm DUT CY2PP3210 R T = 50 ohm VTT VTT Figure 7. CY2PP3210 AC Test Reference Document #: 38-07508 Rev. *A Page 7 of 11 FastEdge™ Series CY2PP3210 PRELIMINARY Applications Information Termination Examples 1 .3 V CY2PP3210 V C C = 3 .3 V R T = 50 ohm 5" Zo = 50 ohm 5" R T = 50 ohm 1 .3 V VEE = 0V Figure 8. Standard LVPECL – PECL Output Termination VTT CY2PP3210 R T = 50 ohm VCC 5" Zo = 50 ohm 5" VTT R T = 50 ohm VBB VEE Figure 9. Driving a PECL Single-Ended Input 3 .3 V CY2PP3210 V C C = 3 .3 V 120 ohm LVDS 5" Zo = 50 ohm 33 ohm ( 2 p la c e s ) 5" 120 ohm 3 .3 V VEE = 0V 51 ohm ( 2 p la c e s ) L V P E C L to LVDS Figure 10. Low-Voltage Positive Emitter-Coupled Logic (LVPECL) to a Low-Voltage Differential Signaling (LVDS) Interface Document #: 38-07508 Rev. *A Page 8 of 11 PRELIMINARY FastEdge™ Series CY2PP3210 Evaluation Material Figure 11. Demonstration PCB Ordering Information Part Number Package Type Product Flow CY2PP3210AI 32-pin TQFP Industrial, –40° to 85°C CY2PP3210AIT 32-pin TQFP – Tape and Reel Industrial, –40° to 85°C Document #: 38-07508 Rev. *A Page 9 of 11 PRELIMINARY FastEdge™ Series Package Drawing and Dimensions 32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14 51-85088-*B FastEdge is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-07508 Rev. *A Page 10 of 11 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. FastEdge™ Series CY2PP3210 PRELIMINARY Document History Page Document Title: CY2PP3210 FastEdge™ Series Dual 1:5 Differential Fanout Buffer Document Number: 38-07508 REV. ECN NO. Issue Date Orig. of Change ** 122396 02/12/03 RGL New Data Sheet *A 125458 04/17/03 RGL Corrected pins 26 to 31 from Q2#, Q2, Q1#, Q1, Q0#, Q0 to QA2#, QA2, QA1#, QA1,QA0#, QA0 in the Pin Configuration diagram Changed pins 9, 16, 25, 32 from VCC to VCCO Changed the title to FastEdge™ Series Dual 1:5 Differential Fanout Buffer Document #: 38-07508 Rev. *A Description of Change Page 11 of 11