19-1755; Rev 1; 3/01 Wide Brightness Range CCFL Backlight Controllers Features ♦ Fast Response to Input Change The MAX1739/MAX1839 monitor and limit the transformer center-tap voltage when required. This ensures minimal voltage stress on the transformer, which increases the operating life of the transformer and eases its design requirements. These controllers also provide protection against many other fault conditions, including lamp-out and buck short faults. These controllers achieve 50:1 dimming range by simultaneously adjusting lamp current and “chopping” the CCFL on and off using a digitally adjusted pulsewidth modulated (DPWM) method. CCFL brightness is controlled by an analog voltage or is set with an SMBusTM-compatible two-wire interface (MAX1739). The MAX1739/MAX1839 drive an external high-side N-channel power MOSFET and two low-side N-channel power MOSFETs, all synchronized to the Royer oscillator. An internal 5.3V linear regulator powers the MOSFET drivers and most of the internal circuitry. The MAX1739/MAX1839 are available in space-saving 20-pin QSOP packages and operate over the -40°C to +85°C temperature range. ♦ Integrated Royer MOSFET Drivers Reduce Transformer Pin Count ♦ Wide Input Voltage Range (4.6V to 28V) ♦ High Power-to-Light Efficiency ♦ Minimizes Transformer Voltage Stress ♦ Lamp-Out Protection with 2s Timeout ♦ Buck Switch Short and Other Single-Point Fault Protection ♦ Buck Operation Synchronized to Royer Oscillator ♦ Synchronizable DPWM Frequency ♦ Pin-Selectable Brightness Control Interface ♦ SMBus Serial Interface (MAX1739) ♦ Analog Interface (MAX1739/MAX1839) Ordering Information TEMP. RANGE PIN-PACKAGE MAX1739EEP PART -40°C to +85°C 20 QSOP MAX1839EEP -40°C to +85°C 20 QSOP Pin Configuration ________________________Applications Notebook/Laptop Computers Car Navigation Displays LCD Monitors TOP VIEW REF 1 20 BATT MINDAC 2 19 DH Point-of-Sale Terminals CCI 3 18 LX Portable Display Electronics CCV 4 17 BST SH/SUS 5 †Patent pending MAX1739 16 VL CRF/SDA 6 15 GND CTL/SCL 7 14 CS MODE 8 13 DL1 CSAV 9 12 DL2 CTFB 10 11 SYNC QSOP SMBus is a trademark of Intel Corp. Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX1739/MAX1839† General Description The MAX1739/MAX1839 fully integrated controllers are optimized to drive cold-cathode fluorescent lamps (CCFLs) using the industry-proven Royer oscillator inverter architecture. The Royer architecture provides near sinusoidal drive waveforms over the entire input range to maximize the life of CCFLs. The MAX1739/ MAX1839 optimize this architecture to work over a wide input voltage range, achieve high efficiency, and maximize the dimming range. MAX1739/MAX1839† Wide Brightness Range CCFL Backlight Controllers ABSOLUTE MAXIMUM RATINGS VBATT to GND ...........................................................-0.3V to 30V VBST, VSYNC to GND.................................................-0.3V to 34V VBST to VLX .................................................................-0.3V to 6V VDH to VLX .................................................-0.3V to (VBST + 0.3V) VLX to GND...................................................-6V to (VBST + 0.3V) VL to GND...................................................................-0.3V to 6V VCCV, VCCI, VREF, VDL1, VDL2 to GND .........-0.3V to (VL + 0.3V) VMINDAC, VCTFB, VCSAV to GND ................................-0.3V to 6V VCS to GND...................................................-0.6V to (VL + 0.3V) VMODE to GND.............................................................-6V to 12V VCRF/SDA, VCRF, VCTL/SCL, VCTL, V SH/SUS, V SH to GND ............................................................-0.3V to 6V Continuous Power Dissipation (TA = +70°C) 20-Pin QSOP (derate 9.1mW/°C above +70°C)...........727mW Operating Temperature .......................................-40°C to +85°C Storage Temperature.........................................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V+ = 8.2V, V SH/SUS = V SH = 5.5V, MINDAC = GND, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER CONDITIONS MIN TYP MAX UNITS SUPPLY AND REFERENCE VBATT Input Voltage Range VBATT Quiescent Current, Operation with Full Duty Cycle on DH VL = VBATT 4.6 5.5 VL = open 6 28 DH = DL1 = DL2 = open VBATT = 28V 3.2 6 VBATT = VL = 5V 3.2 6 V mA µA VBATT Quiescent Current, Shutdown SH/SUS = SH = GND 6 20 VL Output Voltage, Normal Operation 6V < VBATT < 28V, 0 < ILOAD < 15mA 5.0 5.35 5.5 V VL Output Voltage, Shutdown SH/SUS = SH = GND, no load 3.5 4.5 5.5 V VL Undervoltage Lockout Threshold VL rising (leaving lockout) VL falling (entering lockout) 4.6 4.0 VL Undervoltage Lockout Hysteresis REF Output Voltage, Normal Operation V 300 4.5V < VL < 5.5V, IREF = 40µA 2.04 V 2.7 V DH Driver On-Resistance 18 Ω DL1, DL2 Driver On-Resistance 18 Ω VL POR Threshold 1.96 2.00 mV 0.9 SWITCHING REGULATOR Minimum DH Switching Frequency 1/tDH, SYNC = CS or GND, not synchronized DH Minimum Off-Time 49 56 64 kHz 250 375 500 ns 200 kHz DH Maximum Duty Cycle 64 % SYNC Synchronization Range Detect falling edges on SYNC SYNC Input Current 0 < VSYNC < 30V 2 µA SYNC Input Threshold SYNC falling, referred to CS 400 500 600 mV SYNC Input Hysteresis Referred to the SYNC input threshold 50 100 150 mV SYNC Threshold Crossing to DL1, DL2 Toggle Delay VSYNC = 0 to 5V, CDL_1 and CDL_2 < 100pF, 50% point on SYNC to 50% point on DL1 or DL2 120 ns 492 mV CS Overcurrent Threshold 2 98 -2 408 450 _______________________________________________________________________________________ Wide Brightness Range CCFL Backlight Controllers (V+ = 8.2V, V SH/SUS = V SH = 5.5V, MINDAC = GND, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER CONDITIONS MIN TYP MAX UNITS DAC AND ERROR AMPLIFIER DAC Resolution Guaranteed monotonic MINDAC Input Voltage Range MINDAC Input Bias Current MINDAC Digital PWM Disable Threshold CSAV Input Voltage Range CSAV Regulation Point Bits 2 V 0 < VMINDAC < 2V -1 1 µA MINDAC = VL 2.4 2.9 4 V 0.8 V VMINDAC = 0, DAC code = 11111 binary 188 194 200 VMINDAC = 0, DAC code = 00001 binary 2 6.25 16 VMINDAC = 1V, DAC code = 00000 binary 93 100 110 0 CSAV Input Bias Current CSAV to CCI Transconductance 5 0 -1 1V < VCCI < 2.7V 1 0 CTFB Input Bias Current 2 1 µA 600 630 mV 30 40 50 µmho kHz CTFB to CCV Transconductance TIMERS AND FAULT DETECTION 1V < VCCV < 2.7V Chopping Oscillator Frequency No AC signal on MODE, not synchronized 24 28 32 No AC signal on MODE 205 220 235 Digital PWM Chop-Mode Frequency 32kHz AC signal on MODE 250 100kHz AC signal on MODE 781 MODE to DPWM Sync Ratio FMODE / FDPWM 128 Lamp-Out Detection Timeout Timer (Center-Tap Voltage Stuck at Maximum) (Note 1) VCSAV < CSAV lamp-out threshold No AC signal on MODE Fault-Detection Threshold on CCV 2.06 2.33 32kHz AC signal on MODE 2.05 100kHz AC signal on MODE 0.66 CSAV Lamp-Out Threshold 50 (Note 2) 75 0.4 No AC signal on MODE Shorted Buck-Switch Detection Timeout Timer (UL1950 Protection) (Note 3) VCCV < faultdetection threshold on CCV Lamp Turn-On Delay After SH/SUS or SH forces device on or SH rises 332 291 32kHz AC signal on MODE 256 100kHz AC signal on MODE 82 MODE Operating Voltage Range V 570 -1 CTFB Regulation Point µA µmho 100 CTFB Input Voltage Range mV Hz 2.73 s 100 mV 1 V 259 ms 4 -5.5 ms 11 V 0.6 V 2.6 V MODE = GND Threshold (min Brightness = 0) To sync DPWM oscillator, not in shutdown (Note 4) MODE = REF Threshold (max Brightness = 0) To sync DPWM oscillator, not in shutdown (Note 4) 1.4 MODE = VL Threshold (MAX1739 SMB Interface Mode) To sync DPWM oscillator, not in shutdown (Note 4) VL - 0.6 V MODE AC Signal Amplitude Peak to peak (Note 5) 2 V MODE AC Signal Synchronization Range Chopping oscillator synchronized to MODE AC signal 32 100 kHz _______________________________________________________________________________________ 3 MAX1739/MAX1839† ELECTRICAL CHARACTERISTICS (continued) MAX1739/MAX1839† Wide Brightness Range CCFL Backlight Controllers ELECTRICAL CHARACTERISTICS (continued) (V+ = 8.2V, V SH/SUS = V SH = 5.5V, MINDAC = GND, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER CONDITIONS MIN TYP MAX UNIT ANALOG INTERFACE BRIGHTNESS CONTROL (MODE connected to REF or GND ) CRF/SDA, CRF Input Range CRF/SDA, CRF Input Current CTL/SCL, Input Range 2.7 VCRF/SDA = VCRF = 5.5V 5.5 V 20 µA VCRF/SDA = VCRF = 5.5V, SH/SUS = SH = 0 -1 1 µA MAX1739 0 CRF/ SDA V CTL Input Range MAX1839 0 CRF V CTL/SCL, CTL Input Current MODE = REF or GND -1 1 µA ADC Resolution Guaranteed monotonic ADC Hysteresis 5 Bits 1 LSB SH Input Low Voltage 0.8 SH Input High Voltage 2.1 SH/SUS Input Hysteresis when Transitioning In and Out of Shutdown V 150 SH Input Bias Current V -1 mV 1 µA SYSTEM MANAGEMENT BUS BRIGHTNESS CONTROL (MAX1739, MODE connected to VL, see Figures 12 and 13) CRF/SDA, CTL/SCL, SH/SUS Input 0.8 CRF/SDA, CTL/SCL, SH/SUS Input 2.1 CRFSDA, CTLSCL Input Hysteresis V 300 CRF/SDA, CTL/SCL, SH/SUS Input -1 CRF/SDA Output Low Sink Current VCRF/SDA = 0.4V CTL/SCL Serial Clock High Period CTL/SCL Serial Clock Low Period V mV 1 µA 4 mA tHIGH 4 µs tLOW 4.7 µs Start Condition Setup Time tSU:STA 4.7 µs Start Condition Hold Time tHD:STA 4 µs CRF/SDA Valid to CTL/SCL Rising Edge Setup Time, Slave Clocking in Data tSU:DAT 250 ns CTL/SCL Falling Edge to CRF/SDA Transition tHD:DAT 0 ns CTL/SCL Falling Edge to CRF/SDA Valid, Reading Out Data tDV 4 _______________________________________________________________________________________ 1 µs Wide Brightness Range CCFL Backlight Controllers (V+ = 8.2V, V SH/SUS = V SH = 5.5V, MINDAC = GND, TA = -40°C to +85°C, unless otherwise noted.) (Note 6) PARAMETER CONDITIONS MIN TYP MAX UNITS SUPPLY AND REFERENCE VBATT Input Voltage Range VL = VBATT 4.6 5.5 VL = open 6 28 VBATT Quiescent Current, Shutdown SH/SUS = SH = GND VL Output Voltage, Normal Operation 6V < VBATT < 28V, 0 < ILOAD < 15mA VL Undervoltage Lockout Threshold 5.0 VL rising (leaving lockout) V 20 µA 5.6 V 4.6 V VL falling (entering lockout) 4.0 4.5V < VL < 5.5V, IREF = 40µA 1.95 2.05 V 0.9 2.7 V DH Driver On-Resistance 18 Ω DL1, DL2 Driver On-Resistance 18 Ω 64 200 kHz 408 492 mV 186 202 mV 560 640 mV 30 50 µmho 0.8 V REF Output Voltage, Normal Operation VL POR Threshold SWITCHING REGULATOR SYNC Synchronization Range Detect falling edges on SYNC CS Overcurrent Threshold DAC AND ERROR AMPLIFIER CSAV Regulation Point VMINDAC = 0, DAC code = 11111 binary CTFB Regulation Point CTFB to CCV Transconductance 1V < VCCV < 2.7V ANALOG INTERFACE BRIGHTNESS CONTROL (MODE connected to REF or MODE connected to GND) SH Input Low Voltage SH Input High Voltage 2.1 V SYSTEM MANAGEMENT BUS BRIGHTNESS CONTROL (MODE connected to VL) CRF/SDA, CTL/SCL, SH/SUS Input Low Voltage 0.8 CRF/SDA, CTL/SCL, SH/SUS Input High Voltage CRF/SDA Output Low Sink Current VCRF/SDA = 0.4V Note 1: Corresponds to 512 DPWM cycles or 65536 MODE cycles. Note 2: When the buck switch is shorted, VCTFB goes high causing VCCV to go below the fault detection threshold. Note 3: Corresponds to 64 DPWM cycles or 8192 MODE cycles. Note 4: The MODE pin thresholds are only valid while the part is operating. In shutdown, VREF = 0 and the part only differentiates between SMB mode and ADC mode. In shutdown with ADC mode selected, the CRF/SDA and CTL/SCL pins are at high impedance and will not cause extra supply current when their voltages are not at GND or VL. V 2.1 V 4 mA Note 5: The amplitude is measured with the following circuit: VAMPLITUDE > 2V 500pF MODE 10k Note 6: Specifications from -40°C to +85°C are guaranteed by design, not production tested. _______________________________________________________________________________________ 5 MAX1739/MAX1839† ELECTRICAL CHARACTERISTICS Typical Operating Characteristics (VIN = 12V, VCTL = VCRF, VMINDAC = 1V, MODE = GND, Circuit of Figure 8.) WIDE INPUT RANGE (VBATT = 20V) MAX1739/1839 toc02 MAX1739/1839 toc01 WIDE INPUT RANGE (VBATT = 8V) VCTAP 5V/div VCSAV 500mV/div VDH 20V/div VDH 20V/div WIDE INPUT RANGE (VBATT = 20V, DPWM = 9%, VCTL = 0) MAX1739/1839 toc04 WIDE INPUT RANGE (VBATT = 8V, DPWM = 9%, VCTL = 0) MAX1739/1839 toc03 4µs/div VCTAP 10V/div VCCV VCCV VCCV, VCCI 200mV/div VCCI VCCI VCCI VCCV VCCV 1.2V VCCI VCCI VCCV SWITCHING WAVEFORMS FEED-FORWARD COMPENSATION 20V VIN 10V VCTAP 5mV/div VCTAP 10V/div VCSAV 500mV/div VCSAV 500mV/div VDH 20V/div VDH 20V/div 6 1.2V 100µs/div 100µs/div 20µs/div VCCV, VCCI 200mV/div MAX1739/1839 toc08 VCCV VCTAP 10V/div VCSAV 500mV/div VCSAV 500mV/div VCCI VCTAP 5V/div VCSAV 500mV/div 4µs/div MAX1739/1839 toc05 MAX1739/MAX1839† Wide Brightness Range CCFL Backlight Controllers VDL 5V/div 4µs/div _______________________________________________________________________________________ Wide Brightness Range CCFL Backlight Controllers SYNCHRONIZED DPWM (fMODE = 32kHz, VCTL = VCRF/2) MAX1739/1839 toc06 MAX1739/1839 toc07 SYNCHRONIZED DPWM (fMODE = 100kHz, VCTL = VCRF/2) VCTAP 5V/div VCSAV 500mV/div VCTAP 5V/div VCSAV 500mV/div VDH 20V/div VDH 20V/div 1ms/div 1ms/div STARTUP (ADC SOFT-START, MODE = GND) MAX1739/1839 toc10 MAX1739/1839 toc09 LAMP-OUT VOLTAGE LIMITING 12V VBATT 0 VSECONDARY 2kV/div VCTAP 10V/div VCSAV 500mV/div VCTAP 5V/div IBATT 500mA/div 2ms/div LAMP-OUT VOLTAGE LIMITING INPUT CURRENT vs. INPUT VOLTAGE MAX1739/1839 toc12 900 800 VSECONDARY 2kV/div 8 SHUTDOWN 700 7 IBATT (mA) 600 VCTAP 5V/div 6 500 5 MAXIMUM BRIGHTNESS 400 4 300 3 200 2 100 1 MINIMUM BRIGHTNESS 0 400ms/div 9 SHUTDOWN CURRENT (µA) MAX1739/1839 toc11 20ms/div 0 0 5 10 15 20 25 VBATT (V) _______________________________________________________________________________________ 7 MAX1739/MAX1839† Typical Operating Characteristics (continued) (VIN = 12V, VCTL = VCRF, VMINDAC = 1V, MODE = GND, Circuit of Figure 8.) Typical Operating Characteristics (continued) (VIN = 12V, VCTL = VCRF, VMINDAC = 1V, MODE = GND, Circuit of Figure 8.) VL vs. BATT VOLTAGE MAX1739/1839 toc13 4.6 6 4.5 5 NORMAL OPERATION 4.4 3 5.25 4.3 5.20 4.2 5.15 4.1 1 4.0 0 5.10 0.01 0.1 1 10 SHUTDOWN 4 VL (V) SHUTDOWN 5.30 SHUTDOWN VL (V) NORMAL OPERATION 5.35 2 0 100 5 10 15 20 VBATT (V) IVL (mA) VL vs. TEMPERATURE MAX1739/1839 toc15 5.36 4.60 5.35 4.55 5.34 4.50 NORMAL OPERATION 5.33 4.45 5.32 4.40 5.31 SHUTDOWN VL (V) VL (V) SHUTDOWN 4.35 -40 -15 10 35 60 85 TEMPERATURE (°C) 8 MAX1739/1839 toc14 VL vs. IVL 5.40 VL (V) MAX1739/MAX1839† Wide Brightness Range CCFL Backlight Controllers _______________________________________________________________________________________ 25 Wide Brightness Range CCFL Backlight Controllers PIN NAME FUNCTION MAX1739 MAX1839 1 REF REF 2V Reference Output. Bypass to GND with 0.1µF. Forced low during shutdown. 2 MINDAC MINDAC DAC Zero-Scale Input. VMINDAC sets the DAC’s minimum scale output voltage. Disable DPWM by connecting MINDAC to VL. 3 CCI CCI GMI Output. Output of the current loop GMI amplifier that regulates the CCFL current. Typically bypass to GND with 0.1µF . 4 CCV CCV GMV Output. Output of the voltage loop GMV amplifier that regulates the maximum average primary transformer voltage. Typically bypass to GND with 3300p F. 5 SH/SUS SH Logic Low Shutdown Input in Analog Interface Mode. SMBus suspends input in SMBus interface mode (MAX1739 only). 6 CRF/SDA CRF 5-Bit ADC Reference Input in Analog Interface Mode. Bypass to GND with 0.1µF. SMBus serial data input/open-drain output (MAX1739 only) in SMBus interface mode. 7 CTL/SCL CTL CCFL Brightness Control Input in Analog Interface Mode. SMBus serial clock input (MAX1739 only) in SMBus interface mode. 8 MODE MODE Interface Selection Input and Sync Input for DPWM Chopping (see Synchronizing the DPWM Frequency). The average voltage on the MODE pin selects one of three CCFL brightness control interfaces: 1) MODE = VL, enables SMBus serial interface (MAX1739 only). 2) MODE = GND, enables the analog interface (positive scale analog interface mode); VCTL/SCL = 0 means minimum brightness. 3) MODE = REF, enables the analog interface (negative scale analog interface mode); VCTL/SCL = 0 means maximum brightness. 9 CSAV CSAV Current-Sense Input. Input to the GMI error amplifier that drives CCI. 10 CTFB CTFB Center-Tap Voltage Feedback Input. The average VCTFB is limited to 0.6V. Royer Synchronization Input. Falling edges on SYNC force DH on and toggle the DL1 and DL2 drivers. Connect directly to the Royer center tap. 11 SYNC SYNC 12 DL2 DL2 13 DL1 DL1 Low-Side N-Channel MOSFET 1 Gate Drive Current-Sense Input (Current Limit). The current-mode regulator terminates the switch cycle when VCS exceeds (VREF - VCCI). 14 CS CS 15 GND GND 16 VL VL 17 BST BST Low-Side N-Channel MOSFET 2 Gate Drive. Drives the Royer oscillator switch. DL1 and DL2 have make-before-break switching, where at least one is always on. Falling edges on SYNC toggle DL1 and DL2 and turn DH on. System Ground 5.3V Linear Regulator Output. Supply voltage for most of the internal circuits. Bypass with 1µF capacitor to GND. Can be connected to VBATT if VBATT < 5.5V. High-Side Driver Bootstrap Input. Connect through a diode to VL and bypass with 0.1µF capacitor to LX. 18 LX LX High-Side Driver Ground Input 19 DH DH High-Side Gate Driver Output. Falling edges on SYNC turn on DH. 20 BATT BATT Supply Input. Input to the internal 5.3V linear regulator that powers the chip. _______________________________________________________________________________________ _______________________________________________________________________________________ 9 MAX1739/MAX1839† Pin Description MAX1739/MAX1839† Wide Brightness Range CCFL Backlight Controllers detect. Figure 1 shows the current and voltage waveforms for the three operating modes with the brightness control set to 50% of full scale. The MAX1739/MAX1839 include a 5.3V linear regulator to power most of the internal circuitry, drivers for the buck and Royer switches, and the synchronizable DPWM oscillator. The MAX1739/MAX1839 are very flexible and include a variety of operating modes, an analog interface, an SMBus interface (MAX1739 only), a shutdown mode, lamp-out detection, and buck-switch short detection. Detailed Description The MAX1739/MAX1839 regulate the brightness of a CCFL in three ways: 1) Linearly controlling the lamp current. 2) Digitally pulse-width modulating (or chopping) the lamp current (DPWM). 3) Using both methods simultaneously for widest dimming range. DPWM is implemented by pulse-width modulating the lamp current at a rate faster than the human eye can DPWM CONTROL VMINDAC = 0 VCTL = VCRF/2 or BRIGHT[4:0] = 10,000 (DAC SET TO MIDSCALE) EFFECTIVE BRIGHTNESS IS: 50% IN CONTINUOUS AND DPWM CONTROL 25% IN COMBINED CONTROL VCTAP TRANSFORMER VOLTAGE VCSAV LAMP CURRENT CONTINUOUS CURRENT CONTROL CURRENT + DPWM CONTROL VCTAP VCSAV Figure 1. Brightness Control Methods 10 ______________________________________________________________________________________ Wide Brightness Range CCFL Backlight Controllers During DPWM, the two control loops work together to limit the transformer voltage and to allow wide dimming range with good line rejection. During the DPWM offcycle, VCCV is set to 1.2V and CCI is set to high impedance. VCCV is set to 1.2V to create soft-start at the beginning of each DPWM on-cycle in order to avoid overshoot on the transformer primary. VCCI is set to high impedance to keep VCCI from changing during the off-cycles. This allows the current control loop to regulate the average lamp current only during DPWM oncycles and not the overall average lamp current. Upon power-up, VCCI slowly rises, increasing the duty cycle, which provides soft-start. During this time, VCCV, which is the faster control loop, is limited to 150mV above VCCI by the CCV-CLAMP. Once the secondary voltage reaches the strike voltage, the lamp current begins to increase. When the lamp current reaches the regulation point, VCCI reaches steady state. With MINDAC = VL (DPWM disabled), the current control loop remains in control and regulates the lamp current. With MINDAC between REF and GND, DPWM is enabled and the MAX1739/MAX1839 begin pulsing the lamp current. During the on-cycle, VCCV is at 150mV above VCCI. After the on-cycle, VCCV is forced down to 1.2V to provide soft-start at the beginning of the next on-cycle. Also, VCCI retains its value until the beginning of the next on-cycle. When VCCV increases, it causes the buck regulator duty cycle to increase and provides soft-start. When VCCV crosses over VCCI, the current control loop regains control and regulates the lamp current. V CCV is limited to 150mV above V CCI for the remainder of the on-cycle. In a lamp-out condition, VCCI increases the primary voltage in an attempt to maintain lamp current regulation. As VCCI rises, VCCV rises with it until the primary voltage reaches its set limit point. At this point, VCCV stops rising and limits the primary voltage by limiting the duty cycle. Because V CCV is limited to 150mV above VCCI, the voltage control loop is quickly able to limit the primary voltage. Without this clamping feature, the transformer voltage would overshoot to dangerous levels because V CCV would take more time to slew down from its supply rail. Once the MAX1739/MAX1839 sense less than 1/6 the full-scale current through the lamp for 2 seconds, it shuts down the Royer oscillator (see Lamp-Out Detection). See the Sense Resistors section for information about setting the voltage and current control loop thresholds. Feed-Forward Control Both control loops are influenced by the input voltage feed-forward (VBATT) control circuitry of the MAX1739/ MAX1839. Feed-forward control instantly adjusts the buck regulator’s duty cycle when it detects a change in input voltage. This provides immunity to changes in input voltage at all brightness levels. This feature makes compensation over wide input ranges easier, makes startup transients less dependent on input voltage, and improves line regulation for short DPWM ontimes. The MAX1739/MAX1839 feed-forward control is implemented by varying the amplitude of the buck-switch’s PWM ramp amplitude. This has the effect of varying the duty cycle as a function of input voltage while maintaining the same VCCI and VCCV. In other words, VBATT feed forward has the effect of not requiring changes in errorsignal voltage (VCCI and VCCV) to respond to changes in VBATT. Since the capacitors only need to change their voltage minimally to respond to changes in VBATT, the controller’s response is essentially instantaneous. Transient Overvoltage Protection from Dropout The MAX1739/MAX1839 are designed to maintain tight control of the transformer primary under all transient conditions. This includes transients from dropout, where VBATT is so low that the controller loses regulation and reaches maximum duty cycle. Backlight designs will want to choose circuit component values to minimize the transformer turns ratio in order to minimize primary-side currents and I2R losses. To achieve this, _______________________________________________________________________________________ 11 MAX1739/MAX1839† Voltage and Current Control Loops The MAX1739/MAX1839 use two control loops. The current control loop regulates the average lamp current. The voltage control loop limits the maximum average primaryside transformer voltage. The voltage control loop is active during the beginning of DPWM on-cycles and in some fault conditions. Limiting the transformer primary voltage allows for a lower transformer secondary voltage rating that can increase reliability and decrease cost of the transformer. The voltage control loop acts to limit the transformer voltage any time the current control loop attempts to steer the transformer voltage above its limit as set by VCTFB (see Sense Resistors). The voltage control loop uses a transconductance amplifier to create an error current based on the voltage between CTFB and the internal reference level (600mV typ) (Figure 2). The error current is then used to charge and discharge CCCV to create an error voltage VCCV. The current control loop produces a similar signal based on the voltage between CSAV and its internal reference level (see the Dimming Range section). This error voltage is called VCCI. The lower of VCCV and VCCI is used with the buck regulator’s PWM ramp generator to set the buck regulator’s duty cycle. 12 REF VL VL 0.6V SYNC CS CTFB CCV CCI CSAV MODE GND CTL/SCL CRF/SDA GMV GMI 500mV 450mV CCV CLAMP PK_DET_CLAMP SUPPLY BUCK ENABLE MINDAC = VL? Y = 1, N = 0 ROYER OSC BUCK REGULATOR PWM CONTROL PWM RAMP GENERATOR PEAK DETECTOR DPWM OSC SMBus LAMP CURRENT AND DPWM CONTROL CS CS DL2 DL1 LX DH BST REF SH/SUS VL BATT MINDAC REF MAX1739/MAX1839† Wide Brightness Range CCFL Backlight Controllers Figure 2. Functional Diagram ______________________________________________________________________________________ Wide Brightness Range CCFL Backlight Controllers The PK_DET_CLAMP circuit limits VCCI to the peaks of the buck-regulator’s PWM ramp generator. As the circuit reaches dropout, VCCI approaches the peaks of the PWM ramp generator in order to reach maximum duty cycle. If VBATT decreases further, the control loop loses regulation and VCCI tries to reach its positive supply rail. The clamp circuit on VCCI keeps this from happening, and VCCI rides just above the peaks of the PWM ramp. As VBATT decreases further, the feed-forward PWM ramp generator loses amplitude and the clamp drags V CCI down with it to a voltage below where VCCI would have been if the circuit was not in dropout. When VBATT is suddenly increased out of dropout, VCCI is still low and maintains the drive on the transformer at the old dropout level. The circuit then slowly corrects and increases VCCI to bring the circuit back into regulation. Buck Regulator The buck regulator uses the signals from the PWM comparator, the current-limit detection on CS, and DPWM signals to control the high-side MOSFET duty cycle. The regulator uses voltage-mode PWM control and is synchronized to the Royer oscillator. A falling edge on SYNC turns on the high-side MOSFET after a 375ns minimum off-time delay. The PWM comparator or the CS current limit ends the on-cycle. Interface Selection Table 1 lists the functionality of SH/SUS, CRF/SDA, and CTL/SCL in each of the three interface modes of the MAX1739/MAX1839. The MAX1739 features both an SMBus digital interface and an analog interface, while the MAX1839 features only the analog interface. Note that MODE can also synchronize the DPWM frequency (see Synchronizing the DPWM Frequency). Dimming Range Brightness is controlled by either the analog interface (see Analog Interface) or the SMBus interface (see SMBus Interface). CCFL brightness is adjusted in three ways: 1) Lamp current control, where the magnitude of the average lamp current is adjusted. 2) DPWM control, where the average lamp current is pulsed to the lamp with a variable duty cycle. 3) A combination of the first two methods. In each of the three methods, a 5-bit brightness code is generated from the selected interface and is used to set the lamp current and/or DPWM duty cycle. The 5-bit brightness code defines the lamp current level with ob00000 representing minimum lamp current and ob11111 representing maximum lamp current. The average lamp current is measured across an external sense resistor (see Sense Resistors). The voltage on the sense resistor is measured at CSAV. The brightness code adjusts the regulation voltage at CSAV (VCSAV). The minimum average VCSAV is VMINDAC/10, and the maximum average is set by the following formula: VCSAV = VREF ✕ 31 / 320 + VMINDAC / 320 which is between 193.75mV and 200mV. Note that if VCSAV does not exceed 100mV peak (which is about 32mV average) for over 2 seconds, the MAX1739/MAX1839 will assume a lamp-out condition and shut down (see Lamp-Out Detection). The equation relating brightness code to CSAV regulation voltage is: VCSAV = VREF ✕ n / 320 + VMINDAC ✕ (32 - n) / 320 where n is the brightness code. To always use maximum average lamp current when using DPWM control, set VMINDAC to VREF. DPWM control works similar to lamp current control in that it also responds to the 5-bit brightness code. A Table 1. Interface Modes DIGITAL INTERFACE ANALOG INTERFACE PIN MODE = VL (MAX1739 only) MODE = REF, VCTL/SCL = 0 = maximum brightness MODE = GND, VCTL/SCL = 0 = minimum brightness SH/SUS SMBus suspend Logic-level shutdown control input CRF/SDA SMBus data I/O Reference input for minimum brightness CTL/SCL SMBus clock input Analog control input to set brightness (range from 0 to CRF/SDA) Reference input for maximum brightness ______________________________________________________________________________________ 13 MAX1739/MAX1839† allow the circuit to operate in dropout at extremely low battery voltages where the backlight’s performance is secondary. All backlight circuit designs can undergo a transient overvoltage condition when the laptop is plugged into the AC adapter and V BATT suddenly increases. The MAX1739/MAX1839 contain a unique clamp circuit on VCCI. Along with the feed-forward circuitry, it ensures that there is not a transient transformer overvoltage when leaving dropout. brightness code of ob00000 corresponds to a 9.375% DPWM duty cycle, and a brightness code of ob11111 corresponds to a 100% DPWM duty cycle. The duty cycle changes by 3.125% per step, except codes ob00000 to ob00011 all produce 9.375% (Figure 3). To disable DPWM and always use 100% duty cycle, set VMINDAC to VL. Note that with DPWM disabled, the equations above should assume VMINDAC = 0 instead of VMINDAC = VL. Table 2 lists MINDAC’s functionality, and Table 3 shows some typical settings for the brightness adjustment. In normal operation, VMINDAC is set between 0 and VREF, and the MAX1739/MAX1839 use both lamp current control and DPWM control to vary the lamp brightness (Figure 4). In this mode, lamp current control regulates the average lamp current during a DPWM oncycle and not the overall average lamp current. Analog Interface and Brightness Code The MAX1739/MAX1839 analog interface uses an internal ADC with 1-bit hysteresis to generate the brightness code used to dim the lamp (see Dimming Range). CTL/SDA is the ADC’s input, and CRF/SCL is its reference voltage. The ADC can operate in either positivescale ADC mode or negative-scale ADC mode. In positive-scale ADC mode, the brightness code increas- es from 0 to 31 as VCTL increases from 0 to VCRF. In negative-scale mode, the brightness scale decreases from 31 to 0 as VCTL increases from 0 to VCRF (Figure 5). The analog interface’s internal ADC uses 1-bit hysteresis to keep the lamp from flickering between two codes. V CTL ’s positive threshold (V CTL(TH) ) is the voltage required to transition the brightness code as V CTL increases and can be calculated as follows: VCTL(TH) = (n + 2) / 33 VCRF (positive-scale ADC mode, MODE = GND) VCTL(TH) = (33 - n) / 33 VCRF (negative-scale ADC mode, MODE = REF) where n is the current selected brightness code. VCTL’s negative threshold is the voltage required to transition the brightness code as VCTL decreases and can be calculated as follows: VCTL(TH) = n / 33 VCRF (positive-scale ADC mode, MODE = GND) VCTL(TH) = (31 - n) / 33 VCRF (negative-scale ADC mode, MODE = REF) Figure 5 shows a graphic representation of the thresholds. CRF/SDA’s and CTL/SCL’s input voltage range is 2.7V to 5.5V. COMBINED POWER LEVEL (BOTH DPWM AND LAMP CONTROL CURRENT) DPWM SETTINGS 100 100 90 90 80 80 COMBINED POWER LEVEL (%) DPWM DUTY CYCLE (%) MAX1739/MAX1839† Wide Brightness Range CCFL Backlight Controllers 70 60 50 40 30 20 10 70 60 50 40 30 20 10 0 0 0 4 8 12 16 20 24 28 32 0 BRIGHTNESS CODE 4 8 12 16 20 24 28 32 BRIGHTNESS CODE Figure 4. Combined Power Level Figure 3. DPWM Settings Table 2. MINDAC Functionality MINDAC = VL DPWM disabled (always on 100% duty cycle). Operates in lamp current control only. (Use VMINDAC = 0 in the equations.) MINDAC = REF DPWM control enabled, duty cycle ranges from 9% to 100%. Lamp current control is disabled (always maximum current). 0 ≤ VMINDAC < VREF The device uses both lamp current control and DPWM. 14 ______________________________________________________________________________________ Wide Brightness Range CCFL Backlight Controllers BRIGHTNESS POSITIVESCALE ADC NEGATIVESCALE ADC SMBus DAC OUTPUT DPWM DUTY CYCLE (%) COMBINED POWER LEVEL (%) Maximum Brightness MODE = GND, VCTL/SCL = VCRF/SDA MODE = REF, VCTL/SCL = 0 Bright [4:0] = ob11111 Full-scale DAC OUTPUT = 195.83mV 100 100 Minimum Brightness MODE = GND, VCTL/SCL = 0, VMINDAC = VREF / 3 MODE = REF, VCTL/SCL = VCRF/SDA, VMINDAC = VREF / 3 Bright [4:0] = ob00000, VMINDAC = VREF / 3 Zero-scale DAC OUTPUT = VMINDAC / 10 9 3 Note: The current-level range is solely determined by the MINDAC-to-REF ratio and is externally set. Synchronizing the DPWM Frequency MODE has two functions: one is to select the interface mode as described in Interface Selection, and the other is to synchronize the DPWM “chopping” frequency to an external signal to prevent unwanted effects in the display screen. To synchronize the DPWM frequency, connect MODE to VL, REF, or GND through a 10kΩ resistor. Then connect a 500pF capacitor from an AC signal source to MODE as shown in Figure 6. The synchronization range is from 32kHz to 100kHz, which corresponds to a DPWM frequency range of 250Hz to 781Hz (128 MODE pulses per DPWM cycle). High DPWM frequencies limit the dimming range. See Loop Compensation for more information concerning high DPWM frequencies. Royer Oscillator MOSFET Drivers The MAX1739/MAX1839 directly drive the two external MOSFETs used in the Royer oscillator. This has many advantages over the traditional method that uses bipolar switching and an extra winding on the transformer. Directly driving the MOSFET eliminates the need for an extra winding on the transformer, which reduces cost and minimizes the size of the transformer. Also, driving the switches directly improves commutation efficiency and commutation timing. Using MOSFETs for the switches typically improves overall inverter efficiency due to lower switch drops. The Royer topology works as a zero voltage crossing (ZVC) detector and switches currents between the two sections of the transformer primary windings. The two windings work alternately, each generating a half wave that is transferred to the secondary to produce the full- wave sinusoidal lamp voltage and current. The MAX1739/MAX1839 detect the zero crossing through the SYNC pin; the threshold is set at 500mV referred to CS and has a typical delay of 50ns. The active switching forces commutation very close to the ZVC point and has better performance than the traditional windingbased ZVC switchover. Commutation can be further 31 30 BRIGHTNESS CODE See Digital Interface for instructions on using the SMBus interface. 29 3 2 1 0 1 33 2 33 3 33 4 33 VCTL VCRF 1 32 33 31 33 30 33 29 33 VCTL VCRF 30 33 31 33 32 33 1 1 33 0 (MODE = GND) 3 33 2 33 (MODE = REF) Figure 5. Brightness Code ______________________________________________________________________________________ 15 MAX1739/MAX1839† Table 3. Brightness Adjustment Ranges (for 33:1 Dimming) MAX1739/MAX1839† Wide Brightness Range CCFL Backlight Controllers VL REF T1 ADC- L1 10k MODE LX MAX1739 MAX1839 MAX1739 MAX1839 SMBus ADC+ R14 SYNC 500pF GND DPWM SYNCHRONIZATION SIGNAL R15 REF R4 CTFB Figure 6. DPWM Synchronization GND R5 optimized using R14 and R15 as shown in Figure 7. The resistor-divider can be used to force commutation as close to the zero-crossing point as possible. POR and UVLO The MAX1739/MAX1839 include power-on reset (POR) and undervoltage lockout (UVLO) features. The POR resets all internal registers, such as DAC output, fault conditions, and all SMBus registers. POR occurs when VL is below 1.5V. The SMBus input logic thresholds are designed to meet electrical characteristic limits for VL as low as 3.5V, but the interface will continue to function down to the POR threshold. The UVLO threshold occurs when VL is below 4.2V (typ) and disables the buck-switch driver. Low-Power Shutdown When the MAX1739/MAX1839 are placed in shutdown, all IC functions are turned off except the 5V linear regulator that powers all internal registers and the SMBus interface (MAX1739). The SMBus interface is accessible in shutdown. In shutdown, the linear regulator output voltage drops to about 4.5V and the supply current is 6µA (typ), which is the required power to maintain all internal register states. While in shutdown, lamp-out detection and buck-switch short-circuit detection latches are reset. The device can be placed into shutdown by either writing to the MODE register (MAX1739 SMBus mode only) or with SH/SUS. Lamp-Out Detection For safety, during a lamp-out condition, the MAX1739/ MAX1839 limit the maximum average primary-side transformer voltage (see Sense Resistors) and shut down the lamp after 2s. 16 Figure 7. Adjusting the ZVC Detection The lamp-out detection circuitry monitors VCSAV and shuts down the lamp if VCSAV does not exceed 75mV (typ) within 2 seconds. This circuitry ignores most pulses under 200ns. However, in some cases, a small capacitor is needed at CSAV to prevent noise from tripping the circuitry. This is especially true in noisy environments and in designs with marginal layout. Ideally, the voltage at CSAV is a half-wave rectified sine wave. In this case, the CSAV lamp-out threshold is as follows: IMIN = IMAX / 6 where IMIN is the CSAV lamp out threshold, and IMAX is the maximum lamp current (see Sense Resistors). Note: The formulas assume a worst-case CSAV lamp-out threshold of 100mV and a maximum CSAV average voltage of 200mV. Use MINDAC or limit the brightness code to prevent setting the lamp current below the CSAV lamp-out threshold. STATUS1 bit sets when the lamp-out detection circuit shuts down the device. Buck-Switch Short Fault Detection and Protection When the buck switch (N1) fails short, there is no voltage limiting on the transformer and the input forces excessive voltage on the transformer secondary. This ______________________________________________________________________________________ Wide Brightness Range CCFL Backlight Controllers Applications Information As shown in the standard application circuit (Figure 8), the MAX1739/MAX1839 regulate the current of a 4.5W CCFL. The IC’s analog voltage interface sets the lamp brightness with a minimum 20:1 power adjustment range. This circuit operates from a wide supply-voltage range of 7V to 24V. Typical applications include notebook, desktop monitor, and car navigation displays. CCFL Specifications To select the correct component values for the MAX1739/MAX1839 circuit, several CCFL parameters (Table 4) and the minimum DC input voltage must be specified. Royer Oscillator Components T1, C6, C7, N2A, and N2B form the Royer oscillator. A Royer oscillator is a resonant tank circuit that oscillates at a frequency dependent on C7, the primary magnetizing inductance of T1 (LP), and the impedance seen by the T1 secondary. Figure 8 shows VIN (5V TO 28V) BATT CCV C9 4.7µF VL C4 N1 DHI C6 D2 C3 CCI BST C5 C2 MAX1739 MAX1839 L1 T1 LX D1 REF R4 C7 C1 VL MINDAC SYNC MODE CTFB CRF/SDA DL2 CTL/SCL DL1 SH/SUS GND CS R5 N2B D5 DIMMING ON/OFF N2A CSAV R13 Figure 8. Standard Application Circuit ______________________________________________________________________________________ 17 MAX1739/MAX1839† increases the circuit’s demand for current but may not be enough to blow the fuse. With the buck switch shorted, the center tap rises above its regulation point, which causes the CCV amplifier’s output (VCCV) to go low. To detect this, the MAX1739/MAX1839 check that VCCV is below 1V at the end of every DPWM period. If this condition persists for over 250ms (or 64 DPWM pulses), the inverter switch commutation is stopped with either DL1 or DL2 on. With the buck switch shorted, this will cause a short circuit with enough current to blow the fuse. If the buck switch is not shorted, then the inverter latches off as in a lamp-out condition. Both buck-switch short and lamp-out detection will clear the STATUS1 bit in the SMBus interface. STATUS1 does not clear immediately but will clear about 2 seconds after the inverter has been forced off (see Digital Interface). Note that once the inverter board fuse has blown, SMBus communications with the part will cease since the MAX1739 will then be without power. MAX1739/MAX1839† Wide Brightness Range CCFL Backlight Controllers a proven application that is useful for a wide range of CCFL tubes and power ranges. Table 5 shows the recommended components for a 4.5W application. MOSFETs The MAX1739/MAX1839 require three external switches to operate: N1, N2A, and N2B. N1 is the buck switch; select a logic-level N-channel MOSFET with low RDSON to minimize conduction losses (100mΩ, 30V typ). Also select a comparable-power Schottky diode for D1. N2A/N2B are the Royer oscillator switches that drive the transformer primary; select a dual-logic-level Nchannel MOSFET with low RDSON to minimize conduction losses (100mΩ, 30V typ). Sense Resistors R4 and R5 sense the transformer’s primary voltage. Figure 9 shows the relationship between the primary and secondary voltage. To set the maximum average secondary transformer voltage, set R5 = 10kΩ, and select R5 according to the following formula: 1.5VS(RMS) R4 = R5 − 1 N where VS is the maximum RMS secondary transformer voltage (above the strike voltage), and N is the turns ratio of the transformer. Table 4. CCFL Specifications SPECIFICATION SYMBOL UNITS CCFL Minimum Strike Voltage (Kick-Off Voltage) VS VRMS CCFL Typical Operating Voltage (Lamp Voltage) VL VRMS CCFL Maximum Operating Current (Lamp Current) IL mARMS fL kHz CCFL Maximum Frequency (Lamp Frequency) DESCRIPTION Although CCFLs typically operate at <550VRMS, a higher voltage (1000VRMS and up) is required initially to start the tube. The strike voltage is typically higher at cold temperatures and at the tube’s end of life. This voltage is set by the combination of the maximum primary voltage (center-tap voltage limit corresponding to VCTFB = 0.6V) and the transformer (T1) turns ratio. Once a CCFL has been struck, the voltage required to maintain light output falls to approximately 550VRMS. Short tubes may operate on as little as 250VRMS. The CCFL operating voltage stays relatively constant, even as the tube’s brightness is varied. The maximum RMS AC current through a CCFL is typically 5mARMS. DC current is not allowed through CCFLs. The maximum lamp current is set by the sense resistor (R13) at the maximum brightness setting. The maximum AC-lamp-current frequency. The MAX1739/ MAX1839 synchronize to the Royer oscillator frequency set by the external components and are designed to operate between 32kHz and 100kHz. Table 5. Components for the Standard Application Circuit DESIGNATION 18 DESCRIPTION RECOMMENDED DEVICE MANUFACTURER L1 47µH, 1.1A inductor CR104-470 Sumida N1 30V, 0.1Ω N-channel MOSFET FDN361AN Fairchild Fairchild N2 30V, 95mΩ dual N-channel MOSFET FDC6561AN T1 8.7µH, 180:1 transformer 5371-T001 (CIUH842 style) Sumida D1 30V, 1A Schottky diode CRS02 Toshiba D2 0.1A Schottky diode BAT54 Fairchild D3 0.1A dual Schottky diode MMBD4148SE Fairchild C6 22pF, 3.1kV capacitor GHM1038-SL-220J-3K Murata C7 0.1µF, 63V, low-dissipation capacitor SMD1812 WIMA ______________________________________________________________________________________ Wide Brightness Range CCFL Backlight Controllers L1 VCT C6 CCFL N = NS/NP NS T1 NP NP D5A T1 TO CTFB MAX1739/MAX1839† VS = VS(RMS) = N ✕ 1.1 ✕ VCT R4 D5B N2A N2B CSAV IL, RMS, MAX = 0.04304 R13 R5 R13 2π ω -NπVCT 2 IL,PK IL,PK IR13, AVG IL,RMS ILAMP NπVCT 2 IR13 πVCT 2 T1 SECONDARY VOLTAGE (PIN 10–PIN 6) T1 PRIMARY-TAP VOLTAGE (PIN 2) VCT is the average DC voltage at center top -IL,PK 2π ω 2π ω 2π ω Figure 9. Transformer Primary/Secondary Voltage Relationship Figure 10. Current-Sense Waveforms The MAX1739/MAX1839 regulate the average current through the CCFL. The current is sensed through the sense resistor (R13) at CSAV. The voltage at CSAV is the half-wave rectified representation of the current through the lamp (Figure 10). The MAX1739/MAX1839 regulate the average voltage at CSAV (IR13, AVG ✕ R13) and are controlled by either the analog interface or the SMBus interface. To set the maximum lamp current, determine R13 as follows: R13 = 0.4304 / IL,RMS,MAX where IL,RMS,MAX is the maximum RMS lamp current. MINDAC and the wave shape influence the actual maximum RMS lamp current. Use an RMS current meter to make final adjustments to R13. increase the delay to strike voltage in DPWM and can cause loss of regulation in the extreme case. Note that very large CCCV can do the same thing. C6 not only affects loop compensation, but it also affects the waveform shape, overall efficiency, and the maximum necessary secondary transformer voltage. Low values of C6 improve loop stability, especially in systems using a CCFL with a large difference between its restrike voltage and its operating voltage (characteristic of long narrow CCFLs) during DPWM. A low value of C6 also improves stability when the lamp’s operating voltage drops with an increase in lamp current. However, low values of C6 increase the maximum necessary transformer voltage. C7 interacts with C6 and affects the Royer frequency, Royer Q value, and overall efficiency. CCCV sets the speed of the voltage control loop that affects DPWM transients and operation in fault conditions. If DPWM is not used, the voltage control loop should only be active during fault conditions. The standard value of CCCV is 3300pF. Use the smallest value of CCCV necessary to set an acceptable fault transient response and not cause excessive ringing at the beginning of a DPWM pulse. Note that the worst-case fault Loop Compensation CCCI sets the speed of the current control loop that is used during startup, maintaining lamp current regulation, and during transients caused by changing the lamp current setting. The standard C CCI value is 0.01µF. Larger values limit lamp current overshoot. Smaller values speed up its response to changes in the lamp current setting, but can lead to instability for extremely small values. Very large values of C CCI ______________________________________________________________________________________ 19 MAX1739/MAX1839† Wide Brightness Range CCFL Backlight Controllers transient that CCCV is designed to protect against is open tube at the beginning of DPWM pulses. Large CCCV values reduce transient overshoots, but can cause loss of regulation at low DPWM duty cycles by increasing the delay to strike voltage. Smaller values of C CCV allow quicker DPWM startups and faster response to fault conditions. Very small values of CCCV make the circuit more susceptible to ringing, and in extreme cases may cause instability. Some ringing is expected between the Royer oscillator and the buck inductor. Some of the ringing can be suppressed by adding a capacitor in parallel with R5. This capacitor should be chosen such that: 1 / (2 ✕ π ✕ R5 ✕ C) = ringing frequency When using high DPWM frequencies and low DPWM duty cycles, the DPWM on-time is reduced. In some cases, this causes the lamp current transient to exceed the DPWM on-time. In this case, the MAX1739/ MAX1839 lose regulation and the lamp current never reaches the lamp current set point. Supply rejection while operating in this condition is degraded. If the DPWM on-time is short enough, the lamp current does not have enough time to reach the lamp-out threshold and causes a lamp-out detection. To prevent this, decrease the turn-on transient duration (by lowering CCCV), increase the DPWM duty cycle (by limiting the brightness code), or decrease the DPWM frequency (see Synchronizing the DPWM Frequency). DPWM or other “chopping” methods can cause audible noise from some transformers. The transformer should be carefully designed to avoid such behavior. through a signal-level Schottky diode to VL, and bypass it to LX with a 0.1µF ceramic capacitor. This circuit delivers the necessary power to drive N1 as shown in Figure 8. If a higher gate capacitance MOSFET is used, the size of the bypass capacitor must be increased. The current need at BST is as follows: IBST = 1mA d + QT ✕ f where d is the buck controller duty cycle (98% max), QT is the MOSFET total gate charge, and f is twice the Royer oscillator frequency. The maximum current through D2 (ID) is: ID = IBST / (1 - d) D5A and D5B are used to generate the current-sense voltage across R13. The current through these diodes is the lamp current; use a dual-series signal-level diode. Bypassing and Board Layout Connect C4 from VL to GND as close as possible with dedicated traces that are not shared with other signal paths. The ground lines should terminate at the GND end of C4: quiet ground, power ground, and lamp current-sense ground. Quiet ground is used for REF, CCV, R5, and MINDAC (if a resistor-divider is used). The power ground goes from the ground of C4 directly to the ground side of C9. Power ground should also supply the return path for D1, N2, and the buck currentsense resistor (from CS to GND, if used). The ground path for R13 should be separate to ensure that it does not corrupt quiet ground and it is not affected by DC drops in the power ground. Refer to the MAX1739 EV kit for an example of good layout. Dimming Range Digital Interface (MAX1739) The external components required to achieve a dimming range are highly dependent on the CCFL used. The standard application circuit uses a CCFL with stringent requirements. To achieve a 20:1 dimming range, the standard circuit drops slightly more voltage across C6 as it does across the CCFL at the full lamp current setting. This ensures good stability in that circuit with VMINDAC as low as 1V. To further increase the dimming range when using this CCFL, C6 must be increased, which increases the maximum secondary transformer voltage and requires a transformer with a higher voltage rating. Other components (such as the primary transformer inductance and C7) may also need to be adjusted to maintain good waveforms, Royer efficiency, and the desired Royer frequency. With MODE connected to VL, the CRF/SDA and CTL/SCL pins no longer behave as analog inputs; instead, they function as SMBus-compatible 2-wire digital interfaces. CRF/SDA is the bidirectional data line, and CTL/SCL is the clock line of the 2-wire interfaces corresponding, respectively, to the SMBDATA and SMBCLK lines of the SMBus. The MAX1739 uses the write-byte, read-byte, and receive-byte protocols (Figure 11). The SMBus protocols are documented in System Management Bus Specification v1.08 and are available at www.sbs-forum.org. The MAX1739 is a slave-only device and responds to the 7-bit address 0b0101101 (i.e., with the RW bit clear indicating a write, this corresponds to 0x5A). The MAX1739 has three functional registers: a 5-bit brightness register (BRIGHT4–BRIGHT0), a 3-bit shutdown mode register (SHMD2–SHMD0), and a 2-bit status register (STATUS1–STATUS0). In addition, the device Other Components The high-side MOSFET driver is powered by the external boosting circuit formed by C5 and D2. Connect BST 20 ______________________________________________________________________________________ Wide Brightness Range CCFL Backlight Controllers MAX1739/MAX1839† Write-Byte Format S ADDRESS WR ACK COMMAND ACK DATA ACK 7 bits 1b 1b 8 bits 1b 8 bits 1b Slave Address Command Byte: selects which register you are writing to P Data Byte: data goes into the register set by the command byte Read-Byte Format S ADDRESS WR ACK COMMAND ACK 7 bits 1b 1b 8 bits 1b Slave Address Command Byte: selects which register you are reading from Send-Byte Format S S ADDRESS RD ACK DATA /// 7 bits 1b 1b 8 bits 1b Slave Address: repeated due to change in dataflow direction Data Byte: reads from the register set by the command byte Receive-Byte Format ADDRESS WR ACK COMMAND ACK 7 bits 1b 1b 8 bits 1b P S ADDRESS RD ACK DATA /// 7 bits 1b 1b 8 bits 1b Command Byte: sends command with no data; usually used for oneshot command S = Start condition P = Stop condition P Shaded = Slave transmission Ack= Acknowledged = 0 /// = Not acknowledged = 1 WR = Write = 0 RD = Read =1 Slave Address P Data Byte: reads data from the register commanded by the last read-byte or write-byte transmission; also used for SMBus Alert Response return address Figure 11. SMBus Protocols has three identification (ID) registers: an 8-bit chip ID register, an 8-bit chip revision register, and an 8-bit manufacturer ID register. The CRF/SDA and CTL/SCL pins have Schmidt-triggered inputs that can accommodate slow edges; however, the rising and falling edges should still be faster than 1µs and 300ns, respectively. Communication starts with the master signaling the beginning of a transmission with a START condition, which is a high-to-low transition on CRF/SDA while CTL/SCL is high. When the master has finished communicating with the slave, the master issues a STOP condition (P), which is a low-to-high transition on CRF/SDA while CTL/SCL is high (Figures 10, 11). The bus is then free for another transmission. Figures 12 and 13 show the timing diagram for signals on the 2-wire interface. The address byte, command byte, and data byte are transmitted between the START and STOP conditions. The CRF/SDA state is allowed to change only while CTL/SCL is low, except for the START and STOP conditions. Data is transmitted in 8bit words and is sampled on the rising edge of CTL/SCL. Nine clock cycles are required to transfer each byte in or out of the MAX1739 since either the master or the slave acknowledges the receipt of the correct byte during the ninth clock. If the MAX1739 receives its correct slave address followed by RW = 0, it expects to receive 1 or 2 bytes of information (depending on the protocol). If the device detects a start or stop condition prior to clocking in the bytes of data, it considers this an error condition and disregards all of the data. If the transmission is completed correctly, the registers are updated immediately after a STOP (or RESTART) condition. If the MAX1739 receives its correct slave address followed by RW = 1, it expects to clock out the register data selected by the previous command byte. SMBus Commands The MAX1739 registers are accessible through several different redundant commands (i.e., the command byte in the read-byte and write-byte protocols), which can ______________________________________________________________________________________ 21 MAX1739/MAX1839† Wide Brightness Range CCFL Backlight Controllers A tLOW B tHIGH C E D F G I H J K L M SMBCLK SMBDATA tHD:STA tSU:STA tSU:DAT A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLAVE D = R/W BIT CLOCKED INTO SLAVE E = SLAVE PULLS SMBDATA LINE LOW tHD:DAT tHD:DAT tSU:STO tBUF J = ACKNOWLEDGE CLOCKED INTO MASTER K = ACKNOWLEDGE CLOCK PULSE L = STOP CONDITION, DATA EXECUTED BY SLAVE M = NEW START CONDITION F = ACKNOWLEDGE BIT CLOCKED INTO MASTER G = MSB OF DATA CLOCKED INTO SLAVE H = LSB OF DATA CLOCKED INTO SLAVE I = SLAVE PULLS SMBDATA LINE LOW Figure 12. SMBus Write Timing A B tLOW C D E F G H tHIGH J I K SMBCLK SMBDATA tSU:STA tHD:STA A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLAVE D = R/W BIT CLOCKED INTO SLAVE tSU:DAT tHD:DAT E = SLAVE PULLS SMBDATA LINE LOW F = ACKNOWLEDGE BIT CLOCKED INTO MASTER G = MSB OF DATA CLOCKED INTO MASTER H = LSB OF DATA CLOCKED INTO MASTER tSU:DAT tSU:STO tBUF I = ACKNOWLEDGE CLOCK PULSE J = STOP CONDITION K = NEW START CONDITION Figure 13. SMBus Read Timing be used to read or write the brightness, SHMD, status, or ID registers. Table 6 summarizes the command byte’s register assignments, as well as each register’s power-on state. The MAX1739 also supports the receive-byte protocol for quicker data transfers. This protocol accesses the register configuration pointed to by the last command byte. Immediately after power-up, the data byte returned by the receive-byte protocol is the contents of the brightness register, left justified (i.e., BRIGHT4 will be in the MSB position of the data byte) with the remaining bits containing a 1, STATUS1, and STATUS0. 22 This gives the same result as using the read-byte protocol with a 0b10XXXXXX (0x80) command. Use caution with shorter protocols in multimaster systems since a second master could overwrite the command byte without informing the first master. During shutdown, the serial interface remains fully functional. The part also supports limited read/write-word protocol. Read-word works similar to read-byte except the second byte returned is 0xFF. Write-word also works similar to writebyte. The second data byte is acknowledged and updated after the first data byte is acknowledged and updated. ______________________________________________________________________________________ Wide Brightness Range CCFL Backlight Controllers R OR W PROTOCOL DATA REGISTER BIT ASSIGNMENT COMMAND POR BYTE* STATE BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) Read and Write 0x01 0b0XXX XX01 0x17 0 0 0 BRIGHT4 (MSB) BRIGHT3 BRIGHT2 BRIGHT1 BRIGHT0 (LSB) Read and Write 0x02 0b0XXX XX10 0xF9 STATUS1 STATUS0 1 1 1 SHMD2 SHMD1 SHMD0 Read Only 0x03 0b0XXX XX11 0x96 ChipID7 1 ChipID6 0 ChipID5 0 ChipID4 1 ChipID3 0 ChipID2 1 ChipID1 1 ChipID0 0 Read Only 0x04 0b0XXX XX00 0x00 ChipRev7 ChipRev6 ChipRev5 ChipRev4 ChipRev3 ChipRev2 ChipRev1 0 0 0 0 0 0 0 Read and Write 0x40 0b10XX XXXX 0xBF BRIGHT4 (MSB) BRIGHT3 BRIGHT2 BRIGHT1 BRIGHT0 (LSB) 1 STATUS1 STATUS0 Read Only 0xFE 0b11XX XXX0 0x4D MfgID7 0 MfgID6 1 MfgID5 0 MfgID4 0 MfgID3 1 MfgID2 1 MfgID1 0 MfgID0 1 Read Only 0xFF 0b11XX XXX1 0x96 ChipID7 1 ChipID6 0 ChipID5 0 ChipID4 1 ChipID3 0 ChipID2 1 ChipID1 1 ChipID0 0 ChipRev0 0 *The hexadecimal command byte shown is recommended for maximum forward compatibility with future MAXIM products. Brightness Register [BRIGHT4–BRIGHT0] (POR = 0b10111) Shutdown-Mode Register [SHMD2–SHMD0] (POR = 0b001) The 5-bit brightness register corresponds with the 5-bit brightness code used in the dimming control (see Dimming Range). BRIGHT4–BRIGHT0 = 0b00000 sets minimum brightness, and BRIGHT4–BRIGHT0 = 0b11111 sets maximum brightness. The SMBus interface does not control whether the device regulates the current by analog dimming, DPWM dimming, or both; this is done by MINDAC (Table 2). The 3-bit shutdown-mode register configures the operation of the device when the SH/SUS pin is toggled as described in Table 7. The shutdown-mode register can also be used to shut off directly the CCFL, regardless of the SH/SUS state (Table 8). ______________________________________________________________________________________ 23 MAX1739/MAX1839† Table 6. Commands Description MAX1739/MAX1839† Wide Brightness Range CCFL Backlight Controllers Status Register [STATUS1–STATUS0] (POR = 0b11) The status register returns information on fault conditions. If a lamp is not connected to the secondary of the transformer, the MAX1739 will detect that the lamp current has not exceeded the CSAV detection threshold and after 2 seconds will clear the STATUS1 bit (see Lamp-Out Detection). The STATUS1 bit is latched; i.e., it will remain 0 even if the lamp-out condition goes away. When STATUS1 = 0, the lamp is forced off. STATUS0 reports 1 as long as no overcurrent conditions are detected. If an overcurrent condition is detected in any given DPWM period, STATUS0 is cleared for the duration of the following DPWM period. If an overcur- rent condition is not detected in any given DPWM period, STATUS0 is set for the duration of the following digital DPWM period. Forcing the CCFL lamp off by entering shutdown, writing to the mode register, or by toggling SH/SUS sets STATUS1. ID Registers The ID registers return information on the manufacturer, the chip ID, and the chip revision number. The MAX1739 is the first-generation advanced CCFL controller, and its ChipRev is 0x00. Reading from the MfgID register returns 0x4D, which is the ASCII code for “M” (for Maxim); the ChipID register returns 0x96. Writing to these registers has no effect. Table 7. SHMD Register Bit Descriptions BIT NAME POR STATE DESCRIPTION 2 SHMD2 0 SHMD2 = 1 forces the lamp off and sets STATUS1. SHMD2 = 0 allows the lamp to operate, though it may still be shut down by the SH/SUS pin (depending on the state of SHMD1 and SHMD0). 1 SHMD1 0 When SH /SUS = 0, this bit has no effect. SH/SUS = 1 and SHMD1 = 1 forces the lamp off and sets STATUS1. SH /SUS = 1 and SHMD1 = 0 allow the lamp to operate, though it may still be shut down by the SHMD2 bit. 0 SHMD0 1 When SH /SUS = 1, this bit has no effect. SH /SUS = 0 and SHMD0 = 1 forces the lamp off and sets STATUS1. SH /SUS = 0 and SHMD0 = 0 allows the lamp to operate, though it may still be shut down by the SHMD2 bit. Table 8. SH/SUS and SHMD Register Truth Table SH/SUS SHMD2 SHMD1 SHMD0 0 0 X 0 Operate 0 0 X 1 Shutdown, STATUS1 set 1 0 0 X Operate 1 0 1 X Shutdown, STATUS1 set 1 X X Shutdown, STATUS1 set X X = Don’t care OPERATING MODE Table 9. Status Register Bit Descriptions (Read Only/Writes Have No Effect) BIT NAME POR STATE 1 STATUS1 1 STATUS1 = 0 means that a lamp-out condition has been detected. The STATUS1 bit stays clear even after the lamp-out condition has gone away. The only way to set STATUS1 is to shut off the lamp by programming the mode register or by toggling SH/SUS. 0 STATUS0 1 STATUS0 = 0 means that an overcurrent condition was detected during the previous digital PWM period. STATUS0 = 1 means that no overcurrent condition was detected during the previous digital PWM period. 24 DESCRIPTION ______________________________________________________________________________________ Wide Brightness Range CCFL Backlight Controllers Chip Information TRANSISTOR COUNT: 7194 TOP VIEW 20 BATT REF 1 MINDAC 2 19 DH CCI 3 18 LX 17 BST CCV 4 SH 5 MAX1839 16 VL CRF 6 15 GND CTL 7 14 CS MODE 8 13 DL1 CSAV 9 12 DL2 CTFB 10 11 SYNC QSOP ______________________________________________________________________________________ 25 MAX1739/MAX1839† Pin Configurations (continued) Wide Brightness Range CCFL Backlight Controllers QSOP.EPS MAX1739/MAX1839† Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.