SLUS485A – JULY 2001 – REVISED NOVEMBER 2001 FEATURES D Synchronous or Nonsynchronous Operation D Dual Output and Control Stages D BiCMOS Technology D Accurate Current Control with 2-mA Typical Supply Current DESCRIPTION D Analog or Digital Low-Frequency Dimming D D D D APPLICATIONS D Portable PCs D Desktop LCD Monitors D Internet Appliances Capability Open Lamp Protection with Voltage Clamp 4.5-V to 25-V Operation PWM Frequencies Synchronized to External Resonant Tanks TSSOP-16 (PW) Package TYPICAL APPLICATION VIN VIN VIN Design goals for a cold cathode fluorescent lamp (CCFL) converter used for a liquid crystal display (LCD) monitor application include small size, high efficiency, and low cost. The UCC2974/UCC3974 CCFL controllers provide the necessary circuit blocks to implement a highly efficient LCD monitor backlight supply in a small 16-pin TSSOP package. The device features two control stages for operating independent resonant tanks for multi-lamp designs. The BiCMOS controller typically consumes less than 2-mA of operating current, improving overall system efficiency. External parts count is minimized and system cost is reduced by integrating such features as dual PWM driver stages, open lamp protection, overvoltage clamp, and synchronization circuitry between the buck and push-pull stages. The device operates in both analog and low-frequency dimming modes. UCC3974 OUT1 OUT2 16 2 VIN 3 BUCK1 BUCK2 14 4 COMP1 CBP 13 5 FB1 6 RC 7 RD 8 DIM GND COMP2 15 12 MIRROR CHANNEL 1 BRIGHT 1 FB2 11 MODE 10 LFDSYNC 9 SYNC UDG–01023 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated !"# $"%&! '#( '"! ! $#!! $# )# # #* "# '' +,( '"! $!# - '# #!# &, !&"'# # - && $## ( www.ti.com 1 SLUS485A – JULY 2001 – REVISED NOVEMBER 2001 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, Input voltage range, VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 V BUCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to VBAT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.3 V Mode maximum forced current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 µA Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ Unless otherwise specified, all voltages are with respect to GND. AVAILABLE OPTIONS TJ PACKAGE PW§ (SSOP) –40_C to 85_C UCC2974PW 0_C to 70_C UCC3974PW § This package is available taped and reeled. To order this packaging option, add an R suffix to the part number. (e.g. UCC2974PWR) DISSIPATION RATING TABLE PACKAGE 16-pin PW with solder TA ≤ 25°C 775 mW DERATING FACTOR 6.2 mW/°C TA = 70°C 495 mW TA = 85°C 402 mW recommended operating conditions MIN Supply voltage, VIN NOM MAX UNIT 4.5 25 V Mode voltage 0 4.3 V DIM voltage 0 3.5 V LFDSYNC amplitude 0 4.5 V UCC3974 PW PACKAGE (TOP VIEW) UCC2974 PW PACKAGE (TOP VIEW) OUT1 VIN BUCK1 COMP1 FB1 RC RD DIM 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 OUT2 GND BUCK2 CBP COMP2 FB2 MODE LFDSYNC ACTUAL SIZE (5,10mm x 6,60mm) www.ti.com OUT1 VIN BUCK1 COMP1 FB1 RC RD DIM 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 OUT2 GND BUCK2 CBP COMP2 FB2 MODE LFDSYNC SLUS485A – JULY 2001 – REVISED NOVEMBER 2001 electrical characteristics over recommended operating virtual junction temperature range, TA = 0_C to 70_C for the UCC3974, TA = –40_C to 85_C, for the UCC2974, TA = TJ. VIN = VBUCK = 12 V, MODE = OPEN (unless otherwise noted) supply current PARAMETER IIN VIN supply s ppl ccurrent rrent UVLO threshold voltage TEST CONDITIONS MIN 12 V ≤ VIN ≤ 25 V VIN = 12 V, LOW to HIGH MODE < 0.425 V UVLO hysteresis voltage TYP MAX 1.7 3 UNIT mA 300 500 µA 3.6 4 4.4 V 35 120 200 mV MIN TYP MAX UNIT 8 10.5 13 V mV output PARAMETER TEST CONDITIONS High-level output voltage 12 V ≤ VIN ≤ 25 V Low-level output voltage MODE = 0.5 V, 50 200 Rise time CL = 1 nF 170 350 Fall time CL = 1 nF 140 300 MIN TYP MAX 45 ISINK = 1 mA ns oscillator PARAMETER TEST CONDITIONS Free-running oscillator frequency 12 V ≤ VIN ≤ 25 V, BUCK = VIN 30 Free-running synchronizable oscillator frequency 12 V ≤ VIN ≤ 25 V, BUCK = VIN–3 62 Maximum duty cycle FB = 1 V Minimum duty cycle FB = 2 V BUCK input bias current Zero detect threshold voltage UNIT 60 220 kH kHz 100% 0% BUCK = VIN = 12 V 3 10 BUCK = VIN = 25 V 3 10 –2.4 –1.7 –1.1 V UNIT Measured at BUCK with respect to VIN, 12 V ≤ VIN ≤ 25 V A µA error amplifier PARAMETER Input voltage Line regulation voltage MIN TYP MAX COMP = FB, TEST CONDITIONS 0_C ≤ TA ≤ 70_C 1.465 1.5 1.535 COMP = FB, –40_C ≤ TA ≤ 85_C 1.455 1.5 1.545 12 V ≤ VIN ≤ 25 V Input bias current Open loop gain High-level output voltage FB = 1 V, Low-level output voltage FB = 2 V, ISOURCE = 50 µA ISINK = 50 µA Output source current FB = 1 V, COMP = 2 V Output sink current FB = 2 V, COMP = 2 V Unity gain bandwidth TJ = 25C, See Note 1 NOTE 1: V 1 5 mV 100 250 nA 60 80 3.5 3.7 4.2 dB 0.15 0.35 –1.2 –0.3 V mA 45 90 µA 2 5 MHz Ensured by design, not production tested. www.ti.com 3 SLUS485A – JULY 2001 – REVISED NOVEMBER 2001 electrical characteristics over recommended operating virtual junction temperature range, TA = 0_C to 70_C for the UCC3974, TA = –40_C to 85_C, for the UCC2974, TA = TJ. VIN = VBUCK = 12 V, MODE = OPEN (unless otherwise noted) mode select PARAMETER TEST CONDITIONS MIN TYP MAX 0.425 0.500 0.575 Output enable threshold voltage 0.85 1.00 1.15 Open lamp detect enable voltage threshold 2.75 3 3.25 3.8 4.0 4.1 Enable threshold voltage Low-frequency dimming (LFD) voltage threshold UNIT V MODE output current MODE = 0.5 V 3.3 5.0 6.8 µA MODE clamp voltage MODE = OPEN 4.0 4.2 4.4 V low-frequency dimming PARAMETER MIN TYP MAX Duty cycle RC = 400 kΩ, CLFD = 10 nF, TEST CONDITIONS RD = 20 kΩ, DIM < 0.5 V 6% 10% 12% Maximum duty cycle RC = 400 kΩ, CLFD = 10 nF, RD = 20 kΩ, DIM > 3.1 V 100% Free-running oscillator frequency RC = 400 kΩ, CLFD = 10 nF RD = 20 kΩ, Synchronized oscillator frequency RC = 400 kΩ, RD = 20 kΩ, CLFD = 10 nF, FLFDSYNC = 400 Hz at VLFDSYNC = 2.25 V UNIT 200 Hz 400 open lamp PARAMETER Open lamp detect threshold voltage Voltage clamp detect threshold voltage MIN TYP MAX VIN = 12 V, Measured at VBUCK wrt VIN TEST CONDITIONS –8.5 –7.8 –7.0 VIN = 25 V, Measured at VBUCK wrt VIN –8.6 –7.8 –6.9 Measured at VBUCK –9.6 –8.75 –8.0 NOTES: 1: Ensured by design, not production tested. 4 www.ti.com UNIT V SLUS485A – JULY 2001 – REVISED NOVEMBER 2001 Terminal Functions TERMINAL NAME NO. DESCRIPTION I/O I Voltage g sense for the resonant tank. BUCK1 3 BUCK2 14 I CBP 13 O Internally generated low-voltage supply. Bypass to GND with 0.1-µF bypass coordinator. COMP1 4 O Outputs of the error amplifiers for the two channels. COMP2 12 O DIM 8 I Reference signal applied to the LFD PWM that determines the LFD duty cycle. FB1 5 I Inverting g inputs of the error amplifiers. FB2 11 I GND 15 – Power supply return. LFDSYNC 9 I 2.5-V logic-compatible pin used to synchronize the LFD oscillator. MODE 10 I Start-up timing control. OUT1 1 O OUT2 16 O FET drive outputs for the two channels. The pin is driven between GND and internal voltage g (typically 12 V). RC 6 O RD 7 O VIN 2 I Connection for the low-frequency dimming (LFD) charge resistor. The other terminal of the resistor is connected to the LFD capacitor, CLFD. Connection for low-frequency dimming (LFD) discharge resistor, RD. The other terminal of the resistor is connected to the LFD capacitor, CLFD. LFD frequency us user programmable by varying RC, RD and CFLD. Power supply input. 4.5 V to 25 V. detailed pin descriptions DIM – The range is approximately 0.5 V to 3 V for the programmed minimum 100% duty cycle. If the LFDSYNC pin is pulled above 2.25 V before MODE crosses the LFD enable threshold and is held high, the function of DIM changes from an analog voltage, which determines the LFD duty cycle, to a digital signal (2.5-V logic compatible) which turns the lamps on or off directly. This allows users to implement their own LFD solution and easily interface it to the UCC3974. Pulling this pin above 3.0 V (weak internal pull-up device is provided) causes the LFD section of the device to provide 100% LFD duty cycle. LFDSYNC – This 2.5-V logic compatible pin is used to synchronize the LFD oscillator. A positive pulse restarts the LFD ramp. Weak internal pull-down device provided. This pin must be set high when digital LFD mode control is required. MODE – This pin controls the start-up timing for the device. A capacitor is connected from this pin to ground and has a constant current forced into it. The pin voltage controls the state of the device. When the system has a power cycle, the pin is discharged to ground.. MODE PIN VOLTAGE FUNCTION VMODE < 0.5 V VMODE > 0.5 V All circuitry is disabled. VMODE > 1.0 V VMODE > 3.0 V Output driver is enabled. VMODE > 4.0 V Enable low-frequency dimming (LFD). Internal circuitry is enabled. Enable open lamp detection circuitry. BUCK1/BUCK2 – These pins are used to sense the voltage on the resonant tank. This voltage is used for synchronizing the internal high-frequency oscillators with the resonant tanks. This voltage is also used to detect an open lamp condition when MODE is above 3 V. www.ti.com 5 SLUS485A – JULY 2001 – REVISED NOVEMBER 2001 APPLICATION INFORMATION functional block diagram VIN CBP VIN 13 2 INTERNAL REGULATOR OPEN LAMP DETECTOR BUCK1 3 VREG UVLO 1.5 + ZERO DETECTOR 1.0 4–BIT COUNTER AND LOGIC 40 kHz TO 200 kHZ SYNC OVERFLOW VOLTAGE CLAMP OPEN LAMP LFD–PWM + UVLO UVLO OUT1 1 14 BUCK2 OSCILLATOR + VDRV VIN S Q R Q SAME AS OTHER CHANNEL OPEN LAMP OE VINT Q Q S SD + R R DOMINANT FB1 5 16 OUT2 1.5 + EA1 11 FB2 LFD–PWM COMP1 4 12 COMP2 LFD SECTION LFD OSCILLATOR & LOGIC SD 5 µA OE VINT + OLB 1.0 LFD–EN + PRE–CON LFD–EN MODE SELECT 8 9 DIM LFDSYNC 7 6 RT2 RT1 10 MODE UDG–01021 general description The UCC3974 extends the capabilities of the UCC3972 and UCC3973 backlight controllers. The basic functionality is the same as that for the UCC3972; a buck controlled current source feeding a royer oscillator CCFL circuit. As such the application information for the UCC3972 that pertains to the royer oscillator, buck controller and CCFL circuit in general apply to the UCC3974. Also, this device implements a voltage clamping scheme, similar to that of the UCC3973, using an internal current source to bias up the FB pin and thereby limiting the current available to the royer stage. This limits the voltage to which the secondary side of the transformer is exposed. The extensions this device provides are two separately controlled channels to be used with two separate royer stages, and integrated low-frequency dimming (LFD) control . 6 www.ti.com SLUS485A – JULY 2001 – REVISED NOVEMBER 2001 VIN VIN T1 T2 C3 C8 R2 750Ω R6 750Ω Q2 Q3 Q1 C2 33 pF 3 kV VIN 100µF 35 V VIN VIN D2 D3 100µF 35 V Q5 UCC3974 1 OUT1 R10 10Ω 2 VIN 100µF 35 V OUT2 14 CBP 13 5 FB1 COMP2 12 6 RT1 FB2 11 7 RT2 MODE 10 C7 R8 200 kΩ R4 20 kΩ R11 10 kΩ BRIGHT Q6 C8 1µF 4 COMP1 C5 10 nF L2 100µH GND 15 3 OUT1 R1 750 Ω R9 10Ω OUT2 16 C4 R3 D1 C9 33 pF 3 kV Q4 8 DIM LFDSYNC 9 R5 R7 750 Ω C6 1 µF D4 R12 10 kΩ SYNC UDG–01020 Figure 1. Typical Dual-Channel Application low-frequency dimming (LFD) The low-frequency dimming section of the device is implemented as either a low frequency pulse width modulator (PWM) or as a direct digital input. In either case, the DIM pin is the controlling input. The type of DIM input is determined at startup. As the MODE pin transitions through the LFD_ENABLE threshold, the LFDSYNC pin is observed. When this pin is high, the DIM pin is a 2.5-V compatible logic input. When the DIM pin is high, the output is enabled. When it is low the output is disabled. The user is required to provide the correct frequency and duty ratio to the DIM pin in this mode. To change the mode of operation without power cycling the device, the MODE pin must be brought below the LFD_ENABLE threshold and then brought above it with the LFDSYNC pin held in the desired state. To use DIM as an analog input, the LFDSYNC pin must be low when mode crosses the LFD_ENABLE threshold. In this mode, DIM becomes an analog input that varies the amount of time that the lamp is on during the period of the LFD oscillator. From 0.5 V to 3 V applied to the DIM pin varies the lamp on duty cycle from the programmed minimum to 100%. NOTE: The analog dimming signal is senitive to coupled noise from the lamps. Noise on this line will be seen as lamp flicker. It is highly reccommended that precautions be taken to prevent noise coupling to this signal for optimum results. Applying a pulse train to the LFDSYNC pin will synchronize the LFD oscillator to that pulse train. The frequency of the applied pulse train must be higher than the free running frequency of the oscillator. www.ti.com 7 SLUS485A – JULY 2001 – REVISED NOVEMBER 2001 APPLICATION INFORMATION VIN T1 C3 R2 Q2 Q1 C1 VIN D2 L1 UCC3974 Q5 1 OUT1 OUT2 16 2 VIN GND 15 3 OUT1 R3 OUT2 14 C4 4 COMP1 D1 R1 5 FB1 COMP2 12 6 RT1 FB2 11 7 RT2 MODE 10 8 DIM LFDSYNC 9 R8 C5 10 nF R4 BRIGHT C6 UDG–01022 SYNC Figure 2. Typical Single-Channel Application 8 C8 CBP 13 www.ti.com SLUS485A – JULY 2001 – REVISED NOVEMBER 2001 APPLICATION INFORMATION low-frequency dimming oscillator The oscillator for the LFD section of the device is an R-C relaxation oscillator with programmable upslope and downslope on its timing ramp. Figure 3 shows a simplified LFD oscillator diagram that illustrates the principle. The charge time for the timing capacitor, CT is the time it takes to charge that capacitor from 0.5 V to 3 V from a 4.2-V source through RC. This time is: t c + 1.126 R C C T (1) The discharge time is the time it takes to discharge the CT capacitor from 3 V to 0.5 V through RD connected to GND. This time is: t + 1.792 d R C D T (2) The period of the LFD oscillator is simply the sum of the charge and discharge times, or T+C T ǒ1.126 R ) 1.792 C R Ǔ D (3) The minimum duty cycle of the LFD PWM when operating in this mode is: d min t + d T (4) 4.3 4.3 RCRC 3.0 CHARGE 6 0.5 CT 3.0 RD 7 RD + + DISCHARGE R Q S Q 0.5 0.0 tD tC T UDG–01025 Figure 3. LFD Oscillator www.ti.com 9 SLUS485A – JULY 2001 – REVISED NOVEMBER 2001 APPLICATION INFORMATION CT DIM LAMP ON LFD–PWM LAMP OFF UDG–01024 Figure 4. LFD Waveforms Note from the Figure 4 that the LFD-PWM output is turned on at the start of the discharge cycle and is turned off when CT crosses the DIM signal or at the start of the charge cycle if DIM is less than the valley voltage of 0.5 V. The LFD oscillator runs free at some frequency determined by the external timing components. The LFD oscillator can be synchronized to a system clock signal. by applying this clock signal to the LFDSYNC pin. The signal must not be applied during power up since the MODE pin’s crossing of the LFD_ENABLE threshold determines the function DIM takes on. If the synchronization signal is applied during power up, unpredictable results may occur. The synchronization frequency should be fairly close to (but higher than) the free run frequency of the oscillator. The operating range for the DIM signal is reduced when synchronizing the LFD oscillator just as with any other PWM. A synchronization pulse causes termination of the current charge cycle and starts a discharge. The ratio of free run to synchronization frequencies is the reduction factor for DIM’s operating range. For instance if the free-run frequency is 90% of the synchronization frequency, DIM is active over the 0.5-V to 2.75-V range instead of the 0.5-V to 3-V range. As a general recommendation, the free-run frequency should be kept within the 100-Hz to 1-kHz range, and synchronization should be limited to 120% of the free-run frequency to preserve control range on DIM. output driver The OUT1 and OUT2 pins are designed to directly drive small power MOSFETs. Output drive capability is limited by the 50-Ω maximum resistance of the driver. For large FETs where this drive level is insufficient, a separate driver is required. Note also that the output drive level is limited to approximately 12 V if the input voltage exceeds that level. For input voltages below 12 V, the driver drives to slightly below the input voltage. 10 www.ti.com SLUS485A – JULY 2001 – REVISED NOVEMBER 2001 startup sequence 4.0 3.0 MODE 1.0 0.5 0.0 DEVICE ENABLE OUTPUT ENABLE OPEN LAMP DETECT ENABLE LFD ENABLE t0 t1 t2 t3 t4 UDG–01026 Figure 5. Start-Up Sequence Figure 5 describes what happens during a typical startup sequence. At t0, power is applied to the system. A constant current source begins charging the external capacitor connected to the MODE pin. Until the voltage on the MODE pin reaches 0.5 V (t1), the internal circuitry on the device is disabled and nothing happens at the outputs. As the voltage crosses 0.5 V, the internal circuitry is powered up. When the voltage crosses 1 V at t2, the outputs are enabled, allowing the buck stages to begin to charge up and to supply current to the royer stages. During the period from t2 to t3, the open lamp detection circuitry is disabled, preventing a false trip of the open lamp detector circuit when the lamp is trying to ignite for the first time. As a precaution against severe overvoltage on the high-voltage secondary of the transformer, a clamp circuit is included in the UCC3974. The function of the clamp circuit is to monitor the voltage on the BUCK pins and prevent that voltage to drop more than 8.7-V below the input rail. This is accomplished by sourcing a current from the FB pin when the BUCK voltage drops more than 8.7 V. The magnitude of the current sourced from this pin is proportional to the excess drop of the BUCK voltage beyond 8.7 V. The maximum current sourced from this pin is approximately 200 µA. Consequently, the impedance at the FB pin affects the speed at which this clamp becomes effective. A small capacitor and large resistors in the feedback network increases the effectiveness of this feature. From t3 onward, the open lamp detector circuit is enabled. Each time the BUCK pin drops more than 7.8-V below VIN, a 4-bit counter is clocked. If the counter reaches a count of 16 (4 bits) it declares an open lamp fault and shuts down the device. Resetting the device requires a power cycle. The counter in the open lamp detector is an up/down counter. If the BUCK pin only occasionally dips below the 7.8-V threshold, an open lamp condition is not declared since the counter is clocked down on each cycle in which BUCK does not cross the 7.8-V threshold. At time t4, LFD is enabled. Depending on the state of LFDSYNC when this threshold is crossed, DIM is either an analog input or a digital one. www.ti.com 11 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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