LM3075 High Efficiency, Synchronous Current Mode Buck Controller General Description Features The LM3075 is a current mode control, synchronous buck controller IC. Use of synchronous rectification and pulseskipping operation at light load achieves high efficiency over a wide load range. Fixed frequency operation can be obtained by disabling the pulse-skipping mode. Current mode control assures excellent line and load regulation and a wide loop bandwidth for fast response to load transients. n n n n n Current mode control can be achieved by either sensing across the high side NFET or a sense resistor. The switching frequency can be selected as either 200 kHz or 300 kHz from an internal clock. The LM3075 is available with an adjustable output in a TSSOP-20 package. Input voltage range of 4.5V-36V Current Mode Control Skip mode operation available Cycle by cycle current limit 1.24V ± 2% Reference Applications n Automotive Power Supplies n Distributed Power Systems Typical Application Circuit 20162301 © 2005 National Semiconductor Corporation DS201623 www.national.com LM3075 High Efficiency, Synchronous Current Mode Buck Controller September 2005 LM3075 Connection Diagram TOP VIEW 20162302 20-Lead TSSOP (MTC) Ordering Information Order Number Package Type NSC Package Drawing Supplied As LM3075MTC TSSOP-20 MTC-20 73 Units per Anti-Static Tube LM3075MTCX TSSOP-20 MTC-20 2500 Units on Tape and Reel Pin Descriptions LM3075 Pin # Name Function 1 VLIN5 5V linear regulator output 2 VIN Input voltage supply 3 EXT External power connection for VLIN5 4 FS Frequency select 5 EN Enable pin 6 FB Feedback pin 7 FPWM Forced PWM selection 8 COMP Compensation pin 9 SS Output enable / soft-start pin 10 AGND Analog ground 11 PGND Power ground 12 LDRV Low side gate drive www.national.com 13 VDD Low side gate drive supply 14 CBOOT Bootstrap capacitor connection 15 HDRV High side gate drive 16 SW Switch node 17 CSL Current sense low 18 CSH Current sense high 19 ILIM Current limit threshold adjustment 20 PGOOD Power good flag 2 HDRV to SW If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. HDRV to CBOOT Junction Temperature 150˚C Voltages from the indicated pins to GND: Lead Temperature (Soldering, 10 sec) 260˚C ESD Rating (Note 2) 1.5kV VIN, ILIM, CSH −0.3V to 38V PGOOD, FB, VDD, EXT, EN −65˚C to +150˚C −0.3V to +7V COMP, SS, FPWM, FS −0.3V to (VLIN5 +0.3)V CBOOT Operating Ratings(Note 1) Junction Temperature -0.3V to +43V CBOOT to SW −40˚C to +125˚C VIN to GND −0.3V to 7V LDRV +0.3V Storage Temperature Range −0.3 to (VIN + 0.3V) SW, CSL −0.3V 4.5V to 36V EXT −0.3V to (VDD+0.3V) 6V Max Electrical Characteristics Limits in standard type are for TJ = 25˚C only, and limits in boldface type apply over the junction temperature TJ range of -40˚C to +125˚C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25˚C, and are provided for reference purposes only. Unless otherwise specified VIN = 12V. Symbol VFB Parameter Conditions Min Typ Max 1.213 1.238 1.259 Unit Feedback pin voltage VIN = 4.5V to 36V Load Regulation VCOMP = 0.5V to 1.5V 0.04 % Line Regulation VIN = 4.5V to 36V 0.04 % IQ Operating Quiescent current VIN = 4.5V to 36V 1.0 2 mA ISD Shutdown Quiescent current VEN = 0V 60 100 µA VLIN5 VLIN5 Output Voltage VUVLO VLIN5 Under Voltage Lockout VUVLO_HYS VLIN5 Under Voltage Lockout Hysteresis IVLIN5 = 0 to 25mA VIN = 5.5V to 36V VCL_OS IILIM V 4.7 5 5.3 3.7 3.9 4.1 Current Limit Comparator Offset (VILIM – VCSL) ILIM sink current ISS_SRC Soft-Start Pin Source Current VSS = 1.2V ISS_SNK Soft-Start Pin Sink Current VSS = 2V VSS_TO Soft-Start Timeout Threshold VOVP Over Voltage Protection Rising Threshold With respect to VFB VOVP_HYS Over Voltage Protection Hysteresis With respect to VFB V V 0.2 V ± 0.2 mV 8.3 10 11.3 µA 1 2 3 µA 105 4 µA 2 V 111 117 2.8 % % POWERGOOD VPWR_GOOD PGOOD Rising Threshold 92.5 95.5 98.5 VPWR_BAD PGOOD Falling Threshold 87 90.5 95 TPGOOD PGOOD delay PGOOD pin de-asserting IOL PGOOD Low Sink Current VPGOOD = 0.4V IOH PGOOD High Leakage Current VPGOOD = 5V % 10 0.6 µs 1 5 % mA 200 nA GATE DRIVE 3 www.national.com LM3075 Absolute Maximum Ratings (Note 1) LM3075 Electrical Characteristics Limits in standard type are for TJ = 25˚C only, and limits in boldface type apply over the junction temperature TJ range of -40˚C to +125˚C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25˚C, and are provided for reference purposes only. Unless otherwise specified VIN = 12V. (Continued) Symbol Parameter ICBOOT CBOOT Leakage Current Rds_on 1 Conditions Min VCBOOT = 7V Typ Max Unit 10 nA HDRV FET driver pull-up On resistance 2.9 Ω Rds_on 2 HDRV FET driver pull-down On resistance 1.7 Ω Rds_on 3 LDRV FET driver pull-up On resistance 2.4 Ω Rds_on 4 LDRV FET driver pull-down On resistance 0.8 Ω OSCILLATOR fOSC DMAX TON_MIN Oscillator Frequency Maximum Dutycycle VFS = 5V 255 300 330 VFS = 0V 165 200 215 VFB = 1V 95.5 Minimum On Time 98 180 kHz % 260 ns ERROR AMPLIFIER IFB Feedback pin bias current VFB = 1.5V 50 nA ICOMP_SRC COMP Output Source Current VFB = 1V VCOMP = 1V 120 µA ICOMP_SNK COMP Output Sink Current VFB = 1.5V VCOMP = 0.5V 110 µA 620 µmho Gm AVOL Error Amplifier Transconductance 1250 V/V Slope Compensation (referred to the internal summing node) VFS = 0V 0.051 V/µs VFS = 5V 0.076 ACS Current Sense Amplifier Gain VCOMP = 1.25V VIL FS, /FPWM Pin Maximum Low Level Input Level VIH FS, /FPWM Pin Minimum High Level Input Level VSL Error Amplifier Voltage Gain 4 5 6 V/V 0.8 V LOGIC 2 V THERMAL SHUTDOWN TSD Thermal Shutdown 160 ˚C TSD_HYS Thermal Shutdown Hysteresis 10 ˚C 4 Ω 4.6 V EXT REXT THEXT www.national.com EXT pin on resistance VEXT = 5V IVLIN5 = 50 mA VLIN5 to EXT Switch Over Rising Threshold 4 Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Range indicates conditions for which the device is intended to be functional, but does not guarantee specfic performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: For testing purposes, ESD was applied using the human-body model, a 100pF capacitor discharged through a 1.5kΩ resistor. 5 www.national.com LM3075 Electrical Characteristics Limits in standard type are for TJ = 25˚C only, and limits in boldface type apply over the junction temperature TJ range of -40˚C to +125˚C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25˚C, and are provided for reference purposes only. Unless otherwise specified VIN = 12V. (Continued) LM3075 Typical Performance Characteristics Efficiency (VIN = 12V to VOUT = 1.8V) Efficiency (VIN = 12V to VOUT = 3.3V) 20162361 20162351 Efficiency (VIN = 12V to VOUT = 5V) Switching Frequency vs Temperature 20162363 20162362 Error Amplifier Gm vs Temperature ILIM vs Temperature 20162364 www.national.com 20162352 6 (Continued) ILIM vs VIN IQ vs Temperature (Normal Operation) 20162354 20162353 IQ vs Temperature (Shutdown) IQ vs VIN (Shutdown) 20162355 20162356 VFB vs Temperature VLIN5 vs VIN 20162357 20162358 7 www.national.com LM3075 Typical Performance Characteristics LM3075 Typical Performance Characteristics (Continued) Line Regulation Load Regulation 20162359 www.national.com 20162360 8 Block Diagram 20162304 LM3075 9 www.national.com LM3075 Operating Descriptions GENERAL The LM3075 solves the need within many portable systems for 5V, 3.3V, 3.3V stand-by and 12V legacy power supplies. The controller (IC) uses synchronous rectification and employs a peak current mode control scheme. Protection Features include over-voltage protection (OVP), under-voltage protection (UVP), thermal protection, and positive and negative peak current limiting. UVP functionality is automatically disabled during soft-start and then enabled once the IC has correctly started. The device operates with a wide input voltage range from 4.5V to 36V. tive Current Limit section). In force PWM mode, the regulator always operates in Continuous Conduction Mode (CCM) and the duty cycle, which is approximately VOUT/VIN in this mode, is almost independent of load. The force PWM mode is good for applications where fixed switching frequency is required. In forced PWM mode, the top FET has to be turned on for a minimum of typically 180 ns each cycle. However, if the required duty cycle is less than the minimum value, the IC is unable to reach the desired voltage output in FPWM mode. This causes the chip to enter a fault state and the IC attempts to restart until the cause of the fault has been removed (see the Fault State section). SOFT START In normal operation the soft-start functions as follows: SKIP COMPARATOR Whenever the output voltage of the error amplifier (COMP pin) goes below a 0.5V threshold, the PWM cycles are "skipped" until that voltage exceeds the threshold again. Due to the time required for the system loop to respond to changes, it is unlikely that the system will oscillate around the threshold and thus the system remains stable. As the input voltage rises above the 4.2V UVLO threshold, where the internal circuitry is powered on, an internal 2 µA current starts to charge the capacitor connected between the SS pin and ground. A minimum on-time comparator generates the soft-start PWM pulses. As the SS pin voltage ramps up, the duty cycle increases, causing the output voltage to ramp up. During this time, the error amplifier output voltage is clamped at 2V, and the duty cycle generated by the PWM comparator is ignored. When the output voltage exceeds 98.5% (typical) of the set target voltage, the regulator transitions from soft-start to operating mode. Beyond this point, once the PWM pulses generated by the PWM comparator are narrower than those generated by the minimum on-time comparator, the PWM comparator takes over and starts to regulate the output voltage. Peak current mode control now takes place. The rate at which the duty cycle increases depends on the capacitance of the soft-start capacitor. The higher the capacitance, the slower the output voltage ramps up. A unique feature of the LM3075 is that the rate at which the duty cycle grows is independent of the input voltage. This is because the ramp signal used to generate the soft-start duty cycle has a peak value proportional to the input voltage, making the product of duty cycle and input voltage a constant. This makes the soft-start process more predictable and reliable. During soft-start, under-voltage protection is temporarily suspended but over-voltage protection and current limit remain in effect. When the SS pin voltage exceeds 2V, a soft-start time out signal is issued. This signal sets the under-voltage protection into ready mode. This is discussed more in the Under-Voltage Protection section. If the SS pin is short-circuited to ground before startup, the LM3075 operates at minimum duty cycle when it is enabled, and the under-voltage protection is disabled. PULSE-SKIP MODE Pulse-skip mode is activated by pulling the FPWM pin to a TTL-compatible logic high. In this mode, the Zero-Crossing / Negative Current Limit comparator detects the bottom FET current. Once the bottom FET current flows from drain to source, the bottom FET is turned off. This prevents negative inductor current. In force PWM operation, the inductor current is allowed to go negative, so the regulator is always in Continuous Conduction Mode (CCM), no matter what the load is. In pulse-skip mode, the regulator enters Discontinuous Conduction Mode (DCM) under light loads. Once the regulator enters DCM, its switching frequency drops as the load current decreases. The minimum on-time comparator takes over causing the output voltage to continuously rise and COMP pin voltage (the error amplifier output voltage) to continuously drop. When the COMP pin voltage hits the 0.5V level, the Cycle Skip comparator toggles, causing the present switching cycle to be "skipped", i.e., both FETs remain off during the whole cycle. As long as the COMP pin voltage is below 0.5V, no switching of the FETs happens. As a result, the output voltage drops, and the COMP pin voltage rises. When the COMP pin goes above the 0.5V level, the Cycle Skip comparator flips and allows a series of on-time pulses to happen. If the load current is so small that this series of pulses is enough to bring the output voltage up to such a level that the COMP pin drops below 0.5V again, the pulse skipping happens again. Otherwise it may take a number of consecutive pulses to bring the COMP pin voltage down to 0.5V again. As the load current increases, it takes more and more consecutive pulses to drive the COMP voltage to 0.5V. The pulseskipping stops when the load current is sufficiently high. In pulse-skip mode, the frequency of the burst of switching pulses varies directly with the load current. Since the load is usually very light in pulse-skip mode, conducted noise is very low and the variable operating frequency should cause no EMI problems in the system. The LM3075 pulse-skip mode helps the light load efficiency for two reasons. First, the bottom FET is turned on only when inductor current is in the positive conduction region, this eliminates circulating energy loss. Second, the FETs switch only when necessary, rather than every cycle, thus reducing the FETs switching losses and gate drive power losses. FAULT STATE When a fault condition is detected, a "fault" signal is generated internally. This signal discharges the capacitor connected between the SS pin and ground with 4 µA of current until the SS pin reaches 60mV. Once a level of 60mV is reached at the SS pin, the IC restarts normally and resumes operation assuming the cause of the fault condition has been removed. FORCE PWM MODE Pulling the FPWM pin to logic low activates the force PWM mode. In this mode, the top FET and the bottom FET gate signals are always complementary to each other and the Negative Current Limit comparator is activated (see Negawww.national.com 10 LM3075 Operating Descriptions (Continued) CURRENT SENSING The inductor current information is extracted by the current sense pins CSH and CSL. As shown in Figure 1 and Figure 2, current sensing is accomplished by either sensing the Vds of the top FET, or sensing the voltage across a current sense resistor connected from VIN to the drain of the top FET. Both approaches have advantages and disadvantages that need to be weighed for each specific application. The advantage of sensing current through the top FET is reduced parts count, board space, and cost but it also has the disadvantage of accuracy. Using a current sense resistor is the opposite, improving current sense accuracy but requiring additional parts, cost, and board space. The use of a current sense resistor has the additional disadvantage of increasing power loss and thus decreasing efficiency. To ensure linear operation of the current amplifier, the current sense voltage input should not exceed 200 mV. Therefore, the Rdson of the top FET or the current sense resistor must be calculated carefully to ensure that, when the top FET is conducting the maximum current for that application, the current sense voltage does not exceed 200 mV. Assuming a maximum of 200 mV across the CSL/Rdson resistor, the maximum allowable resistance can be calculated as follows: 20162308 FIGURE 1. Current Sensing by Vds of the Top FET 20162309 FIGURE 2. Current Sensing by External Sense Resistor Where IMAX is the maximum expected load current, including an overload multiplier (typically 120%), and ∆IL is the inductor ripple current. Note that the above equation defines only the maximum allowable value and not necessarily the recommended value. As the resistance increases, so do the switching losses. NEGATIVE CURRENT LIMIT The purpose of negative current limit is to ensure that the inductor does not saturate during negative current flow causing excessive current to flow through the bottom FET. The negative current limit is realized through sensing the bottom FET Vds. An internally generated 100mV (typical) reference is used to compare with the bottom FET Vds when it is on. Upon sensing too high a Vds, the bottom FET is turned off. The negative current limit is only activated in force PWM mode. CURRENT LIMITING There is a leading edge blanking circuit that forces the top FET to be on for at least 180 ns. Beyond this minimum on time, the output of the PWM comparator is used to turn off the top FET. With an external resistor connected between the ILIM pin and the CSH pin the 10 µA current sink on the ILIM pin produces a voltage across the resistor to serve as the reference voltage for current limit. Adding a 10 nF capacitor across this resistor filters unwanted noise that could improperly trip the current limit comparator. Current limit is activated if the inductor current is too high causing the voltage at the CSL pin to be lower than that of the ILIM pin, toggling the comparator thus turning off the top FET immediately. The comparator is disabled either when the top FET is turned off or during the leading edge blanking time. The equation for the current limit resistor, RLIM, is as follows: OVER VOLTAGE PROTECTION (OVP) The LM3075 responds to over-voltage events by attempting to recover without the need to restart the IC. There is a trip point at approximately 111% (typical) of VOUT that, once reached, causes the circuit to shut off the HDRV FET and turn on the LDRV FET immediately to drive the bottom FET to discharge the output capacitor through the filter inductor. The system stays in this configuration until the output falls below approximately 108% (typical) of VOUT. Once this lower level has been reached, the system resumes operation in either DCM or CCM. This scenario repeats until the cause of the over-voltage condition is removed. UNDER VOLTAGE PROTECTION When an under-voltage event is detected by the LM3075 and the under-voltage protection (UVP) is in ready mode, the IC attempts to restart the entire system. It does so by shutting off both the LDRV and HDRV FETs until the soft-start capacitor has discharged below a level of 60mV (typical). At this point, the IC shuts off the UVP and restarts the system as though it had just been powered up. The UVP is reengaged once the soft-start capacitor voltage reaches a 11 www.national.com LM3075 Operating Descriptions OUTPUT CAPACITORS FOR LINEAR REGULATORS Like any linear regulator, the linear output that is either generated or controlled by the LM3075 requires an output capacitor to ensure stability. The output of VLIN5 needs a minimum of 4.7 µF. (Continued) level of 2V (typical) and it enters ready mode as it does when the IC first was powered up. The UVP stays in ready mode until a new under-voltage event is detected. POWER GOOD FUNCTION SWITCHING NOISE REDUCTION Power MOSFETs are very fast switching devices. In a synchronous rectifier converter, the rapid drain current rise rate of the top FET coupled with parasitic inductance generates unwanted Ldi/dt spike noise at the source node of the FET (SW pin). The magnitude of the spike noise increases as the output current increases. This parasitic spike noise may turn into electromagnetic interference (EMI) that may cause trouble to the system performance. Therefore, it is vital to correct system performance to suppress this kind of noise. As shown in Figure 3, adding a resistor in series with the CBOOT pin scales the spikes and slow down the gate drive (HDRV) rise time of the top FET to yield a desired drain current transition time. Usually a 3.3Ω to 5.1Ω resistor is sufficient to suppress the noise. It is important to note that the addition of these resistors does increase the power loss in the system and thus decreases the efficiency. It is therefore important to choose the size of the resistor carefully; the top FET switching losses increases with higher resistance values. A power good signal is available for indicating the general state of the IC. The function is realized through the internal MOSFET tied from the PGOOD pin to ground. The power good signal is asserted by turning off the MOSFET. The on resistance of the power good MOSFET is about 300Ω. The internal power good MOSFET is not turned on unless at least one of the following occurs: 1. There is an output over-voltage event. 2. The output voltage is below the power good lower limit (UVP event). 3. System is in shutdown mode, i.e. the EN pin voltage is below 0.6V. As with the other protection responses, the power good signal has built-in hysteresis. See VPWR_GOOD in the Electrical Characteristics table. FREQUENCY SELECT The operating frequency may be set at 200 kHz or 300 kHz by the voltage on the frequency select (FS) pin. A voltage of 0V corresponds to a frequency of 200 kHz and a voltage of 5V corresponds to a frequency of 300 kHz. See the Electrical Characteristics table for more information. VLIN5, VDD and EXT An internal 5V supply (VLIN5) is generated from the VIN voltage through an internal linear regulator. This 5V supply is mainly for internal circuitry use, but can also be used externally. When used externally, it is recommended that the VLIN5 voltage only be used for powering the gate drivers, i.e. supplying the bias for the top drivers’ bootstrap circuit and the bottom drivers’ VDD pins. When the voltage applied to the EXT pin is below 4.7V, an internal 5V low dropout regulator supplies the power for the VLIN5. If the EXT voltage is taken above 4.7V, the 5V regulator is turned off and an internal switch is turned on to connect the EXT pin to the VLIN5 pin. This allows the VLIN5 power to be derived from a high efficiency source such as the output of the switching channel, when the channel is configured to operate in fixed 5V mode. The VLIN5 voltage output comes from the EXT pin whenever the voltage applied to the EXT pin is higher than 4.7V. The externally applied voltage is required to be less than the voltage applied to the VIN pin at all times. This prevents a voltage feedback situation from the EXT pin to the VIN pin. When the input voltage must be guaranteed to be within 4.5V to 5.5V, tie the VLIN5 pin directly to the VIN pin and tie the EXT pin to ground. In this mode, the VLIN5 current directly comes from power stage input rail and power loss due to the internal linear regulation is no longer an issue. Always connect the VDD pin to the VLIN5 pin through a 4.7Ω resistor and connect a ceramic capacitor of at least 1 µF to bypass the VDD pin to ground. 20162310 FIGURE 3. Adding a resistor in series with the CBOOT pin to suppress the turn-on switching noise Component Selection OUTPUT VOLTAGE SETTING The output voltage for each channel is set by the ratio of a voltage divider as shown in Figure 4. The resistor values can be determined by the following equation: (1) Where VFB is the typical value of feedback pin voltage and VOUT is the nominal output voltage . Although increasing the value of R1 and R2 increases efficiency, this also decreases accuracy. Therefore, a maximum value is recommended for R2 in order to keep the output within 0.3% of VOUT. This maximum R2 value should be calculated first with the following equation: THERMAL PROTECTION The LM3075 IC enters thermal protection mode if the die temperature exceeds 160˚C. In this mode, the top and bottom FETs are turned off immediately. The IC then behaves in a manner as described in the Fault State section. www.national.com 12 Output Capacitor Selection (Continued) In applications that exhibit large and fast load current swings, the slew rate of such a load current transient may be beyond the response speed of the regulator. Therefore, to meet voltage transient requirements during worst-case load transients, special consideration should be given to output capacitor selection. The total combined ESR of the output capacitors must be lower than a certain value, while the total capacitance must be greater than a certain value. Also, in applications where the specification of output voltage regulation is tight and ripple voltage must be low, starting from the required output voltage ripple (∆VOUT) often results in fewer design iterations. (2) Where IFB_MAX is the maximum current drawn by the FB pin. Example: VOUT = 5V, VFB = 1.238V, IFB_MAX = 200 nA. ALLOWED TRANSIENT VOLTAGE EXCURSION The allowed output voltage excursion during a load transient (∆VTRANS) is: 20162312 FIGURE 4. Output Voltage Setting (5) Where δ% is the output voltage regulation window, e% is the output voltage initial accuracy VOUT is the nominal output voltage, and ∆VOUT is the output voltage ripple. Example: VOUT = 5V, δ% = 7%, e% = 3.4%, ∆VOUT = 40 mV peak-to-peak. (3) R2 is chosen to be 60.4 kΩ ± 1%. To calculate R1: (6) Since the ripple voltage is included in the calculation of ∆VTRANS, the inductor ripple current should not be included in the worst-case load current excursion. That is, the worstcase load current excursion should be simply maximum load current change specification, ∆ITRANS. (4) The output voltage is limited by the maximum duty cycle as well as the minimum on time. Figure 5 shows the limits for input and output voltages. The recommended maximum output voltage is approximately 1V less than the nominal input voltage. At 30V input, the minimum output is approximately 2.3V and the maximum is approximately 27V. For input voltages below 5.5V, VLIN5 must be connected to VIN through a small resistor (approximately 4.7Ω). Doing this ensures that VLIN5 does not fall below the UVLO threshold. MAXIMUM ESR CALCULATION Unless the rise and fall times of a load transient are slower than the response speed of the control loop, if the total combined ESR (Resr) is too high, the load transient requirement is not met, no matter how large the capacitance. The maximum allowed total combined ESR is: (7) Example: ∆VTRANS = 160mV, ∆ITRANS = 3A. Then Resr_max = 53.3mΩ. Maximum ESR criterion can be used when the associated capacitance is high enough, otherwise more capacitors than the number determined by this criterion should be used in parallel. MINIMUM CAPACITANCE CALCULATION In a switch mode power supply, the minimum output capacitance is typically dictated by the load transient requirement. If there is not enough capacitance, the output voltage excursion will exceed the maximum allowed value even if the maximum ESR requirement is met. The worst-case load transient is an unloading transient that happens when the 20162314 FIGURE 5. Available Output Voltage Range 13 www.national.com LM3075 Component Selection LM3075 Output Capacitor Selection capacitors to choose from, it may be a good idea to adjust the inductance value so that a requirement of 3.2 capacitors can be reduced to 3 capacitors. Since inductor ripple current is often the criterion for selecting an output inductor, it is a good idea to double-check this value. The equation is: (Continued) input voltage is the highest and when the present switching cycle has just finished. The corresponding minimum capacitance is calculated as follows: (8) Notice it is already assumed the total ESR, Resr, is no greater than Resr_max, otherwise the term under the square root will be a negative value. Also, it is assumed that L has already been selected, therefore the minimum L value should be calculated before CMIN and after Resr (see Inductor Selection below). Example: Resr = 20mΩ, VOUT = 5V, ∆VTRANS = 160mV, ∆ITRANS = 3A, L = 8µH (12) Where D is the duty cycle, defined by VOUT/VIN. Also important is the ripple current, which is defined by ∆IL /INOM., where INOM is the nominal output current. Generally speaking, a ripple content of less than 50% is ok. Larger ripple content causes excessive losses in the inductor. Example: VIN = 12V, VOUT = 5.0V, fSW = 300 kHz, L = 8 µH (13) Given a maximum load current of 5A, the ripple content is 1.2A / 5A = 24%. When choosing an inductor, the saturation current should be higher than the maximum peak inductor current and the RMS current rating should be higher than the maximum load current. (9) Generally speaking, CMIN decreases with decreasing Resr, ∆ITRANS, and L, but with increasing VOUT and ∆VTRANS. The output capacitance can therefore be chosen to be slightly larger than the calculated value so that it is more easily available. Here we would likely be fine choosing 220 µF. Input Capacitor Selection Inductor Selection The input capacitor must be selected such that it can handle both the maximum ripple RMS current at highest ambient temperature and the maximum input voltage. The equation for the RMS current through the input capacitor is then The size of the output inductor can be determined from the desired output ripple voltage, ∆VOUT, and the impedance of the output capacitors at the switching frequency. The equation to determine the minimum inductance value is as follows: (14) Where IMAX is maximum load current and D is the duty cycle. Example: IMAX = 5A and D = 0.42 (10) In the above equation, Resr is used in place of the impedance of the output capacitors. This is because in most cases, the impedance of the output capacitors at the switching frequency is very close to Resr. In the case of ceramic capacitors, replace Resr with the true impedance. Example: VIN_MAX = 36V, VOUT = 5.0V, ∆VOUT = 40 mV, Resr = 20 mΩ, fSW = 300 kHz, (15) The function D(1-D) has a maxima at D = 0.5. This duty cycle corresponds to the maximum RMS input current that may be used as a worst case in selecting an input capacitor. Input capacitors must meet the minimum requirements of voltage and ripple current capacity. The size of the capacitor should then be selected based on hold up time requirements. Bench testing for individual applications is still the best way to determine a reliable input capacitor value. The input capacitor should always be placed as close as possible to the current sense resistor or the drain of the top FET. (11) The actual selection process usually involves several iterations of all of the above steps, from ripple voltage selection, to capacitor selection, to inductance calculations. Both the highest and the lowest input and output voltages and load transient requirements should be considered. If an inductance value larger than LMIN is selected, make sure that the CMIN requirement is not violated. Priority should be given to parameters that are not flexible or more costly. For example, if there are very few types of www.national.com MOSFET Selection BOTTOM FET SELECTION During normal operation, the bottom FET is switching at almost zero voltage and therefore only conduction losses are present in the bottom FET. This makes the on resistance (Rdson) the most important parameter when selecting the bottom FET; the lower the on resistance, the lower the power loss. The bottom FETs’ power losses peak at the maximum 14 capacity to switching losses. The best way to precisely determine switching losses is through bench testing. The equation for calculating the on resistance of the top FET is thus: (Continued) input voltage and load current. The equation for the maximum allowable on resistance at room temperature for a given FET package, is: (18) Example: TJ_MAX = 100˚C, TA_MAX = 60˚C, RθJA = 60˚C/W, VIN_MIN = 5.5V, VNOM = 5V, and IMAX = 5A. (16) where TJ_MAX is the maximum allowed junction temperature in the FET, TA_MAX is the maximum ambient temperature, RθJA is the junction-to-ambient thermal resistance of the FET, and TC is the temperature coefficient of the on resistance which is typically in the range of 10,000ppm/˚C. If the calculated Rdson_max is smaller than the lowest value available, multiple FETs can be used in parallel. This effectively reduces the IMAX term in the above equation, thus reducing Rdson. When using two FETs in parallel, multiply the calculated Rdson_max by 4 to obtain the Rdson_max for each FET. In the case of three FETs, multiply by 9. Example: TJ_MAX = 100˚C, TA_MAX = 60˚C, RθJA = 60˚C/W, VIN_MAX = 36V, VOUT = 5V, and IMAX = 5A (19) When using FETs in parallel, the same guidelines apply to the top FET as apply to the bottom FET. BOOTSTRAP COMPONENT SELECTION Selection of the bootstrap components can be done after top FET and driving voltage are chosen. VLIN5 or another supply such as input may be used as the driving voltage. Once chosen, the bootstrap components can be selected . Typically a 0.1µF ceramic (X5R, X7R) works well. Any suitably sized Schottky diode works well for the bootstrap Diode. If excessive leakage current is seen, the a larger bootstrap capacitance may be needed . Loop Compensation (17) If the selected FET has an Rdson value higher than 17.7Ω, then two FETs with an Rdson less than 30mΩ can be used in parallel. In this case, the temperature rise on each FET will not go to TJ_MAX because each FET is now dissipating only half of the total power. The purpose of loop compensation is to meet static and dynamic performance requirements while maintaining stability. Loop gain is usually checked to determine small-signal performance. Loop gain is equal to the product of the control-output transfer function and the output-control transfer function (the compensation network transfer function). Generally speaking, it is a good idea to have a loop gain slope that is -20dB/decade from a very low frequency to well beyond the crossover frequency. The crossover frequency should not exceed one-fifth of the switching frequency. The higher the bandwidth, the faster the load transient response speed unless duty cycle saturates during a load transient. Since the control-output transfer function usually has very limited low frequency gain, it is a good idea to place a pole in the compensation at zero frequency, so that the low frequency gain is relatively large. A large DC gain means high DC regulation accuracy (i.e. DC voltage changes little with load or line variations). The rest of the compensation scheme depends highly on the shape of the control-output plot. As shown in Figure 6, the control-output transfer function consists of one pole (fp), one zero (fz), and a double pole at fn (half the switching frequency). The following can be done to create a -20dB/decade roll-off of the loop gain: Place the first pole at 0Hz, the first zero at fp, the second pole at fz, and the second zero at fn. The resulting output-control transfer function is shown in Figure 7. TOP FET SELECTION The output resistance for the top FET driver is 3.1Ω (maximum). The bias voltage is developed by an external bootstrap supply circuit, which is comprised of a diode and a capacitor. Before selecting the top FET, it is recommended to select the driving voltage for the bootstrap circuit first (see more in the Bootstrap Component Selection section). If VLIN5 is chosen to drive the bootstrap circuit, care must be taken to ensure that the gate threshold voltage of the top FET is less than 3V (maximum). The top FET starts to turn on when the input voltage exceeds the threshold voltage of the UVLO, which has a minimum threshold of 3.8V. In this case, VLIN5 follows at approximately 3.8V also and thus the bias voltage to the top FET driver is about 3V after the bootstrap diode. The top FET has two types of losses: switching loss and conduction loss. The switching losses mainly consist of crossover loss and bottom diode reverse recovery loss. Since it is rather difficult to estimate the switching loss, a general starting point is to allot 60% of the top FET thermal 15 www.national.com LM3075 MOSFET Selection LM3075 Loop Compensation (Continued) (23) (24) Once the fp range is determined, Rc1 should be calculated using: 20162331 FIGURE 6. Control-Output Transfer Function (25) Where B is the desired gain in V/V at fp (fz1), gm is the transconductance of the error amplifier, and R1 and R2 are the feedback resistors. A gain value around 10dB (3.3V/V) is generally a good starting point. Example: B = 3.3 V/V, gm = 0.650 µmho, R1 = 20 kΩ, R2 = 60.4 kΩ: (26) Bandwidth varies proportionally to the value of Rc1. Next, Cc1 can be determined with the following equation : 20162332 FIGURE 7. Output-Control Transfer Function The control-output corner frequencies, and thus the desired compensation corner frequencies, can be determined approximately by the following equations: (27) Example: fpmin = 313Hz, Rc1 = 20kΩ: (20) (28) The value of Cc1 should be within the range determined by fpmin/max. A higher value generally provides a more stable loop, but too high a value slows the transient response time. The compensation network also introduces a low frequency pole that is close to 0Hz. A second pole should also be placed at fz. This pole can be created with a single capacitor Cc2 and a shorted Rc2 (see Figure 9). The minimum value for this capacitor can be calculated by: (21) Since fp is determined by the output network, it shifts with loading (Ro) and duty cycle. First determine the range of frequencies (fpmin/max) of the pole across the expected load range and then place the first compensation zero within that range. Example: Resr = 20mΩ, Co = 100uF, Romax = 5V/ 100mA=50Ω, Romin = 5V/5A = 1Ω, L = 8 µH. (29) Cc2 may not be necessary, however it does create a more stable control loop. This is especially important with high load currents and in current sharing mode. Example: fz = 36kHz, Rc1 = 20kΩ: (22) www.national.com 16 LM3075 Loop Compensation (Continued) (30) 20162345 FIGURE 8. Compensation Network 20162365 Typical Application Circuit 17 www.national.com LM3075 High Efficiency, Synchronous Current Mode Buck Controller Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead TSSOP Package Order Number LM3075MTC NS Package Number MTC20 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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