198-2710; Rev 0; 2/03 KIT ATION EVALU LE B A IL A AV 2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier Features ♦ 2.488Gbps and 2.667Gbps Input Data Rates ♦ Reference Clock Not Required for Data Acquisition ♦ Exceeds ANSI, ITU, and Bellcore SONET/SDH Jitter Specifications ♦ 2.7mUIRMS Clock Jitter Generation ♦ 10mVP-P Input Sensitivity Without Threshold Adjust ♦ 0.65UIP-P High-Frequency Jitter Tolerance ♦ ±170mV Wide Input Threshold Adjust Range ♦ Clock Holdover Capability Using FrequencySelectable Reference Clock The MAX3874 contains a vertical threshold control to compensate for optical noise due to EDFAs in DWDM transmission systems. The recovered data and clock outputs are CML with on-chip 50Ω back termination on each line. Its jitter performance exceeds all SONET/ SDH specifications. The MAX3874A is the MAX3874 with a voltage-controlled oscillator (VCO) centered at 2.0212GHz. ♦ Serial Loopback Input Available for System Diagnostic Testing ♦ Loss-of-Lock (LOL) Indicator ♦ Small 5mm ✕ 5mm 32-Pin QFN Package The MAX3874 operates from a single +3.3V supply and typically consumes 580mW. It is available in a 5mm ✕ 5mm 32-pin QFN with exposed pad package and operates over the -40°C to +85°C temperature range. Ordering Information TEMP RANGE PINPACKAGE PKG CODE MAX3874EGJ -40°C to +85°C 32 QFN-EP* G3255-1 MAX3874AEGJ** -40°C to +85°C 32 QFN-EP* G3255-1 PART Applications SONET/SDH Receivers and Regenerators Add/Drop Multiplexers Digital Cross-Connects SONET/SDH Test Equipment DWDM Transmission Systems Access Networks *EP = Exposed pad. **Contains a VCO centered at 2.0212GHz. Pin Configuration appears at end of data sheet. Typical Application Circuit +3.3V +3.3V CAZ 0.1µF CFIL 0.068µF VCC FILTER +3.3V FIL VCC_VCO CAZ- OUT+ MAX3745* OUT- +3.3V CAZ+ FREFSET VCC SDI+ 2.488Gbps DATA SDO+ SDI- IN SDO- SLBI+ GND MAX3874 SLBI- SCLKO+ SCLKO- +3.3V CML CML VCTRL VREF *FUTURE PRODUCT 2.488Gbps SYSTEM LOOPBACK DATA SIS LREF LOL RATESET GND +3.3V ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3874 General Description The MAX3874 is a compact, dual-rate clock and data recovery with limiting amplifier for OC-48 and OC-48 with FEC SONET/SDH applications. Without using an external reference clock, the fully integrated phaselocked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input. The input data is then retimed by this recovered clock, providing a clean data output. An additional serial input (SLBI±) is available for system-loopback diagnostic testing. Alternatively, this input can be connected to a reference clock to maintain a valid clock output in the absence of data transitions. The device also includes a loss-of-lock (LOL) output. MAX3874 2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC..............................................-0.5V to +5.0V Input Voltage Levels (SDI+, SDI-, SLBI+, SLBI-) ..............................(VCC - 1.0V) to (VCC + 0.5V) Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)..............±20mA CML Output Current (SDO+, SDO-, SCLKO+, SCLKO-) ...±22mA Voltage at LOL, LREF, SIS, FIL, RATESET, FREFSET, VCTRL,VREF, CAZ+, CAZ-.......................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85°C) 32-Pin QFN (derate 21.3mW/°C above +85°C) .........1384mW Operating Junction Temperature ......................-55°C to +150°C Storage Temperature Range .............................-55°C to +150°C Processing Temperature (die) .........................................+400°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL Supply Current CONDITIONS ICC (Note 2) VIS Figure 1 Figure 1 MIN TYP MAX UNITS 175 215 mA VCC 0.8 VCC + 0.4 V VCC 0.4 VCC V 57.5 Ω 50 600 mVP-P INPUT SPECIFICATION (SDI±, SLBI±) Single-Ended Input Voltage Range Input Common-Mode Voltage Input Termination to VCC RIN 42.5 50 THRESHOLD-SETTING SPECIFICATION (SDI±) Differential Input Voltage Range (SDI±) Threshold Adjustment Range Threshold Control Voltage Threshold adjust enabled VTH VCTRL Figure 2 -170 +170 Figure 2 (Note 3) 0.3 2.1 mV V Figure 2 -18 +18 mV ±5 Threshold Control Linearity Threshold Setting Accuracy Threshold Setting Stabiliity % 15mV ≤ |VTH| ≤ 80mV -6 +6 80mV < |VTH| ≤ 170mV -12 +12 +10 µA mV Maximum Input Current ICTRL -10 Reference Voltage Output VREF 2.14 2.2 2.24 V 85 100 115 Ω CML OUTPUT SPECIFICATION (SDO±, SCLKO±) CML Differential Output Impedance CML Output Common-Mode Voltage 2 RO (Note 4) VCC 0.2 _______________________________________________________________________________________ V 2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier MAX3874 DC ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.8 V +10 µA 0.4 V LVTTL INPUT/OUTPUT SPECIFICATION (LOL, LREF, RATESET, FREFSET) LVTTL Input High Voltage VIH LVTTL Input Low Voltage VIL 2.0 LVTTL Input Current -10 LVTTL Output High Voltage VOH IOH = +20µA LVTTL Output Low Voltage VOL IOL = -1mA Note 1: Note 2: Note 3: Note 4: V 2.4 V At -40°C, DC characteristics are guaranteed by design and characterization. CML outputs open. Voltage applied to VCTRL pin is from 0.3V to 2.1V when input threshold is adjusted from +170mV to -170mV. RL = 50Ω to VCC. AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 5) PARAMETER SYMBOL Serial Input Data Rate CONDITIONS MIN 2.488 MAX3874 (RATESET = VCC) 2.667 MAX3874A Differential Input Voltage (SDI±) VID Jitter Transfer Bandwidth Jitter Peaking Threshold adjust disabled, Figure 1 (Note 6) BER ≤ 10 Differential Input Voltage (SLBI±) JBW JP Sinusoidal Jitter Tolerance MAX3874 Sinusoidal Jitter Tolerance (MAX3874A) Sinusoidal Jitter Tolerance with Threshold Adjust Enabled (Note 8) TYP MAX3874 (RATESET = GND) -10 MAX UNITS Gbps 2.0212 10 1600 mVP-P 50 800 mVP-P MAX3874 1.5 MAX3874A 0.75 f ≤ JBW 2.0 0.1 f = 100kHz 3.1 8.0 f = 1MHz 0.62 0.93 f = 10MHz 0.44 0.65 f = 1MHz (Note 7) >0.5 f = 10MHz (Note 7) f = 100kHz >0.3 f = 1MHz 0.82 f = 10MHz 0.54 MHz dB UIP-P UIP-P 7.1 Jitter Generation JGEN (Note 9) 2.7 Differential Input Return Loss (SDI±, SLBI±) -20log | S11 | 100kHz to 2.5GHz 16 2.5GHz to 4GHz 15 UIP-P 4.0 mUIRMS dB CML OUTPUT SPECIFICATION (SDO ±, SCLKO±) Output Edge Speed tr, tf CML Output Differential Swing Clock-to-Q Delay tCLK-Q 20% to 80% RL = 100Ω differential 600 (Note 10) -40 800 110 ps 1000 mVP-P +40 ps _______________________________________________________________________________________ 3 MAX3874 2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier AC ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PLL ACQUISITION/LOCK SPECIFICATION Tolerated Consecutive Identical Digits -10 BER ≤ 10 Acquisition Time Figure 4 (Note 11) LOL Assert Time Figure 4 Low-Frequency Cutoff for DCOffset Cancellation Loop CAZ = 0.1µF 2000 2.3 Bits 1.0 ms 10.0 µs 4 kHz CLOCK HOLDOVER SPECIFICATION Reference Clock Frequency Table 4 Maximum VCO Frequency Drift (Note 12) 400 ppm Note 5: Minimum and maximum AC characteristics are guaranteed by design and characterization using the MAX3874. Specifications apply to the MAX3874A only when noted. Note 6: Jitter tolerance is guaranteed (BER ≤ 10-10) within this input voltage range. Input threshold adjust is disabled with VCTRL connected to VCC. Note 7: Measurements limited by equipment capability. Note 8: Measured using a 100mVP-P differential swing with a 20mVDC offset and an edge speed of 145ps (4th-order Bessel filter with f3dB = 1.8GHz). Note 9: Measured with 10mVP-P differential input, 223 - 1 PRBS pattern at OC-48 with bandwidth from 12kHz to 20MHz. Note 10: Relative to the falling edge of the SCLKO+ (Figure 3). Note 11: Measured at OC-48 data rate using a 0.068µF loop filter capacitor initialized to +3.6V. Note 12: Measured at OC-48 data rate under LOL condition with the CDR clock output set by the external reference clock. Timing Diagrams VCC + 0.4V VTH (mV) 800mV 5mV VCC - 0.4V +188 THRESHOLD-SETTING STABILITY (OVERTEMPERATURE AND POWER SUPPLY) +170 +152 VCC (a) AC-COUPLED SINGLE-ENDED INPUT 1.3 5mV VCTRL (V) VCC 0.3 1.1 800mV VCC - 0.4V VCC - 0.8V -152 -170 -188 (b) DC-COUPLED SINGLE-ENDED INPUT Figure 1. Definition of Input Voltage Swing 4 2.1 THRESHOLDSETTING ACCURACY (PART-TO-PART VARIATION OVER PROCESS) Figure 2. Relationship Between Control Voltage and Threshold Voltage _______________________________________________________________________________________ 2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier DATA tCLK DATA INPUT DATA SCLKO+ tCLK-Q LOL ASSERT TIME SDO ACQUISITION TIME LOL OUTPUT Figure 4. LOL Assert Time and PLL Acquisition Time Measurement Figure 3. Definition of Clock-to-Q Delay Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) MAX3874toc02 RECOVERED CLOCK AND DATA (2.67Gbps, 223 - 1 PATTERN, VIN = 10mVP-P) MAX3874toc01 RECOVERED CLOCK AND DATA (2.488Gbps, 223 - 1 PATTERN, VIN = 10mVP-P) 200mV/ div 200mV/ div 100ps/div 100ps/div JITTER GENERATION vs. POWER-SUPPLY WHITE NOISE 3.5 100 INPUT JITTER (UIP-P) 3.0 WITH ADDITIONAL 0.15UI OF DETERMINISTIC JITTER 2.5 2.0 1.5 10 1 1.0 BELLCORE MASK 0.5 0.0 10ps/div TOTAL WIDEBAND RMS JITTER = 1.60ps PEAK-TO-PEAK JITTER = 12.20ps MAX3874 toc05 OC-48 PRBS = 223 - 1 JITTER TOLERANCE (2.488Gbps, 223 - 1 PATTERN, VIN = 10mVP-P) MAX3874toc04 4.0 JITTER GENERATION (psRMS) MAX3874toc03 RECOVERED CLOCK JITTER (2.488Gbps) 0.1 0 5 10 15 20 25 WHITE-NOISE AMPLITUDE (mVRMS) 30 10k 100k 1M 10M JITTER FREQUENCY (Hz) _______________________________________________________________________________________ 5 MAX3874 Timing Diagrams (continued) Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25°C, unless otherwise noted.) JITTER TOLERANCE vs. INPUT DETERMINISTIC JITTER 0.6 0.5 0.4 JITTER FREQUENCY = 10MHz 0.3 0.2 WITH ADDITIONAL 0.15UI DETERMINISTIC JITTER 0.1 0.7 0.6 0.5 fJITTER = 10MHz 0.4 0.3 0.2 0.1 0 0 1 10 100 1000 INPUT AMPLITUDE (mVP-P) 0 10,000 -1.5 -2.0 CFIL = 0.068µF PRBS = 223 - 1 2.488Gbps -2.5 0.20 0.25 DETERMINISTIC JITTER (UIP-P) 10-5 -6 10-7 10 -8 10 -9 OC-48 PRBS = 223 - 1 10-11 10k 100k 1M 10M 0 0.3 0.2 1 2 3 INPUT DATA FILTERED BY A 1870MHz 4TH-ORDER BESSEL FILTER 0.1 20 30 40 50 60 70 80 INPUT THRESHOLD (% AMPLITUDE) 4 5 200 195 190 185 180 175 170 165 160 155 150 145 140 -50 -25 INPUT VOLTAGE (mVP-P) FREQUENCY (Hz) DIFFERENTIAL S11 vs. FREQUENCY PULLIN RANGE (RATESET = 0) 2.9 2.8 FREQUENCY (GHz) -10 -15 -20 -25 MAX3874toc13 -5 0 25 50 TEMPERATURE (°C) 3.0 MAX3874 toc12 0 S11 (dB) 0.4 10 MAX3874toc10 10-4 10 VIN = 100mVP-P 2.488Gbps 223 - 1 PATTERN 2.7 2.6 2.5 2.4 2.3 -30 2.2 -35 2.1 -40 2.0 0 6 0.5 1.0 1.5 2.0 2.5 3.0 3.5 FREQUENCY (GHz) 4.0 90 SUPPLY CURRENT vs. TEMPERATURE -3 10-10 -3.0 1k 0.5 0 0.30 SUPPLY CURRENT (mA) BELLCORE MASK -1.0 10 BIT-ERROR RATIO -0.5 0.15 10-2 MAX3874toc09 0 0.10 JITTER FREQUENCY = 10MHz 0.6 BIT-ERROR RATIO vs. INPUT AMPLITUDE JITTER TRANSFER 0.5 0.05 MAX3874toc08 fJITTER = 1MHz 0.8 0.7 MAX3874toc11 JITTER FREQUENCY = 1MHz 223 - 1 PATTERN 2.488Gbps VIN = 10mVP-P 0.9 SINUSOIDAL JITTER TOLERANCE (UIP-P) JITTER TOLERANCE (UIP-P) 0.7 1.0 SINUSOIDAL JITTER TOLERANCE (UIP-P) MAX3874toc06 0.8 JITTER TOLERANCE vs. THRESHOLD ADJUST MAX3874toc07 JITTER TOLERANCE vs. INPUT AMPLITUDE (2.488Gbps, 223 - 1 PATTERN) JITTER TRANSFER (dB) MAX3874 2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier -50 -25 0 25 50 75 AMBIENT TEMPERATURE (°C) _______________________________________________________________________________________ 100 75 100 2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier PIN NAME 1, 4, 27 VCC 2 SDI+ Positive Serial Data Input, CML 3 SDI- Negative Serial Data Input, CML 5 SLBI+ 6 SLBI- 7 SIS 8 LREF Lock-to-Reference Clock Input, LVTTL. Set high for PLL lock to serial data, set low for PLL lock to reference clock. 9 LOL Loss-of-Lock Output, LVTTL. Active low. 10, 11, 16, 25, 32 GND Supply Ground 12 13, 18 FUNCTION +3.3V Supply Voltage Positive System Loopback Input or Reference Clock Input, CML Negative System Loopback Input or Reference Clock Input, CML Signal Selection Input, LVTTL. Set low for normal operation, set high for system loopback. FIL PLL Loop-Filter Capacitor Input. Connect a 0.068µF capacitor between FIL and VCC_VCO. VCC_VCO +3.3V Supply Voltage for the VCO 14, 15 N.C. 17 RATESET 19 SCLKO- Negative Serial Clock Output, CML SCLKO+ Positive Serial Clock Output, CML 20 21, 24 22 Not Connected VCO Frequency Select Input, LVTTL (Tables 2, 3, and 4) VCC_OUT Supply Voltage for the CML Outputs SDO- Negative Serial Data Output, CML 23 SDO+ 26 FREFSET Positive Serial Data Output, CML 28 CAZ+ Positive Capacitor Input for DC-Offset Cancellation Loop. Connect a 0.1µF capacitor between CAZ+ and CAZ-. 29 CAZ- Negative Capacitor Input for DC-Offset Cancellation Loop. Connect a 0.1µF capacitor between CAZ+ and CAZ-. 30 VREF +2.2V Bandgap Reference Voltage Output. Optionally used for threshold adjustment. 31 VCTRL Analog Control Input for Threshold Adjustment. Connect to VCC to disable threshold adjust. EP Exposed Pad Reference Clock Frequency Select Input, LVTTL (Tables 2, 3, and 4) Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and electrical performance. _______________________________________________________________________________________ 7 MAX3874 Pin Description MAX3874 2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier SLBI Input Amplifier Detailed Description The SLBI input amplifier accepts either NRZ loopback data or a reference clock signal. This amplifier can accept a differential input amplitude from 50mVP-P to 800mVP-P. The MAX3874 consists of a fully integrated PLL limiting amplifier with threshold adjust, DC-offset cancellation loop, data retiming block, and CML output buffers (Figure 5). The PLL consists of a phase/frequency detector, a loop filter, and a VCO. This device is designed to deliver the best combination of jitter performance and power dissipation by using a fully differential signal architecture and low-noise design techniques. Phase Detector The phase detector incorporated in the MAX3874 produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. SDI Input Amplifier The SDI inputs of the MAX3874 accept serial NRZ data with a differential input amplitude from 10mV P-P to 1600mVP-P. The input sensitivity is 10mVP-P, at which the jitter tolerance is met for a BER of 10-10 with threshold adjust disabled. The input sensitivity can be as low as 4mV P-P and still maintain a BER of 10 -10 . The MAX3874 inputs are designed to directly interface with a transimpedance amplifier such as the MAX3745. For applications in which vertical threshold adjustment is needed, the MAX3874 can be connected to the output of an AGC amplifier such as the MAX3861. When using the threshold adjust, the input voltage range is 50mVP-P to 600mVP-P (see the Design Procedure section). CAZ+ VCTRL AMP SDI- LOL CAZ- FIL DC-OFFSET CANCELLATION LOOP VREF RATESET MAX3874 THRESHOLD ADJUST SDI+ Frequency Detector The digital frequency detector (FD) acquires frequency lock without the use of an external reference clock. The frequency difference between the received data and the VCO clock is derived by sampling the in-phase and quadrature VCO outputs on both edges of the datainput signal. Depending on the polarity of the frequency difference, the FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the FD returns to a neutral state. False locking is eliminated by this digital frequency detector. BANDGAP REFERENCE SDO+ 0 D Q CML SDO- 1 PHASE/ FREQUENCY DETECTOR SLBI+ AMP SLBI- LOOP FILTER SCLKO+ VCO CML SIS LREF LOGIC FREFSET Figure 5. Functional Diagram 8 _______________________________________________________________________________________ SCLKO- 2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier Modes of Operation The MAX3874 has three operational modes controlled by the LREF and SIS inputs: normal, system loopback, and clock holdover. Normal operation mode requires a serial data stream at the SDI± inputs, system loopback mode requires a serial data stream at the SLBI± inputs, and clock holdover mode requires a reference clock signal at the SLBI± inputs. See Table 1 for the required LREF and SIS settings. Once an operational mode is chosen, the remaining logic inputs (RATESET, FREFSET) program the input data rate or reference clock frequency. Loss-of-Lock Monitor Normal and System Loopback Settings The RATESET pin is available for setting the SDI± and SLBI± inputs to receive the appropriate data rate. The FREFSET pin can be set to a zero or 1 while in normal or system-loopback mode (Tables 2 and 3). The LOL output indicates a PLL lock failure due to excessive jitter present at the data input or due to loss of input data. The LOL output is asserted low when the PLL loses lock. DC-Offset Cancellation Loop A DC-offset cancellation loop is implemented to remove the DC offset of the limiting amplifier. To minimize the lowfrequency pattern-dependent jitter associated with this DC-cancellation loop, the low-frequency cutoff is 10kHz (typ) with CAZ = 0.1µF, connected from CAZ+ to CAZ-. The DC-offset cancellation loop operates only when threshold adjust is disabled. Table 1. Operational Modes MODE LREF SIS Normal 1 0 System loopback 1 1 Clock holdover 0 1 or 0 Design Procedure Decision Threshold Adjust In applications in which the noise density is not balanced between logical zeros and ones (i.e., optical amplification using EDFA amplifiers), lower bit-error ratios (BERs) can be achieved by adjusting the input threshold. Varying the voltage at VCTRL from +0.3V to +2.1V achieves a vertical decision threshold adjustment of +170mV to -170mV, respectively (Figure 2). Use the provided bandgap reference voltage output (VREF) with a voltage-divider circuit or the output of a DAC to set the voltage at VCTRL. See Figure 10 when using VREF to generate the voltage for VCTRL. VREF can be used to generate the voltage for VCTRL (Figure 10). If threshold adjust is not required, disable it by connecting VCTRL directly to VCC and leave VREF floating. Table 2. Data-Rate Settings (MAX3874) INPUT DATA RATE (Gbps) RATESET FREFSET 2.667 1 1 or 0 2.488 0 1 or 0 Table 3. Data-Rate Settings (MAX3874A) INPUT DATA RATE (Gbps) RATESET FREFSET 2.0212 0 1 or 0 _______________________________________________________________________________________ 9 MAX3874 Loop Filter and VCO The phase detector and frequency detector outputs are summed into the loop filter. An external capacitor (CFIL) connected from FIL to VCC_VCO is required to set the PLL damping ratio. Note that the PLL jitter bandwidth does not change as the external capacitor changes, but the jitter peaking, acquisition time, and loop stability are affected. See the Design Procedure section for guidelines on selecting this capacitor. The loop filter output controls the two on-chip VCOs. The VCOs provide low phase noise and are trimmed to the 2.488GHz and 2.667GHz frequencies. (The MAX3874A uses a single VCO trimmed to 2.0212GHz.) The RATESET pin is used to select the appropriate VCO. See Tables 2, 3, and 4 for the proper settings. Table 4. Holdover Frequency Settings REFERENCE CLOCK FREQUENCY (MHz) SCLKO FREQUENCY (GHz) RATESET FREFSET 666.51 2.667 1 0 622.08 2.488 0 0 166.63 2.667 1 1 155.52 2.488 0 1 Clock Frequencies in Holdover Mode Set the incoming reference-clock frequency and outgoing serial-clock frequency by setting RATESET and FREFSET appropriately (Table 3). HO(j2πf) (dB) fZ = OPEN-LOOP GAIN Setting the Loop Filter The MAX3874 is designed for both regenerator and receiver applications. Its fully integrated PLL is a classic second-order feedback system, with a jitter transfer bandwidth (JBW) below 2MHz. The external capacitor (CFIL) connected from FIL to VCC_VCO sets the PLL damping. Note that the PLL jitter transfer bandwidth does not change as CFIL changes, but the jitter peaking, acquisition time, and loop stability are affected. Figures 6 and 7 show the open-loop and closed-loop transfer functions. The PLL zero frequency, fZ, is a function of external capacitor CFIL, and can be approximated according to: CFIL = 0.068µF fZ = 3.6kHz CFIL = 0.01µF fZ = 24.5kHz f (kHz) 1 1 2π(650Ω)CFIL CFIL = 0.01µF H(j2πf) (dB) For an overdamped system (fZ / JBW < 0.25), the jitter peaking (JP) of a second-order system can be approximated by: f JP = 20 log1 + Z J BW where JBW is the jitter transfer bandwidth for a given data rate. The recommended value of CFIL = 0.068µF is to guarantee a maximum jitter peaking of less than 0.1dB. Decreasing C FIL from the recommended value decreases acquisition time, with the trade-off of increased peaking. Excessive reduction of CFIL can cause PLL instability. CFIL must be a low-TC, high-quality capacitor of type X7R or better. Input Terminations The SDI± and SLBI± inputs of the MAX3874 are current-mode-logic (CML) compatible. The inputs all pro10 1000 100 10 Figure 6. Open-Loop Transfer Function CLOSED-LOOP GAIN MAX3874 2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier 0 -3 CFIL = 0.068µF f (kHz) 1 10 100 1000 Figure 7. Closed-Loop Transfer Function vide internal 50Ω termination to reduce the required number of external components. AC-coupling is recommended. See Figure 8 for the input structure. For additional information about logic interfacing, refer to Maxim Application Note HFAN 1.0: Introduction to LVDS, PECL, and CML. ______________________________________________________________________________________ 2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier MAX3874 VCC MAX3874 VCC 50Ω 50Ω 50Ω 50Ω SDI+ SDO+ SDI- SDO- MAX3874 Figure 8. CML Input Model Output Terminations The MAX3874 uses CML for its high-speed digital outputs (SDO± and SCLKO±). The configuration of the output circuit includes internal 50Ω back terminations to VCC. See Figure 9 for the output structure. CML outputs can be terminated by 50Ω to VCC, or by 100Ω differential impedance. For additional information on logic interfacing, refer to Maxim Application Note HFAN 1.0: Introduction to LVDS, PECL, and CML. Applications Information Clock Holdover Capability Clock holdover is required in some applications in which a valid clock must be provided to the upstream device in the absence of data transitions. To provide this function, an external reference clock signal must be applied to the SLBI± inputs and the proper control signals set (see the Modes of Operation section). To enter holdover mode automatically when there are no transitions applied to the SDI+ inputs, LOL or the system LOS can be directly connected to LREF. System Loopback The MAX3874 is designed to allow system-loopback testing. When the device is set for system-loopback mode, the serial output data of a transmitter can be directly connected to the SLBI inputs to run system diagnostics. See Table 1 for selecting system loopback operation mode. While in system loopback mode, LREF should not be connected to LOL. Figure 9. CML Output Model Consecutive Identical Digits (CIDs) The MAX3874 has a low phase and frequency drift in the absence of data transitions. As a result, long runs of consecutive zeros and ones can be tolerated while maintaining a BER better than 10-10. The CID tolerance is tested using a 213 - 1 PRBS with long runs of ones and zeros inserted in the pattern. A CID tolerance of 2000 bits is typical. Exposed Pad (EP) Package The EP, 32-pin QFN incorporates features that provide a very low thermal-resistance path for heat removal from the IC. The pad is electrical ground on the MAX3874 and should be soldered to the circuit board for proper thermal and electrical performance. Layout Considerations For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3874 high-speed inputs and outputs. Place power-supply decoupling as close to VCC as possible. To reduce feedthrough, isolate the input signals from the output signals. If a bare die is used, mount the back of die to ground (GND) potential. Figure 10 shows interfacing with the MAX3861 AGC using threshold adjust. ______________________________________________________________________________________ 11 MAX3874 2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier +3.3V +3.3V 0.1µF +3.3V 0.068µF +3.3V FIL VCC_VCO CAZ- CAZ+ VCC FREFSET SDI+ TIA OUTPUT (2.488Gbps) MAX3861 AGC AMPLIFIER SDI- SDO+ SLBI+ SDO- CML R1 155.52MHz REFERENCE CLOCK MAX3874 SLBI- SCLKO+ VCTRL SCLKO- CML VREF SIS LREF LOL RATESET GND R2 TTL R1 + R2 ≥ 50kΩ Figure 10. Interfacing with the MAX3861 AGC Using Threshold Adjust GND VCTRL VREF CAZ- CAZ+ VCC FREFSET GND 31 30 29 28 27 26 25 TOP VIEW 32 Pin Configuration TRANSISTOR COUNT: 5142 PROCESS: SiGe BiPOLAR SUBSTRATE: SOI VCC 1 24 VCC_OUT SDI+ 2 23 SDO+ SDI- 3 22 SDO- VCC 4 21 VCC_OUT 20 SCLKO+ MAX3874 15 GND RATESET 16 17 N.C. 8 14 LREF N.C. VCC_VCO 13 18 VCC_VCO 7 12 SIS FIL SCLKO- 11 19 GND 6 10 SLBI- GND 5 9 SLBI+ LOL Chip Information 5mm x 5mm 32 QFN 12 ______________________________________________________________________________________ 2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier 32L QFN.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX3874 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)