19-2718; Rev 2; 4/09 2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier Features The MAX3882A is a deserializer combined with clock and data recovery and limiting amplifier ideal for converting 2.488Gbps serial data to 4-bit-wide, 622Mbps parallel data for SDH/SONET applications. The device accepts serial NRZ input data as low as 10mVP-P of 2.488Gbps and generates four parallel LVDS data outputs at 622Mbps. Included is an additional high-speed serial data input for system loopback diagnostic testing. For data acquisition, the MAX3882A does not require an external reference clock. However, if needed, the loopback input can be connected to an external reference clock of 155MHz or 622MHz to maintain a valid clock output in the absence of input data transitions. Additionally, a TTL-compatible loss-of-lock output is provided. The device provides a vertical threshold adjustment to compensate for optical noise generated by EDFAs in WDM transmission systems. The MAX3882A operates from a single +3.3V supply and consumes 610mW. The MAX3882A’s jitter performance exceeds all SDH/ SONET specifications. The device is available in a 6mm ✕ 6mm, 36-pin TQFN package. ♦ No Reference Clock Required for Data Acquisition ♦ Serial Input Rate: 2.488Gbps ♦ Fully Integrated Clock and Data Recovery with Limiting Amplifier and 1:4 Demultiplexer ♦ Parallel Output Rate: 622Mbps ♦ Differential Input Range: 10mVP-P to 1.6VP-P without Threshold Adjust ♦ Differential Input Range: 50mVP-P to 600mVP-P with Threshold Adjust ♦ 0.65UI High-Frequency Jitter Tolerance ♦ Loss-of-Lock (LOL) Indicator ♦ Wide Input Threshold Adjust Range: ±170mV ♦ Maintain Valid Clock Output in Absence of Data Transitions ♦ System Loopback Input Available for System Diagnostic Testing ♦ Operating Temperature Range -40°C to +85°C ♦ Low Power Dissipation: 610mW at +3.3V Applications Ordering Information SDH/SONET Receivers and Regenerators PART TEMP RANGE PIN-PACKAGE -40°C to +85°C 36 TQFN-EP* Add/Drop Multiplexers MAX3882AETX+ Digital Cross-Connects +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. SDH/SONET Test Equipment Pin Configuration Typical Application Circuits appear at end of data sheet. PD3- PD2+ PD2- GND PD1+ PD1- PD0+ PD0- TOP VIEW PD3+ DWDM Transmission Systems 27 26 25 24 23 22 21 20 19 VCC_OUT 28 18 PCLK+ GND 29 17 PCLK- FREFSET 30 16 GND VCC 31 15 VCC_OUT VCC 32 14 VCC_VCO CAZ+ 33 13 FIL CAZ- 34 12 VCC_VCO VREF 35 11 GND VCTRL 36 10 LREF MAX3882A *EP SDI+ SDI- 6 7 8 9 LOL VCC 5 SIS 4 SLBI- 3 SLBI+ 2 VCC 1 GND + TQFN *EXPOSED PAD. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3882A General Description MAX3882A 2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC ................................................-0.5 to +5.0V Input Voltage Levels (SDI+, SDI-, SLBI+, SLBI-) ...........(VCC - 1.0V) to (VCC + 0.5V) Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)..............±20mA LVDS Output Voltage Levels (PCLK±, PD_±).......................................-0.5V to (VCC + 0.5V) Voltage at LOL, SIS, LREF, VREF, FIL, CAZ+, CAZ-, VCTRL, FREFSET ..........................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +70°C) 36-Pin TQFN (derate 35.7mW/°C above +70°C) ......2856mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0 to +3.6V, TA = -40°C to +85°C. Typical values are at +3.3V and at TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL Supply Current ICC Single-Ended Input Voltage Range VIS Input Common-Mode Voltage Range Input Termination to VCC Threshold-Control Voltage MIN VCC + 0.4 V Figure 1 VCC 0.4 VCC V 57.5 42.5 50 600 mVP-P VTH Figure 2 -170 +170 mV VCTRL (Note 2) 0.302 2.097 ±5 Figure 2 VREF Voltage Output -18 +18 -6 +6 80mV < |VTH| 170mV -12 +12 RL = 50k 2.14 VOH LVDS Output Low Voltage VOL 0.925 |V OD | 250 2.2 LVDS Offset Output Voltage 2.24 1.475 |V OD | 1.125 |V OS | _______________________________________________________________________________________ V % 15mV |VTH| 80mV LVDS Output High Voltage 2 mA 100 Threshold Setting Stability LVDS Change in Magnitude of Output Offset Voltage for Complementary States UNITS 230 Figure 2 Threshold Setting Accuracy LVDS Change in Magnitude of Differential Output Voltage for Complementary States MAX 185 VCC 0.8 Threshold-Control Linearity LVDS Differential Output Voltage TYP Figure 1 RIN Differential Input Voltage Range with Threshold Adjust Enabled SDI+, SDIThreshold Adjustment Range CONDITIONS mV mV V V V 400 mV 25 mV 1.275 V 25 mV 2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier MAX3882A DC ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0 to +3.6V, TA = -40°C to +85°C. Typical values are at +3.3V and at TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS LVDS Differential Output Impedance MIN TYP 80 LVDS Output Current Short together or short to GND LVTTL Input High Voltage VIH LVTTL Input Low Voltage VIL MAX UNITS 120 12 mA 2.0 LVTTL Input Current V -10 LVTTL Output High Voltage VOH I OH = +20μA LVTTL Output Low Voltage VOL I OL = -1mA 0.8 V +10 μA 2.4 V 0.4 V Note 1: At -40°C, DC characteristics are guaranteed by design and characterization. Note 2: Voltage applied to VCTRL pin is from 0.302V to 2.097V when input threshold is adjusted from +170mV to -170mV. AC ELECTRICAL CHARACTERISTICS (VCC = +3.0 to +3.6V, TA = -40°C to +85°C. Typical values are at +3.3V and at TA = +25°C, unless otherwise noted.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN Serial Input Data Rate Differential Input Voltage Threshold Adjust Disabled SDI+, SDI- VID (Note 4) Figure 1 Differential Input Voltage SLBI+, SLBIJitter Peaking JP Jitter Transfer Bandwidth Sinusoidal Jitter Tolerance with Threshold Adjust Enabled (Note 5) J GEN Differential Input Return Loss Tolerated Consecutive Identical Digits MAX 20log|S11| UNITS Gbps 10 1600 mVP-P 50 800 mVP-P f 2MHz JBW Sinusoidal Jitter Tolerance Jitter Generation TYP 2.488 1.7 f = 100kHz 3.1 4.1 f = 1MHz 0.62 1.0 f = 10MHz 0.44 0.6 f = 100kHz 4.1 f = 1MHz 0.75 f = 10MHz 0.41 (Note 6) 2.7 100kHz to 2.5GHz 17 2.5GHz to 4.0GHz 15 BER = 10-10 2000 Acquisition Time (Note 7) Figure 4 0011 pattern 0.6 PRBS 223 - 1 pattern 0.62 LOL Assert Time Figure 4 Low-Frequency Cutoff for DC Offset Cancellation Loop CAZ = 0.1μF 2.3 0.1 dB 2.0 MHz UI P-P UI P-P psRMS dB Bits 1.5 100.0 4 ms μs kHz _______________________________________________________________________________________ 3 MAX3882A 2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier AC ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0 to +3.6V, TA = -40°C to +85°C. Typical values are at +3.3V and at TA = +25°C, unless otherwise noted.) (Note 3) PARAMETER SYMBOL Reference Clock Frequency CONDITIONS MIN FREFSET = VCC 155 FREFSET = GND 622 Reference Clock Accuracy VCO Frequency Drift (Note 8) Data Output Rate Clock Output Frequency Output Clock-to-Data Delay MAX (Note 9) ±100 ppm 400 ppm 622 Mbps -80 45 tR, tF 20% to 80% LVDS Differential Skew t SKEW1 Any differential pair LVDS Channel-to-Channel Skew t SKEW2 PD_± UNITS MHz 622 tCK-Q Clock Output Duty Cycle Clock and Data Output Rise/Fall Time TYP 50 100 MHz +80 ps 55 % 250 ps 50 ps 100 ps Note 3: AC characteristics are guaranteed by design and characterization. Note 4: Jitter tolerance is guaranteed (BER ≤ 10-10) within this input voltage range. Input threshold adjust is disabled when VCTRL is connected to VCC. Note 5: Measured with the input amplitude set at 100mVP-P differential swing with a 20mV offset and an input edge speed of 145ps (4th-order Bessel filter with f3dB = 1.8GHz). Note 6: Measured with 10mVP-P OC-48 differential input with PRBS 223 - 1 and BW = 12kHz to 20MHz. Note 7: Measured at OC-48 data rate using a 0.068µF loop-filter capacitor. Note 8: Under LOL condition, the CDR clock output is set by the external reference clock. Note 9: Relative to the falling edge of PCLK+. See Figure 3. 4 _______________________________________________________________________________________ 2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier RECOVERED CLOCK AND DATA (INPUT = 2.488Gbps, 223 - 1 PATTERN, VIN = 10mVP-P) JITTER TOLERANCE (2.48832Gbps, 223 - 1 PATTERN, VIN = 16mVP-P WITH ADDITIONAL 0.15UI DETERMINISTIC JITTER) SUPPLY CURRENT vs. TEMPERATURE 230 220 210 200 190 MAX3882A toc03 240 100 JITTER TOLERANCE (UIP-P) 250 SUPPLY CURRENT (mA) 200mV/div MAX3882A toc02 MAX3882A toc01 260 10 1 BELLCORE MASK 180 170 0.1 -50 -25 0 JITTER TOLERANCE vs. INPUT AMPLITUDE (2.48832Gbps, 223 - 1 PATTERN, WITH ADDITIONAL 0.15UI DETERMINISTIC JITTER) 0.4 0.3 100 1k TEMPERATURE (°C) JITTER FREQUENCY (Hz) JITTER TRANSFER PARALLEL CLOCK OUTPUT JITTER -5 fCLK = 622.08MHz TOTAL WIDEBAND RMS JITTER = 2.720ps PEAK-TO-PEAK JITTER = 20.80ps BELLCORE MASK -10 10k -15 -20 -25 0.2 -30 0.1 -35 -40 0 10 100 1000 1 10,000 10 100 1000 10,000 20ps/div JITTER FREQUENCY (kHz) INPUT AMPLITUDE (mVP-P) BIT-ERROR RATE vs. INPUT AMPLITUDE PULLIN RANGE 2.9 2.8 1.00E-07 1.00E-08 2.7 0 2.6 2.5 -20 2.2 1.00E-10 -10 2.4 2.3 1.00E-09 10 dB FREQUENCY (GHz) 1.00E-06 20 MAX3882A toc08 1.00E-05 S11 3.0 MAX3882A toc07 1.00E-04 MAX3882A toc09 1 BIT-ERROR RATIO 10 100 MAX3882A toc05 JITTER FREQUENCY = 10MHz 75 0 TRANSFER (dB) JITTER TOLERANCE (UIP-P) 0.5 50 5 MAX3882A toc04 0.6 25 MAX3882A toc06 160 500ps/div -30 2.1 1.00E-11 -40 2.0 1 2 3 4 INPUT VOLTAGE (mVP-P) 5 -40 -15 10 35 60 AMBIENT TEMPERATURE (°C) 85 0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (MHz) _______________________________________________________________________________________ 5 MAX3882A Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) MAX3882A 2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier Pin Description PIN NAME 1, 11, 16, 23, 29 GND 6 FUNCTION Supply Ground 2, 5, 31, 32 VCC +3.3V Supply Voltage 3 SDI+ Positive Data Input. 2.488Gbps serial data stream, CML. 4 SDI- Negative Data Input. 2.488Gbps serial data stream, CML. 6 SLBI+ Positive System Loopback Input or Positive Reference Clock Input, CML 7 SLBI- Negative System Loopback Input or Negative Reference Clock Input, CML 8 SIS Signal Input Selection, LVTTL. Low for normal data, high for system loopback. 9 LOL Loss-of-Lock Output, LVTTL, Active Low 10 LREF TTL Control Input for PLL Clock Holdover. Low for PLL lock to reference clock, high for PLL lock to input data. 12, 14 VCC_VCO 13 FIL 15, 28 VCC_OUT Supply Voltage for the VCO PLL Loop-Filter Capacitor Input. Connect a 0.068μF loop-filter capacitor between FIL and VCC_VCO. Supply Voltage for LVDS Output Buffers 17 PCLK- Negative Clock Output, LVDS 18 PCLK+ Positive Clock Output, LVDS 19 PD0- Negative Data Output, LVDS 20 PD0+ Positive Data Output, LVDS 21 PD1- Negative Data Output, LVDS 22 PD1+ Positive Data Output, LVDS 24 PD2- Negative Data Output, LVDS 25 PD2+ Positive Data Output, LVDS 26 PD3- Negative Data Output, LVDS, MSB 27 PD3+ Positive Data Output, LVDS, MSB Sets Reference Frequency. LVTTL low for 622MHz/667MHz reference, high for 155MHz/167MHz reference. 30 FREFSET 33 CAZ+ Positive Capacitor Input for DC Offset-Cancellation Loop. Connect a 0.1μF capacitor between CAZ+ and CAZ-. 34 CAZ- Negative Capacitor Input for DC Offset-Cancellation Loop. Connect a 0.1μF capacitor between CAZ+ and CAZ-. 35 VREF 2.2V Bandgap Reference Voltage Output. Optionally used for threshold adjustment. 36 VCTRL Analog Control Input for Threshold Adjustment. Connect to VCC to disable threshold adjust. — EP Exposed Pad. The exposed pad must be soldered to the circuit board ground for proper thermal and electrical performance. _______________________________________________________________________________________ 2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier The MAX3882A deserializer with clock and data recovery and limiting amplifier converts 2.488Gbps serial data to clean 4-bit-wide, 622Mbps LVDS parallel data. The device combines a limiting amplifier with a fully integrated phase-locked loop (PLL), data retiming block, 4bit demultiplexer, clock divider, and LVDS output buffer (Figure 5). The PLL consists of a phase/frequency detector (PFD), loop filter, and voltage- controlled oscillator (VCO). The MAX3882A is designed to deliver the best combination of jitter performance and power dissi- pation by using a fully differential signal architecture and low-noise design techniques. The input signal to the device (SDI) passes through a DC offset control block, which balances the input signal to a zero crossing at 50%. The PLL recovers the serial clock from the serial input data stream and produces the properly aligned data and the buffered recovered clock. The frequency of the recovered clock is divided by four and converted to differential LVDS parallel output PCLK. The demultiplexer generates 4-bit-wide 622Mbps parallel data. VTH (mV) VCC + 0.4V 5mV 800mV +188 VCC THRESHOLD-SETTING ACCURACY (PART-TO-PART VARIATION OVER PROCESS) +170 +152 VCC - 0.4V (a) AC-COUPLED SINGLE-ENDED INPUT 1.3 5mV 1.1 0.3 VCTRL (V) 2.1 VCC 800mV -152 VCC - 0.4V -170 -188 VCC - 0.8V THRESHOLD-SETTING STABILITY (OVER TEMPERATURE AND POWER SUPPLY) (b) DC-COUPLED SINGLE-ENDED INPUT Figure 1. Definition of Input Voltage Swing Figure 2. Relationship Between Control Voltage and Threshold Voltage tCK 2.488Gbps PRBS 223 - 1 2.488Gbps PRBS 223 - 1 INPUT DATA PCLK+ tCK-Q LOL ASSERT TIME (PD+) - (PD-) ACQUISITION TIME LOL OUTPUT Figure 3. Definition of Clock-to-Q Delay Figure 4. LOL Assert Time and PLL Acquisition Time Measurement _______________________________________________________________________________________ 7 MAX3882A Detailed Description MAX3882A 2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier Input Amplifier The SDI inputs of the MAX3882A accept serial NRZ data at 2.488Gbps with 10mVP-P to 1600mVP-P amplitude. The input sensitivity is 10mVP-P, at which the jitter tolerance is met for a BER of 10-10 when the threshold adjust is not used. The input sensitivity is as low as 4mVP-P for a BER of 10-10. The MAX3882A is designed to directly interface with a transimpedance amplifier (MAX3277). For applications when vertical threshold adjustment is needed, the MAX3882A can be connected to the output of an AGC amplifier (MAX3861). Here, the input voltage range is 50mVP-P to 600mVP-P. See the Design Procedure section for decision threshold adjust. Phase Detector jitter transfer bandwidth does not change as the external capacitor changes, but the jitter peaking, acquisition time, and loop stability are affected. For an overdamped system (f Z /f L ) < 0.25, the jitter peaking (JP) of a second-order system can be approximated by: JP = 20log(1 + fZ/fL) The PLL zero frequency (fZ) is a function of the external capacitor (CFIL) and can be approximated according to: fZ = 1/2π(650)CFIL Figures 6 and 7 show the open-loop and closed-loop transfer functions. The PLL acquisition time is also directly proportional to the external capacitor CFIL. Loss-of-Lock Monitor The phase detector in the MAX3882A produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. The LOL output indicates a PLL lock failure, either due to excessive jitter present at data input or due to loss of input data. In the case of loss of input data, the LOL indicates a loss-of-signal condition. The LOL output is asserted low when the PLL loses lock. Frequency Detector The MAX3882A’s clock and data outputs are LVDS compatible to minimize power dissipation, speed transition time, and improve noise immunity. These outputs comply with the IEEE LVDS specification. The differential output signal magnitude is 250mV to 400mV. The digital frequency detector (FD) acquires frequency lock without using an external reference clock. The frequency difference between the received data and the VCO clock is derived by sampling the in-phase and quadrature VCO outputs on both edges of the data input signal. Depending on the polarity of the frequency difference, the FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the FD returns to a neutral state. False locking is eliminated by this digital frequency detector. Loop Filter and VCO The fully integrated PLL has a second-order transfer function, with a loop bandwidth (fL) fixed at 1.7MHz. An external capacitor between VCC_VCO and FIL sets the damping of the PLL. All jitter specifications are based on the CFIL capacitor being 0.068µF. Note that the PLL Output LVDS Interface: PD, PCLK Design Procedure The MAX3882A provides a differential output clock (PCLK). Table 1 shows the pin configuration for choosing the type of operation mode. Decision Threshold Adjust Decision threshold adjust is available for WDM applications where optical amplifiers are used, generating spontaneous optical noise at data logic high. The decision threshold adjust range is ±170mV. Use the provided 2.2V bandgap reference VREF pin or an outside source, such as an output from a DAC to control the Table 1. Operation Modes FREFSET 8 LREF SIS OPERATION MODE DESCRIPTION X 1 0 Normal operation: PLL locked to data input at 2.488Gbps X 1 1 System loopback: PLL lock frequency at 2.488Gbps 1 0 X Clock holdover: PLL locked to reference frequency at 155MHz 0 0 X Clock holdover: PLL locked to reference frequency at 622MHz _______________________________________________________________________________________ 2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier MAX3882A CAZ CAZ+ CAZ- PDO+ LVDS BANDGAP REFERENCE VREF PDO- MAX3882A PD1+ SDI+ DC OFFSET CANCELLATION AMP SDI- 0 1 LVDS D Q CK PD1- 4-BIT DEMULTIPLEXER PD2+ VCTRL LVDS PD2PD3+ SLBI+ AMP LVDS PD3- SLBILPF PFD LREF SIS FREFSET VCO PCLK+ DIV/4 LOGIC LVDS PLL PCLK- FIL LOL VCC Figure 5. Functional Diagram CFIL = 0.01μF HO(j2πf) (dB) CLOSED-LOOP GAIN OPEN-LOOP GAIN HO(j2πf) (dB) CFIL = 0.01μF fZ = 2.45kHz CFIL = 0.068μF fZ = 3.6kHz 0 -3 CFIL = 0.068μF f = (kHz) f = (kHz) 1 10 100 1000 Figure 6. Open-Loop Transfer Function threshold voltage. The +170mV to -170mV threshold offset can be accomplished by varying the VCTRL voltage from 0.3V to 2.1V, respectively. See Figure 2. When using the VREF to generate voltage for threshold setting, see Figure 8. Connect VCTRL directly to VCC to disable threshold adjust. 1 10 100 1000 Figure 7. Closed-Loop Transfer Function DC-Offset Cancellation Loop Filter A DC-offset cancellation loop is implemented to remove the DC offset of the limiting amplifier. To minimize the low-frequency pattern-dependent jitter associated with this DC-cancellation loop, the low-frequency cutoff is 10kHz typical with CAZ = 0.1µF, connected across CAZ+ and CAZ-. _______________________________________________________________________________________ 9 MAX3882A 2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier Applications Information Clock Holdover Capability Clock holdover is required in some applications where a valid clock needs to be provided to the upstream device in the absence of data transitions. To provide this function, an external reference clock rate of 155MHz or 622MHz must be applied to the SLBI input. Control input FREFSET selects which reference clock rate to use. The control LREF selects whether the PLL locks to the input data stream (SDI) or the reference clock (SLBI). When LREF is low, the input is switched to the reference clock input. This LREF input can be driven by connecting the LOL output pin directly or connecting to any other power monitor signal from the system. System Loopback The MAX3882A is designed to allow system loopback testing. The user can connect the serializer output (MAX3892) directly to the SLBI± inputs of the MAX3882A for system diagnostics. See Table 1 for selecting the system loopback operation mode. During system loopback, LOL cannot be connected to LREF. 10 Interfacing the MAX3882A To correctly interface with the MAX3882A’s CML input and LVDS outputs, refer to Application Note 291: HFAN-1.0: Introduction to LVDS, PECL, and CML. Layout Techniques For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3882A high-speed inputs and outputs. Power-supply decoupling should be placed as close to the VCC as possible. To reduce feedthrough, isolate input signals from output signals. Exposed-Paddle Package The exposed pad, 36-pin TQFN incorporates features that provide a very low thermal-resistance path for heat removal from the IC. The pad is electrical ground on the MAX3882A and should be soldered to the circuit board for proper thermal and electrical performance. ______________________________________________________________________________________ 2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier MAX3882A +3.3V 0.068μF SIS 155MHz CLOCK +3.3V FIL VCC LREF LOL VCC PD3+ 100Ω* SLBI+ PD3- SLBIPD2+ 100Ω* MAX3882A PD2- 0.1μF SDI+ TIA OUTPUT AGC PD1+ SDI- 100Ω* 0.1μF VCTRL MAX3861 OVERHEAD TERMINATION PD1- R1 VREF PD0+ R2 R1 + R2 ≥ 50kΩ 100Ω* PD0- PCLK+ 100Ω* FREFSET CAZ+ CAZ- +3.3V PCLK- 0.1μF *REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω. Figure 8. Connecting the MAX3882A with Threshold Adjust and Clock Holdover Enabled ______________________________________________________________________________________ 11 2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier MAX3882A Typical Application Circuit +3.3V 0.068μF SYSTEM LOOPBACK SIS FIL VCC LREF LOL VCC PD3+ +3.3V 100Ω* SLBI+ 0.01μF PD3- SLBIPD2+ 100Ω* MAX3882A PD2- 0.1μF SDI+ TIA PD1+ SDI- 100Ω* 0.1μF VCTRL OVERHEAD TERMINATION PD1- MAX3277 VREF PD0+ 100Ω* PD0+3.3V PCLK+ 100Ω* PCLKFREFSET CAZ+ CAZ- 0.1μF *REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω. Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. 12 PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 36 TQFN-EP T3666-2 21-0141 ______________________________________________________________________________________ 2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier REVISION NUMBER REVISION DATE 0 1/03 1 11/05 2 4/09 DESCRIPTION PAGES CHANGED Initial release (MAX3882 only). — Added the MAX3882A. All Removed the MAX3882. All Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX3882A Revision History