19-2718; Rev 0; 1/03 2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier Features ♦ No Reference Clock Required for Data Acquisition ♦ Input Data Rates: 2.488Gbps or 2.67Gbps ♦ Fully Integrated Clock and Data Recovery with Limiting Amplifier and 1:4 Demultiplexer ♦ Parallel Output Rate: 622Mbps/667Mbps ♦ Differential Input Range: 10mVP-P to 1.6VP-P without Threshold Adjust ♦ Differential Input Range: 50mVP-P to 600mVP-P with Threshold Adjust ♦ 0.65UI High-Frequency Jitter Tolerance ♦ Loss-of-Lock (LOL) Indicator ♦ Wide Input Threshold Adjust Range: ±170mV ♦ Maintain Valid Clock Output in Absence of Data Transitions ♦ System Loopback Input Available for System Diagnostic Testing ♦ Operating Temperature Range -40°C to +85°C ♦ Low Power Dissipation: 610mW at +3.3V The MAX3882’s jitter performance exceeds all SDH/ SONET specifications. The device is available in a 6mm ✕ 6mm 36-pin QFN package. TEMP RANGE PINPACKAGE PKG CODE MAX3882EGX -40oC to +85oC 36 QFN G3666-1 Add/Drop Multiplexers Pin Configuration VCTRL VREF CAZ- CAZ+ VCC VCC FREFSET RATESET VCC_OUT 35 34 33 32 31 30 29 28 TOP VIEW DWDM Transmission Systems GND 1 27 PD3+ VCC 2 26 PD3- SDI+ 3 25 PD2+ SDI- 4 24 PD2- VCC 5 23 GND SLBI+ 6 22 PD1+ SLBI- 7 21 PD1- SIS 8 20 PD0+ LOL 9 19 PD0- 16 17 18 GND PCLK+ 13 FIL PCLK- 12 VCC_VCO 15 11 14 10 GND MAX3882 LREF SDH/SONET Test Equipment 36 Digital Cross-Connects VCC_OUT SDH/SONET Receivers and Regenerators PART VCC_VCO Applications Ordering Information QFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3882 General Description The MAX3882 is a deserializer combined with clock and data recovery and limiting amplifier ideal for converting 2.488Gbps/2.67Gbps serial data to 4-bit-wide, 622Mbps/667Mbps parallel data for SDH/SONET applications. The device accepts serial NRZ input data as low as 10mVP-P of 2.488Gbps/2.67Gbps and generates four parallel LVDS data outputs at 622Mbps/667Mbps. Included is an additional high-speed serial data input for system loopback diagnostic testing. For data acquisition, the MAX3882 does not require an external reference clock. However, if needed, the loopback input can be connected to an external reference clock of 155MHz/167MHz or 622MHz/667MHz to maintain a valid clock output in the absence of input data transitions. Additionally, a TTL-compatible loss-of-lock output is provided. The device provides a vertical threshold adjustment to compensate for optical noise generated by EDFAs in WDM transmission systems. The MAX3882 operates from a single +3.3V supply and consumes 610mW. MAX3882 2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC ................................................-0.5 to +5.0V Input Voltage Levels (SDI+, SDI-, SLBI+, SLBI-) ...........(VCC - 1.0V) to (VCC + 0.5V) Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)..............±20mA LVDS Output Voltage Levels (PCLK±, PD_±).......................................-0.5V to (VCC + 0.5V) Voltage at LOL, RATESET, SIS, LREF, VREF, FIL, CAZ+, CAZ-, VCTRL, FREFSET ..........................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85°C) 36-Lead QFN (derate 32.4mW/°C above +85°C) .......830mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0 to +3.6V, TA = -40°C to +85°C. Typical values are at +3.3V and at TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL Supply Current ICC Single-Ended Input Voltage Range VIS Input Common-Mode Voltage Range Input Termination to VCC Threshold-Control Voltage MIN V Figure 1 VCC 0.4 VCC V 57.5 Ω 600 mVP-P 42.5 100 Figure 2 -170 +170 mV (Note 2) 0.302 2.097 V Figure 2 -18 +18 mV 15mV ≤ |VTH| ≤ 80mV -6 +6 80mV < |VTH| ≤ 170mV -12 +12 RL = 50kΩ 2.14 ±5 LVDS Output High Voltage VOH LVDS Output Low Voltage VOL 0.925 VOD 250 2.2 ∆VOD LVDS Offset Output Voltage 2 50 VTH VREF Voltage Output LVDS Differential Output Impedance mA VCTRL Threshold Setting Stability LVDS Change in Magnitude of Output Offset Voltage for Complementary States UNITS 230 VCC + 0.4 Figure 2 Threshold Setting Accuracy LVDS Change in Magnitude of Differential Output Voltage for Complementary States MAX 185 VCC 0.8 Threshold-Control Linearity LVDS Differential Output Voltage TYP Figure 1 RIN Differential Input Voltage Range with Threshold Adjust Enabled SDI+, SDIThreshold Adjustment Range CONDITIONS 1.125 ∆VOS 80 _______________________________________________________________________________________ % mV 2.24 V 1.475 V V 400 mV 25 mV 1.275 V 25 mV 120 Ω 2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier MAX3882 DC ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0 to +3.6V, TA = -40°C to +85°C. Typical values are at +3.3V and at TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL LVDS Output Current CONDITIONS MIN TYP Short together or short to GND LVTTL Input High Voltage VIH LVTTL Input Low Voltage VIL MAX UNITS 12 mA 2.0 LVTTL Input Current V -10 LVTTL Output High Voltage VOH IOH = +20µA LVTTL Output Low Voltage VOL IOL = -1mA 0.8 V +10 µA 2.4 V 0.4 V Note 1: At -40°C, DC characteristics are guaranteed by design and characterization. Note 2: Voltage applied to VCTRL pin is from 0.302V to 2.097V when input threshold is adjusted from +170mV to -170mV. AC ELECTRICAL CHARACTERISTICS (VCC = +3.0 to +3.6V, TA = -40°C to +85°C. Typical values are at +3.3V and at TA = +25°C, unless otherwise noted.) (Note 3) PARAMETER SYMBOL Serial Input Data Rate Differential Input Voltage Threshold Adjust Disabled SDI+, SDI- VID CONDITIONS JP Jitter Transfer Bandwidth RATESET = 1 2.667 (Note 4) Figure 1 Sinusoidal Jitter Tolerance with Threshold Adjust Enabled (Note 5) Jitter Generation JGEN Differential Input Return Loss 20log|S11| 50 800 mVP-P f = 100kHz 3.1 4.1 f = 1MHz 0.62 1.0 f = 10MHz 0.44 0.6 f = 100kHz 4.1 f = 1MHz 0.75 f = 10MHz 0.41 (Note 6) 2.7 100kHz to 2.5GHz 17 2.5GHz to 4.0GHz 15 Acquisition Time (Note 7) Figure 4 LOL Assert Time Figure 4 Low-Frequency Cutoff for DC Offset-Cancellation Loop CAZ = 0.1µF Gbps mVP-P 1.7 BER = 10-10 UNITS 1600 f ≤ 2MHz Tolerated Consecutive Identical Digits MAX 10 JBW Sinusoidal Jitter Tolerance TYP 2.488 Differential Input Voltage SLBI+, SLBIJitter Peaking MIN RATESET = 0 0.1 dB 2.0 MHz UIP-P UIP-P psRMS dB 2000 2.3 4 Bits 1.0 ms 100.0 µs kHz _______________________________________________________________________________________ 3 MAX3882 2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier AC ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0 to +3.6V, TA = -40°C to +85°C. Typical values are at +3.3V and at TA = +25°C, unless otherwise noted.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN FREFSET = VCC, RATESET = GND Reference Clock Frequency 167 FREFSET = GND, RATESET = GND 622 (Note 8) Clock Output Frequency Output Clock-to-Data Delay TCK-Q Clock and Data Output Rise/Fall Time ppm 622 667 RATESET = 0 622 RATESET = 1 667 -80 45 tR , tF ppm 400 RATESET = 1 (Note 9) 20% to 80% MHz ±100 RATESET = 0 Clock Output Duty Cycle UNITS 667 RATESET = VCC Data Output Rate MAX 155 RATESET = VCC Reference Clock Accuracy VCO Frequency Drift TYP 50 100 Mbps MHz +80 ps 55 % 250 ps LVDS Differential Skew tSKEW1 Any differential pair 50 ps LVDS Channel-to-Channel Skew tSKEW2 PD_± 100 ps Note 3: AC characteristics are guaranteed by design and characterization. Note 4: Jitter tolerance is guaranteed (BER ≤ 10-10) within this input voltage range. Input threshold adjust is disabled when VCTRL is connected to VCC. Note 5: Measured with the input amplitude set at 100mVP-P differential swing with a 20mV offset and an input edge speed of 145ps (4th-order Bessel filter with f3dB = 1.8GHz). Note 6: Measured with 10mVP-P OC-48 differential input with PRBS 223 - 1 and BW = 12kHz to 20MHz. Note 7: Measured at OC-48 data rate using a 0.068µF loop-filter capacitor. Note 8: Under LOL condition, the CDR clock output is set by the external reference clock. Note 9: Relative to the falling edge of PCLK+. See Figure 3. 4 _______________________________________________________________________________________ 2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier RECOVERED CLOCK AND DATA (INPUT = 2.488Gbps, 223 - 1 PATTERN, VIN = 10mVP-P) JITTER TOLERANCE (2.48832Gbps, 223 - 1 PATTERN, VIN = 16mVP-P WITH ADDITIONAL 0.15UI DETERMINISTIC JITTER) SUPPLY CURRENT vs. TEMPERATURE JITTER TOLERANCE (UIP-P) SUPPLY CURRENT (mA) 240 230 220 210 200 190 MAX3882 toc03 250 200mV/div 100 MAX3882 toc02 MAX3882 toc01 260 10 1 BELLCORE MASK 180 170 0.1 160 JITTER TOLERANCE vs. INPUT AMPLITUDE (2.48832Gbps, 223 - 1 PATTERN, WITH ADDITIONAL 0.15UI DETERMINISTIC JITTER) JITTER FREQUENCY = 10MHz 25 50 75 TRANSFER (dB) 100 1k TEMPERATURE (°C) JITTER FREQUENCY (Hz) JITTER TRANSFER PARALLEL CLOCK OUTPUT JITTER MAX3882 toc05 -5 0.3 10 100 0 0.4 fCLK = 622.08MHz TOTAL WIDEBAND RMS JITTER = 2.720ps PEAK-TO-PEAK JITTER = 20.80ps BELLCORE MASK -10 10k -15 -20 -25 0.2 -30 0.1 -35 -40 0 1 10 100 1 10,000 1000 10 100 1000 20ps/div 10,000 JITTER FREQUENCY (kHz) INPUT AMPLITUDE (mVP-P) PULLIN RANGE (RATESET = 0) BIT-ERROR RATE vs. INPUT AMPLITUDE 1.00E-05 2.9 2.8 FREQUENCY (GHz) 1.00E-06 1.00E-07 1.00E-08 MAX3882 toc08 3.0 MAX3882 toc07 1.00E-04 BIT-ERROR RATIO JITTER TOLERANCE (UIP-P) 0.5 0 5 MAX3882 toc04 0.6 -25 MAX3882 toc06 -50 500ps/div 2.7 2.6 2.5 2.4 2.3 1.00E-09 2.2 1.00E-10 2.1 1.00E-11 2.0 1 2 3 4 INPUT VOLTAGE (mVP-P) 5 -40 -15 10 35 60 85 AMBIENT TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX3882 Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) JITTER TOLERANCE vs. VCTRL (2.67Gbps, 223 - 1 PATTERN, VIN = 100mVP-P) INPUT FILTERED WITH AN 1870MHz FILTER MAX3882 toc10 0.6 S11 20 MAX3882 toc09 0.7 10 0.5 0 0.4 dB SINUSOIDAL JITTER TOLERANCE (UIP-P) 1MAX3882 2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier -10 0.3 -20 0.2 -30 0.1 JITTER FREQUENCY = 5MHz 0 -40 1.05 1.10 1.15 1.20 1.25 1.30 VCTRL (V) 0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (MHz) Pin Description 6 PIN NAME FUNCTION 1, 11, 16, 23 GND Supply Ground 2, 5, 31, 32 VCC +3.3V Supply Voltage 3 SDI+ Positive Data Input. 2.488Gbps/2.67Gbps serial data stream, CML. 4 SDI- Negative Data Input. 2.488Gbps/2.67Gbps serial data stream, CML. 6 SLBI+ Positive System Loopback Input or Positive Reference Clock Input, CML 7 SLBI- Negative System Loopback Input or Negative Reference Clock Input, CML 8 SIS Signal Input Selection, LVTTL. Low for normal data, high for system loopback. 9 LOL Loss-of-Lock Output, LVTTL, Active Low 10 LREF TTL Control Input for PLL Clock Holdover. Low for PLL lock to reference clock, high for PLL lock to input data. 12, 14 VCC_VCO 13 FIL 15, 28 VCC_OUT 17 PCLK- 18 PCLK+ Positive Clock Output, LVDS 19 PD0- Negative Data Output, LVDS 20 PD0+ Positive Data Output, LVDS 21 PD1- Negative Data Output, LVDS 22 PD1+ Positive Data Output, LVDS Supply Voltage for the VCO PLL Loop-Filter Capacitor Input. Connect a 0.068µF loop-filter capacitor between FIL and VCC_VCO. Supply Voltage for LVDS Output Buffers Negative Clock Output, LVDS _______________________________________________________________________________________ 2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier PIN NAME 24 PD2- 25 PD2+ Positive Data Output, LVDS 26 PD3- Negative Data Output, LVDS, MSB 27 PD3+ Positive Data Output, LVDS, MSB 29 RATESET Sets the VCO frequency. LVTTL low for 2.488Gbps operation, high for 2.67Gbps operation. 30 FREFSET Sets Reference Frequency. LVTTL low for 622MHz/667MHz reference, high for 155MHz/167MHz reference. 33 CAZ+ Positive Capacitor Input for DC Offset-Cancellation Loop. Connect a 0.1µF capacitor between CAZ+ and CAZ-. 34 CAZ- Negative Capacitor Input for DC Offset-Cancellation Loop. Connect a 0.1µF capacitor between CAZ+ and CAZ-. 35 VREF 2.2V Bandgap Reference Voltage Output. Optionally used for threshold adjustment. 36 VCTRL Analog Control Input for Threshold Adjustment. Connect to VCC to disable threshold adjust. EP FUNCTION Negative Data Output, LVDS Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and Exposed Pad electrical performance. Detailed Description The MAX3882 deserializer with clock and data recovery and limiting amplifier converts 2.488Gbps/2.67Gbps serial data to clean 4-bit-wide, 622Mbps/667Mbps LVDS parallel data. The device combines a limiting amplifier with a fully integrated phase-locked loop (PLL), data retiming block, 4-bit demultiplexer, clock divider, and LVDS output buffer (Figure 5). The PLL consists of a phase/frequency detector (PFD), loop filter, and voltagecontrolled oscillator (VCO). The MAX3882 is designed to deliver the best combination of jitter performance and power dissipation by using a fully differential signal architecture and low-noise design techniques. The input signal to the device (SDI) passes through a DC offset control block, which balances the input signal to a zero crossing at 50%. The PLL recovers the serial clock from the serial input data stream and produces the properly aligned data and the buffered recovered clock. The frequency of the recovered clock is divided by four and converted to differential LVDS parallel output PCLK. The demultiplexer generates 4-bit-wide 622Mbps/667Mbps parallel data. Input Amplifier The SDI inputs of the MAX3882 accept serial NRZ data at 2.488Gbps/2.67Gbps with 10mVP-P to 1600mVP-P amplitude. The input sensitivity is 10mVP-P, at which the jitter tolerance is met for a BER of 10 -10 when the threshold adjust is not used. The input sensitivity is as low as 4mV P-P for a BER of 10 -10. The MAX3882 is designed to directly interface with a transimpedance amplifier (MAX3277). For applications when vertical threshold adjustment is needed, the MAX3882 can be connected to the output of an AGC amplifier (MAX3861). Here, the input voltage range is 50mV P-P to 600mV P-P . See the Design Procedure section for decision threshold adjust. Phase Detector The phase detector in the MAX3882 produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. Frequency Detector The digital frequency detector (FD) acquires frequency lock without using an external reference clock. The frequency difference between the received data and the VCO clock is derived by sampling the in-phase and quadrature VCO outputs on both edges of the data input signal. Depending on the polarity of the frequency difference, the FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the FD returns to a neutral state. False locking is eliminated by this digital frequency detector. _______________________________________________________________________________________ 7 MAX3882 Pin Description (continued) MAX3882 2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier VTH (mV) VCC + 0.4V 5mV 800mV +188 THRESHOLD-SETTING ACCURACY (PART-TO-PART VARIATION OVER PROCESS) +170 VCC +152 VCC - 0.4V (a) AC-COUPLED SINGLE-ENDED INPUT 1.3 5mV 1.1 0.3 VCTRL (V) 2.1 VCC 800mV -152 VCC - 0.4V -170 -188 VCC - 0.8V THRESHOLD-SETTING STABILITY (OVER TEMPERATURE AND POWER SUPPLY) (b) DC-COUPLED SINGLE-ENDED INPUT Figure 1. Definition of Input Voltage Swing Figure 2. Relationship Between Control Voltage and Threshold Voltage tCK 2.488Gbps PRBS 223 - 1 PCLK+ tCK-Q LOL ASSERT TIME (PD+) - (PD-) ACQUISITION TIME LOL OUTPUT Figure 3. Definition of Clock-to-Q Delay VCO Tuning Range The MAX3882 can operate at both OC-48 and OC-48 with FEC data rates. Select the data frequency using the RATESET pin. Loop Filter and VCO The fully integrated PLL has a second-order transfer function, with a loop bandwidth (fL) fixed at.1.7MHz. An external capacitor between VCC_VCO and FIL sets the damping of the PLL. All jitter specifications are based on the CFIL capacitor being 0.068µF. Note that the PLL jitter transfer bandwidth does not change as the external capacitor changes, but the jitter peaking, acquisition time, and loop stability are affected. 8 2.488Gbps PRBS 223 - 1 INPUT DATA Figure 4. LOL Assert Time and PLL Acquisition Time Measurement For an overdamped system (fZ / fL) < 0.25, the jitter peaking (JP) of a second-order system can be approximated by: JP = 20log(1 + fZ / fL) The PLL zero frequency (fZ) is a function of the external capacitor (CFIL) and can be approximated according to: fZ = 1 / 2π(650)CFIL Figures 6 and 7 show the open-loop and closed-loop transfer functions. The PLL acquisition time is also directly proportional to the external capacitor CFIL. _______________________________________________________________________________________ 2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier Output LVDS Interface: PD, PCLK The MAX3882’s clock and data outputs are LVDS compatible to minimize power dissipation, speed transition time, and improve noise immunity. These outputs comply with the IEEE LVDS specification. The differential output signal magnitude is 250mV to 400mV. Design Procedure The MAX3882 provides a differential output clock (PCLK). Table 1 shows the pin configuration for choosing the type of operation mode. Decision Threshold Adjust Decision threshold adjust is available for WDM applications where optical amplifiers are used, generating spontaneous optical noise at data logic high. The decision threshold adjust range is ±170mV. Use the provided 2.2V bandgap reference VREF pin or an outside source, such as an output from a DAC to control the threshold voltage. The +170mV to -170mV threshold offset can be accomplished by varying the VCTRL voltage from 0.3V to 2.1V, respectively. See Figure 2. When using the VREF to generate voltage for threshold setting, see Figure 8. Connect VCTRL directly to VCC to disable threshold adjust. Applications Information Clock Holdover Capability Clock holdover is required in some applications where a valid clock needs to be provided to the upstream device in the absence of data transitions. To provide this function, an external reference clock rate of 155MHz/167MHz or 622MHz/667MHz must be applied to the SLBI input. Control input FREFSET selects which reference clock rate to use. The control LREF selects whether the PLL locks to the input data stream (SDI) or the reference clock (SLBI). When LREF is low, the input is switched to the reference clock input. This LREF input can be driven by connecting the LOL output pin directly or connecting to any other power monitor signal from the system. System Loopback The MAX3882 is designed to allow system loopback testing. The user can connect the serializer output (MAX3892) directly to the SLBI± inputs of the MAX3882 for system diagnostics. See Table 1 for selecting the system loopback operation mode. During system loopback, LOL cannot be connected to LREF. Interfacing the MAX3882 To correctly interface with the MAX3882’s CML input and LVDS outputs, refer to Maxim Application Note HFAN-1.0: Interfacing Between CML, PECL, and LVDS. DC-Offset Cancellation Loop Filter A DC-offset cancellation loop is implemented to remove the DC offset of the limiting amplifier. To minimize the low-frequency pattern-dependent jitter associated with this DC-cancellation loop, the low-frequency cutoff is 10kHz typical with CAZ = 0.1µF, connected across CAZ+ and CAZ-. Table 1. Operation Modes FREFSET LREF SIS RATESET X 1 0 0 Normal operation: PLL locked to data input at 2.488Gbps X 1 0 1 Normal operation: PLL locked to data input at 2.67Gbps X 1 1 0 System loopback: PLL lock frequency at 2.488Gbps OPERATION MODE DESCRIPTION X 1 1 1 System loopback: PLL lock frequency at 2.67Gbps 1 0 X 0 Clock holdover: PLL locked to reference frequency at 155MHz 1 0 X 1 Clock holdover: PLL locked to reference frequency at 167MHz 0 0 X 0 Clock holdover: PLL locked to reference frequency at 622MHz 0 0 X 1 Clock holdover: PLL locked to reference frequency at 667MHz _______________________________________________________________________________________ 9 MAX3882 Loss-of-Lock Monitor The LOL output indicates a PLL lock failure, either due to excessive jitter present at data input or due to loss of input data. In the case of loss of input data, the LOL indicates a loss-of-signal condition. The LOL output is asserted low when the PLL loses lock. MAX3882 2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier CAZ CAZ+ CAZ- PDO+ LVDS BANDGAP REFERENCE VREF PDO- MAX3882 PD1+ SDI+ 0 1 DC OFFSET CANCELLATION AMP SDI- LVDS D Q CK PD1- 4-BIT DEMULTIPLEXER PD2+ VCTRL LVDS PD2PD3+ SLBI+ AMP LVDS PD3- SLBIVCO LPF PFD LREF SIS FREFSET PCLK+ DIV/4 LOGIC LVDS PLL PCLK- FIL RATESET LOL VCC Figure 5. Functional Diagram CFIL = 0.01µF HO(j2πf) (dB) CLOSED-LOOP GAIN OPEN-LOOP GAIN HO(j2πf) (dB) CFIL = 0.01µF fZ = 2.45kHz CFIL = 0.068µF fZ = 3.6kHz f = (kHz) 1 10 100 1000 Figure 6. Open-Loop Transfer Function 0 -3 CFIL = 0.068µF f = (kHz) 1 10 100 1000 Figure 7. Closed-Loop Transfer Function Layout Techniques Exposed Pad Package For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3882 high-speed inputs and outputs. Power-supply decoupling should be placed as close to the VCC as possible. To reduce feedthrough, isolate input signals from output signals. The exposed pad, 36-pin QFN incorporates features that provide a very low thermal-resistance path for heat removal from the IC. The pad is electrical ground on the MAX3882 and should be soldered to the circuit board for proper thermal and electrical performance. 10 ______________________________________________________________________________________ 2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier MAX3882 +3.3V 0.068µF 155MHz CLOCK -3.3V SIS RATESET FIL VCC LREF LOL VCC PD3+ 100Ω* SLBI+ PD3- SLBIPD2+ 100Ω* MAX3882 PD2- 0.1µF SDI+ TIA OUTPUT AGC PD1+ SDI- 100Ω* 0.1µF VCTRL MAX3861 OVERHEAD TERMINATION PD1- R1 VREF PD0+ R2 R1 + R2 ≥ 50kΩ 100Ω* PD0- PCLK+ 100Ω* FREFSET CAZ+ CAZ- +3.3V PCLK- 0.1µF *REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω. Figure 8. Connecting the MAX3882 with Threshold Adjust and Clock Holdover Enabled ______________________________________________________________________________________ 11 2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier MAX3882 Typical Application Circuit +3.3V 0.068µF SYSTEM LOOPBACK SIS RATESET FIL VCC LREF LOL VCC PD3+ +3.3V 100Ω* SLBI+ 0.01µF PD3- SLBIPD2+ 100Ω* MAX3882 PD2- 0.1µF SDI+ TIA PD1+ SDI- 100Ω* 0.1µF VCTRL OVERHEAD TERMINATION PD1- MAX3277 VREF PD0+ 100Ω* PD0+3.3V PCLK+ 100Ω* PCLKFREFSET CAZ+ CAZ- 0.1µF *REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω. 12 ______________________________________________________________________________________ 2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier 36L,40L, QFN.EPS ______________________________________________________________________________________ 13 MAX3882 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX3882 2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) U Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 14 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.