DS1803 DS1803 Addressable Dual Digital Potentiometer FEATURES PIN ASSIGNMENT • 3V or 5V Power Supplies • Ultra–low power consumption H1 1 14 VCC L1 2 13 NC W1 3 12 H0 • 14–Pin TSSOP (173 mil) and 16–Pin SOIC (150 mil) A2 4 11 L0 packaging available for surface mount applications A1 5 10 W0 A0 6 9 SDA • Serial/Synchronous Bus Interface GND 7 8 SCL • Operating Temperature DS1803E 14–PIN TSSOP (173 MIL) • Two digitally controlled, 256–position potentiometers • Addressable using 3–Chip Select Inputs – Industrial: –40°C to +85°C • Standard Resistance Values: – DS1803–010 – DS1803–050 – DS1803–100 10KΩ 50KΩ 100KΩ H1 1 16 VCC NC 2 15 NC L1 3 14 H0 W1 4 13 L0 A2 5 12 W0 A1 6 11 NC A0 7 10 SDA GND 8 9 SCL DS1803Z 16–PIN SOIC (150 MIL) DS1803 16–PIN DIP (300 MIL) See Mech. Drawings Section PIN DESCRIPTION L0, L1 H0, H1 W0, W1 VCC A0 ..A2 SDA SCL GND NC – – – – – – – – – Low End of Resistor High End of Resistor Wiper Terminal of Resistor 3V/5V Power Supply Input Chip Select Inputs Serial Data I/O Serial Clock Input Ground No connection DESCRIPTION The DS1803 is an addressable device having two independently controlled potentiometers. Each potentiometer’s wiper can be set to one of 256 positions. Device control is achieved via a 2–wire serial interface having a data I/O terminal and a clock input terminal. Device addressing is provided through three chip select input terminals and correct communication protocol. Addressing capability, when operating in a bus topology, allows Copyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. up to eight devices to be controlled by the serial interface. The exact wiper position of each potentiometer can be written or read. The DS1803 is available in a 16–pin DIP, 16–pin SOIC and 14–pin TSSOP package. The device is available in three standard resistance values: 10KΩ, 50KΩ, and 100KΩ, and is specified over the industrial temperature range. 062097 1/10 DS1803 DEVICE OPERATION 2–WIRE SERIAL DATA BUS The DS1803 is an addressable, digitally controlled device which has two 256–position potentiometers. A functional block diagram of the part is shown in Figure 1. Communication and control of the device is accomplished via a 2–wire serial interface having signals SDA and SDL. Device addressing is attained using the device chip select inputs A0, A1, A2 and correct communication protocol over the 2–wire serial interface. The DS1803 supports a bi–directional 2–wire bus and data transmission protocol. A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a “master”. The devices that are controlled by the master are “slaves”. The bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1803 operates as a slave on the 2–wire bus. Connections to the bus are made via the open–drain I/O lines SDA and SCL. Each potentiometer is composed of a 256 position resistor array. Two 8–bit registers, each assigned to a respective potentiometer, are used to set wiper position on the resistor array. The wiper terminal is multiplexed to one of 256 positions on the resistor array based on its corresponding 8–bit register value. For example, the high–end terminals, H0 and H1, have wiper position values FF(Hex) while the low–end terminals, L0 and L1, have wiper position values 00(Hex). The DS1803 is a volatile device that does not maintain the position of the wiper during power–down or loss of power. On power–up, the DS1803 wipers’ position will be set to position 00(Hex) –– the low–end terminals. The user may then reset the wiper value to a desired position. Communication with the DS1803 takes place over the 2–wire serial interface consisting of the bi–directional data terminal, SDA, and the serial clock input, SCL. Complete details of the 2–wire interface are discussed in the section entitled “2–wire Serial Bus”. The 2–wire interface and chip select inputs A0, A1, and A2 allow operation of up to eight devices in a bus topology; with A0, A1, and A2 being the address of the device. Application Considerations The DS1803 is offered in three standard resistor values which include the 10KΩ, 50KΩ, and 100KΩ. The resolution of the potentiometer is defined as RTOT/255, where RTOT is the total resistor value of the potentiometer. The DS1803 is designed to operate using 3V or 5V power supplies over the industrial (–40°C to +85°C) temperature range. Maximum input signal levels across the potentiometer cannot exceed the operating power supply of the device. 062097 2/10 The following bus protocol has been defined (see Figure 2). • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Figure 2 details how data transfer is accomplished on the 2–wire bus. Depending upon the state of the R/W* bit, two types of data transfer are possible. DS1803 Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte–wise and each receiver acknowledges with a ninth bit. Within the bus specifications a regular mode (100 KHz clock rate) and a fast mode (400 KHz clock rate) are defined. The DS1803 works in both modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. 1. Data transfer from a master transmitter to a slave receiver: The first byte transmitted by the master is the control byte (slave address). Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. 2. Data transfer from a slave transmitter to a master receiver: The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a ‘not acknowledge’ is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus will not be released. The DS1803 may operate in the following two modes: 1. Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. 2. Slave transmitter mode: The first byte is received and handled as in the slave receiver mode. However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1803 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. SLAVE ADDRESS A control byte is the first byte received following the START condition from the master device. The control byte consist of a four bit control code; for the DS1803, this is set as 0101 binary for read/write operations. The next three bits of the control byte are the device select bits (A2, A1, A0). They are used by the master device to select which of eight devices are to be accessed. The select bits are in effect the three least significant bits of the slave address. Additionally, A2, A1 and A0 can be changed anytime during a powered condition of the part. The last bit of the control byte (R/W*) defines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. Figure 3 shows the control byte structure for the DS1803. Following the START condition, the DS1803 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving the 0101 address code and appropriate device select bits, the slave device outputs an acknowledge signal on the SDA line. 062097 3/10 DS1803 COMMAND AND PROTOCOL The command and protocol structure of the DS1803 allows the user to read or write the potentiometer(s). The command structures for the part are presented in Figures 4 and 5. Potentiometer data values and control and command values are always transmitted most significant bit (MSB) first. During communications the receiving unit always generates the acknowledge. Reading the DS1803 As shown in Figure 4, the DS1803 provides one read command operation. This operation allows the user to read both potentiometers. Specifically, the R/W bit of the control byte is set equal to a 1 for a read operation. Communication to read the DS1803 begins with a START condition which is issued by the master device. The control byte from the master device will follow the START condition. Once the control byte has been received by the DS1803, the part will respond with an ACKNOWLEDGE. The read/write bit of the control byte as stated should be set equal to ‘1’ for reading the DS1803. When the master has received the ACKNOWLEDGE from the DS1803, the master can then begin to receive potentiometer wiper data. The value of the potentiometer–0 wiper position will be the first returned from the DS1803. Once the eight bits of the potentiometer–0 wiper position has been transmitted, the master will need to issue an ACKNOWLEDGE, unless it is the only byte to be read, in which case the master issues a NOT ACKNOWLEDGE. If desired the master may stop the communication transfer at this point by issuing the STOP condition. However, if the value of the potentiometer–1 wiper position value is needed communication transfer can continue by clocking the remaining eight 062097 4/10 bits of the potentiometer–1 value, followed by an NOT ACKNOWLEDGE. Final communication transfer is terminated by issuing the STOP command. Again the flow of the read operation is presented in Figure 4. Writing the DS1803 A data flow diagram for writing the DS1803 is shown in Figure 5. The DS1803 has three write command operations. These include write pot–0, write pot–1, and write pot–0/1. The write pot–0 command allows the user to write the value of potentiometer–0 and as an option the the value of potentiometer–1. The write–1 command allows the user to write the value of potentiometer–1 only. The last write command, write–0/1, allows the user to write both potentiometers to the same value with one command and one data value being issued. All the write operations begin with a START condition. Following the START condition, the master device will issue the control byte. The read/write bit of the control byte will be set to ‘0’ for writing the DS1803. Once the control byte has been issued and the master receives the acknowledgment from the DS1803, the command byte is transmitted to the DS1803. As mentioned above, there exist three write operations that can be used with the DS1803. The binary value of each write command is shown in Figure 5 and also in the Table 1. 2–WIRE COMMAND WORDS Table 1 COMMAND COMMAND VALUE Write Potentiometer–0 101010 01 Write Potentiometer–1 101010 10 Write Both Pots 101011 11 DS1803 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature –1.0V to +7.0V –40°C to +85°C; industrial –55°C to +125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER SYMBOL MIN Supply Voltage VCC Resistor Inputs GND (–40°C to+85°C) TYP MAX UNITS NOTES +2.7 5.5 V 1 L, H, W GND–0.5 VCC+0.5 V 1 GND GND GND DC ELECTRICAL CONDITIONS PARAMETER (–40°C to+85°C; VCC=2.7V to 5.5V) SYMBOL CONDITION MIN TYP MAX UNITS NOTES 200 µA 3 +1 µA 1000 Ω Supply Current Active ICC Input Leakage ILI Wiper Resistance RW Wiper Current IW 1 mA Input Logic 1 VIH 0.7VCC VCC+0.5 V 1, 2 Input Logic 0 VIL GND–0.5 0.3VCC V 1, 2 14 –1 400 Input Logic Levels A0, A1, A2 Input Logic 1 Input Logic 0 0.7VCC GND–0.5 VCC+0.5 0.3VCC V Input Current each I/O Pin 0.4<VI/O<0.9 VDD –10 +10 µA 40 µA VOL1 3 mA sink current 0.0 0.4 V VOL2 6 mA sink current 0.0 0.6 V 10 pF 50 ns Standby Current ISTBY 20 4 Low Level Output Voltage I/O Capacitance CI/O Pulse Width of Spikes which must be suppressed by the input filter tSP Fast Mode 0 062097 5/10 DS1803 ANALOG RESISTOR CHARACTERISTICS PARAMETER SYMBOL End–to–End Resistor Tolerance (–40°C to+85°C; VCC=2.7V to 5.5V) MIN TYP –20 MAX UNITS +20 % NOTES Absolute Linearity ±0.75 LSB 13 Relative Linearity ±0.3 LSB 14 Hz 11 –3 dB Cutoff Frequency fcutoff Temperature Coefficient 650 Capacitance CI 5 AC ELECTRICAL CHARACTERISTICS PARAMETER ppm/C pF (–40°C to+85°C; VCC=2.7V to 5.5V) SYMBOL MIN SCL Clock Frequency fSCI 0 0 Bus Free Time Between STOP and START Condition tBUF Hold Time (Repeated) START Condition MAX UNITS NOTES 400 100 KHz 16 17 1.3 4.7 µs 16 17 tHD:STA 0.6 4.0 µs 5 Low Period of SCL Clock tLOW 1.3 4.7 µs High Period of SCL Clock tHIGH 0.6 4.0 µs Data Hold Time tHD:DAT 0 0 Data Setup Time tSU:DAT 100 250 Rise Time of both SDA and SCL Signals tR 20+0.1CB Fall Time of both SDA and SCL Signals tF 20+0.1CB Setup Time for STOP Condition tSU:STO 0.6 4.0 Capacitive Load for each Bus Line TYP CB µs 6, 7 ns 8 300 1000 ns 9 300 300 ns 9 0.9 µs 400 pF NOTES: 1. All voltages are referenced to ground. 2. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VDD is switched off. 3. ICC specified with SDA pin open SCL = 400 KHz clock rate. 4. ICC specified with VCC at 5.0V and SDA, SCL = 5.0V, –40°C to +85°C. 5. After this period, the first clock pulse is generated. 062097 6/10 DS1803 6. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 7. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 8. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250=1250 ns before the SCL line is released. 9. CB – total capacitance of one bus line in picofarads, timing referenced to (0.9)(VCC) and (0.1)(VCC). 10. Typical values are for tA = 25°C and nominal supply voltage. 11. –3 dB cutoff frequency characteristics for the DS1803 depend on potentiometer total resistance: DS1803–010; 1 MHz, DS1803–50; 200 KHz, DS1803–100; 100 KHz. 12. Address Inputs, A0, A1, and A2, should be tied to either VCC or GND depending on the desired address selections. 13. Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper position. Device test limits are ±1.6 LSB. 14. Relative linearity is used to determine the change in voltage between successive tap positions. Device test limits ±0.5 LSB. 15. Fast mode. 16. Standard mode. 062097 7/10 DS1803 DS1803 BLOCK DIAGRAM Figure 1 L0 POTENTIOMETER–0 H0 L1 256–TO–1 MULTIPLEXER H1 256–TO–1 MULTIPLEXER WIPER–0 (8–BIT REGISTER) W0 POTENTIOMETER–1 WIPER–1 (8–BIT REGISTER) W1 SCL COMMAND/ CONTROL UNIT SDA 2–WIRE SERIAL INTERFACE A0 DEVICE ADDRESS SELECTION A1 A2 2–WIRE DATA TRANSFER OVERVIEW Figure 2 SDA MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 2 6 7 8 9 ACK 1 2 3–7 8 9 ACK START CONDITION REPEATED IF MORE BYTES ARE TRANSFERRED 062097 8/10 STOP CONDITION OR REPEATED START CONDITION DS1803 CONTROL BYTE Figure 3 MSB LSB 0 1 0 1 A2 DEVICE IDENTIFIER A1 A0 R/W DEVICE ADDRESS 2–WIRE READ PROTOCOLS Figure 4 OPTIONAL DATA BYTE 0 1 A2 A1 A0 LSB 1 MSB LSB POT–0 POT–1 STOP 1 DATA BYTE MSB ACK 0 LSB ACK START MSB ACK CONTROL BYTE R/W=1 2–WIRE WRITE PROTOCOLS Figure 5 Write Pot–0 OPTIONAL 1 0 1 0 1 0 0 1 POT–0 LSB MSB DATA BYTE POT–1 LSB STOP 1 A2 A1 A0 0 MSB ACK 0 LSB DATA BYTE ACK 1 MSB COMMAND BYTE ACK 0 LSB ACK START MSB CONTROL BYTE R/W=0 Write Pot–1 1 A2 A1 A0 0 1 0 COMMAND BYTE 1 0 1 0 LSB 1 0 MSB DATA BYTE POT–1 LSB STOP 0 MSB ACK 1 LSB ACK 0 CONTROL BYTE ACK START MSB R/W=0 Write Pot–0/1 (same value) 1 A2 A1 A0 0 1 0 COMMAND BYTE 1 0 1 1 LSB 1 1 MSB DATA BYTE POT–0/1 VALUE LSB STOP 0 MSB ACK 1 LSB ACK 0 CONTROL BYTE ACK START MSB R/W=0 062097 9/10 DS1803 TIMING DIAGRAM Figure 6 SDA tBUF tSP tHD:STA tLOW tR tF SCL tHD:STA tSU:STA tHIGH tSU:DAT STOP START tSU:STO REPEATED START tHD:DAT DS1803 ORDERING INFORMATION ORDERING NUMBER PACKAGE OPERATING TEMPERATURE VERSION DS1803–010 16L DIP –40°C TO +85°C 10KΩ DS1803–050 16L DIP –40°C TO +85°C 50KΩ DS1803–100 16L DIP –40°C TO +85°C 100KΩ DS1803E–010 14L TSSOP (173 MIL) –40°C TO +85°C 10KΩ DS1803E–050 14L TSSOP (173 MIL) –40°C TO +85°C 50KΩ DS1803E–100 14L TSSOP (173 MIL) –40°C TO +85°C 100KΩ DS1803Z–010 16L SOIC (150 MIL) –40°C TO +85°C 10KΩ DS1803Z–050 16L SOIC (150 MIL) –40°C TO +85°C 50KΩ DS1803Z–100 16L SOIC (150 MIL) –40°C TO +85°C 100KΩ 062097 10/10