MICROCIRCUIT DATA SHEET Original Creation Date: 02/09/99 Last Update Date: 03/10/00 Last Major Revision Date: 02/21/00 MNDS90LV031A-X REV 1A0 3V LVDS Quad CMOS Differential Line Driver General Description The DS90LV031A is a quad CMOS differential line driver utilizing Low Voltage Differentional Signaling (LVDS) technology. It is designed for applications requiring low power dissipation and high data rates. The DS90LV031A accepts TTL/CMOS input levels and translates them to low voltage (350 mV) differential output siginals. In addition the driver supports a TRI-STATE function that may be used to disable the output stage, disabling the load current, and thus dropping the device to a low idle power state. The EN and EN* inputs allow active Low or active High control of the TRI-STATE outputs. The enables are common to all four drivers. The DS90LV031A and companion line receiver (DS90LV032A) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications. Industry Part Number NS Part Numbers DS90LV031A DS90LV031AW-QML* DS90LV031AWGMLS DS90LV031AWGQML** Prime Die DS90LV031A Controlling Document 5962-9865101QFA*, QXA** Processing Subgrp Description MIL-STD-883, Method 5004 1 2 3 4 5 6 7 8A 8B 9 10 11 Quality Conformance Inspection MIL-STD-883, Method 5005 1 Static tests at Static tests at Static tests at Dynamic tests at Dynamic tests at Dynamic tests at Functional tests at Functional tests at Functional tests at Switching tests at Switching tests at Switching tests at Temp ( oC) +25 +125 -55 +25 +125 -55 +25 +125 -55 +25 +125 -55 MICROCIRCUIT DATA SHEET MNDS90LV031A-X REV 1A0 Features - 3.3V power supply design +/- 350mV differential signaling Low power dissipation. Low differential skew. Low propagation delay Interoperable with existing 5V LVDS devices Military operating temprature range Pin compatible with DS26C31. Compatible with IEEE 1596.3 SCI LVDS standard Compatible with proposed TIA/EIA-644 LVDS standard Typical Rise/Fall times of 800pS. Typical Tri-State Enable/Disable Delays of less than 5nS. 2 MICROCIRCUIT DATA SHEET MNDS90LV031A-X REV 1A0 (Absolute Maximum Ratings) (Note 1) Supply Voltage (Vcc) -0.3 to +4V Input Voltage (Din) -0.3 to (Vcc+0.3V) Enable Input Voltage (EN, EN*) -0.3 to (Vcc+0.3V) Output Voltage (Dout+, Dout-) -0.3 to +3.9V Storage Temperature Range -65C to +150C Lead Temperature Soldering (4 sec) 260C ESD Rating. 6000 Volts. Maximum Junction Temperature +150C Maximum Power Dissipation @ +25C (Note 2) 16 PIN CERPAK (W Pkg) 16 PIN CERAMIC SOIC (WG Pkg) Thermal Resistance. (Theta JA) 16 PIN CERPAK (W Pkg) 16 PIN CERAMIC SOIC (WG Pkg) Thermal Resistance. (Theta JC) 16 PIN CERPAK (W Pkg) 16 PIN CERAMIC SOIC (WG Pkg) Note 1: Note 2: 845mW 845mW 148C/W 148C/W 22C/W 22C/W Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation. Derate (W & WG Pkgs) at 6.8mW/C for temperatures above +25C. Recommended Operating Conditions Supply Voltage 3.0 to 3.6V Operating Free Air Temperature -55 to +125 C 3 MICROCIRCUIT DATA SHEET MNDS90LV031A-X REV 1A0 Electrical Characteristics DC PARAMETERS (The following conditions apply to all the following parameters, unless otherwise specified.) DC: Vcc = 3.0/3.6V unless otherwise specified SYMBOL PARAMETER CONDITIONS NOTES PINNAME MIN Vod1 Differential Ouput Voltage RL = 100 Ohms Dout-, Dout+ DVod1 Change in Magnitude of Vod1 for complementary output States RL = 100 Ohms Dout-, Dout+ Vos Offset Voltage RL = 100 Ohms Dout-, Dout+ DVos Change in Magnitude of Vos for Complementary Output States RL = 100 Ohms Voh Output Voltage High Vol Output Voltage Low Vih Input Voltage High 1 Din, 2.0 EN, EN* Vil Input Voltage Low 1 IIH Input Current IIL UNIT SUBGROUPS 450 mV 1, 2, 3 50 mV 1, 2, 3 1.625 V 1, 2, 3 Dout-, Dout+ 50 mV 1, 2, 3 RL = 100 Ohms Dout-, Dout+ 1.85 V 1, 2, 3 RL = 100 Ohms Dout-, Dout+ V 1, 2, 3 Vcc V 1, 2, 3 Din, Gnd EN, EN* 0.8 V 1, 2, 3 Vin = Vcc or 2.5V, Vcc = 3.6V Din, EN, EN* +10 uA 1, 2, 3 Input Current Vin = Gnd or 0.4V, Vcc = 3.6V Din, EN, EN* +10 uA 1, 2, 3 Vcl Input Clamp Voltage Icl = -8mA, Vcc = 3.0V Din, EN, EN* -1.5 V 1, 2, 3 Ios Output Short Circuit Current ENABLED Din = Vcc, Dout + = 0V or Din = Gnd, Dout- = 0V Dout-, Dout+ -9.0 mA 1, 2, 3 Ioff Power-off Leakage Vout = 0V or 3.6V Vcc = 0V or Vcc = Open Dout-, Dout+ +20 uA 1, 2, 3 Ioz Output TRI-STATE Current EN = 0.8V and EN* = 2.0V VOUT = 0V or VCC, VCC = 3.6V Dout-, Dout+ +10 uA 1, 2, 3 Icc No Load Enabled Current Din = Vcc or Gnd Vcc 18 mA 1, 2, 3 Iccl Loaded Drivers Enabled Supply Current Rl = 100 ohms All Channels, Din = Vcc or Gnd (all inputs) Vcc 35 mA 1, 2, 3 Iccz Loaded or No Load Drivers Disabled Supply Current Din = Vcc or Gnd, En = Gnd, En* = Vcc Vcc 12 mA 1, 2, 3 Drivers Supply 4 250 MAX 1.125 .9 MICROCIRCUIT DATA SHEET MNDS90LV031A-X REV 1A0 Electrical Characteristics AC PARAMETERS (The following conditions apply to all the following parameters, unless otherwise specified.) AC: VCC = 3.0/3.3/3.6V, RL = 100 Ohms, CL = 20pF SYMBOL PARAMETER CONDITIONS NOTES PINNAME MIN MAX UNIT SUBGROUPS tPHLD Differential Propagation Delay High to Low 0.3 3.5 ns 9, 10, 11 tPLHD Differential Propagation Delay Low to High 0.3 3.5 ns 9, 10, 11 tSKD Differential Skew tPHLD-tPLHD 1.5 ns 9, 10, 11 tSK1 Channel to Channel Skew 2 1.75 ns 9, 10, 11 tSK2 Chip to Chip Skew 3 3.2 ns 9, 10, 11 Note 1: Note 2: Note 3: Tested during VOH/VOL tests. Channel to Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on the inputs. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays. 5 MICROCIRCUIT DATA SHEET MNDS90LV031A-X REV 1A0 Graphics and Diagrams GRAPHICS# DESCRIPTION W16ARL CERPACK (W), 16 LEAD (P/P DWG) WG16ARC CERAMIC SOIC (WG), 16 LEAD (P/P DWG) See attached graphics following this page. 6 MICROCIRCUIT DATA SHEET MNDS90LV031A-X REV 1A0 Revision History Rev ECN # Originator Changes 0A0 M0003265 03/10/00 Rel Date Mike Fitzgerald Initial MDS Release 1A0 M0003630 03/10/00 Mike Fitzgerald Added WG pkg NSID's, split out Pkg references under the "Absolute Maximum Ratings" section for Thermal Resistance, and Power Dissipation. Added WG pkg Marketing Outline Drawing. 7