DS90LV032AQML www.ti.com SNLS205A – NOVEMBER 2011 – REVISED APRIL 2013 DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver Check for Samples: DS90LV032AQML FEATURES DESCRIPTION • • • • • The DS90LV032A is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. 1 23 • • • • Low chip to chip skew Low differential skew High impedance LVDS inputs with power-off Low power dissipation Accepts small swing (330 mV) differential signal levels. Compatible with ANSI/TIA/EIA-644 Operating temperature range (-55°C to +85°C) Pin compatible with DS90C032A and DS26C32A. Typical Rise/Fall time is 350pS. The DS90LV032A accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The receiver supports a TRI-STATE® function that may be used to multiplex outputs. The DS90LV032A and companion LVDS line driver (eg. DS90LV031A) provide a new alternative to high power PECL/ECL devices for high speed point-topoint interface applications. In addition, the DS90LV032A provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present. Connection Diagram Figure 1. NAD0016A and NAC0016A Packages 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TRI-STATE is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2013, Texas Instruments Incorporated DS90LV032AQML SNLS205A – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com Functional Diagram Figure 2. Truth Table ENABLES INPUTS OUTPUT RO En En* RI+ − RI− L H X Z VID ≥ 0.1V H VID ≤ −0.1V L Full Fail-safe Open/Short or Terminated H All other combinations of enable inputs These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90LV032AQML DS90LV032AQML www.ti.com SNLS205A – NOVEMBER 2011 – REVISED APRIL 2013 Absolute Maximum Ratings (1) −0.3V to +4V Supply Voltage (VCC) Input Voltage (RI+, RI−) −0.3V to +3.9V Enable Input Voltage (En, En*) −0.3V to (VCC + 0.3V) Output Voltage (RO) −0.3V to (VCC + 0.3V) −65°C ≤ TA ≤ +150°C Storage Temperature Range Lead Temperature Range (Soldering 4 sec.) Maximum Package Power Dissipation @ +25°C +260°C (2) NAD0016A Package 845 mW NAC0016A Package 845 mW Thermal Resistance θJA NAD0016A Package 148°C/W NAC0016A Package 148°C/W θJC NAD0016A Package 21°C/W NAC0016A Package 21°C/W Maximum Junction Temperature ESD Rating (1) (2) (3) +150°C (3) 4.5 KV “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Derate @ 6.8mW/°C Human body model, 1.5 kΩ in series with 100 pF. Recommended Operating Conditions Min Max Unit +3.15 +3.45 V Receiver Input Voltage Gnd +3.0 V Operating Free Air −55 +85 °C Supply Voltage (VCC) Temperature (TA) Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A Subgroup Description 1 Static tests at Temp °C +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 12 Settling time at +25 13 Settling time at +125 14 Settling time at -55 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90LV032AQML 3 DS90LV032AQML SNLS205A – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com DS90LV032A Electrical Characteristics DC Parameters The following conditions apply, unless otherwise specified. Over supply voltage range of 3.15V to 3.45V and operating temperature of −55°C to +85°C. Symbol Parameter Conditions Notes VTL Differential Input Low Threshold VCM = +1.2V (1) VTh Differential Input High Threshold VCM = +1.2V (1) VCMR Common Mode Voltage Range VID = 200mV peak to peak II Input Current VCC = 3.45V or 0V, VI = 2.8V or 0V VOH Output High Voltage VOL Output Low Voltage IOL = 2 mA, VID = -200mV IOS Output Short Circuit Current Enabled, VO = 0V IOZ Output TRI-STATE Current Disabled, VO = 0V or VCC (1) (2) , Min -100 0.1 VCC = 0V, VI = 3.45V IOH = -0.4 mA, VID = 200mV 2.7 IOH = -0.4 mA, Inputs Open 2.7 (3) Max -15 Units Subgroups mV 1, 2, 3 100 mV 1, 2, 3 2.3 V 1, 2, 3 ±10 µA 1, 2, 3 ±20 µA 1, 2, 3 V 1, 2, 3 V 1, 2, 3 0.25 V 1, 2, 3 -120 mA 1, 2, 3 ±10 µA 1, 2, 3 VIH Input High Voltage (4) VIL Input Low Voltage (4) IL Input Current VI = VCC or 0V, Other Input = VCC or Gnd ±10 VCl Input Clamp Voltage ICl = -18mA -1.5 V 1, 2, 3 ICC No Load Supply Current Receivers Enabled En, En* = VCC or Gnd, Inputs Open 15 mA 1, 2, 3 En, En* = 2.4 or 0.5, Inputs Open 15 mA 1, 2, 3 En = Gnd, En* = VCC , Inputs Open 5.0 mA 1, 2, 3 ICCZ (1) (2) (3) (4) 4 No Load Supply Current Receivers Disabled 2.0 VCC V 1, 2, 3 Gnd 0.8 V 1, 2, 3 µA 1, 2, 3 Tested during VOH/VOL tests by applying appropriate voltage levels to the input pins of the device under test. The VCMR range is reduced for larger VID. Example: if VID = 400mV, the VCMR is 0.2V to 2.2V. The fail-safe condition with inputs shorted is valid over a common-mode range of 0V to 2.3V. A VID up to VCC − 0V may be applied to the RIN+/ RI− inputs with the Common-Mode voltage set to VCC/2. Propagation delay and Differential Pulse skew decrease when VID is increased from 200mV to 400mV. Skew specifications apply for 200mV ≤ VID ≤ 800mV over the common-mode range . Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature. Tested during IOZ tests by applying appropriate threshold voltage levels to the En and En* pins. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90LV032AQML DS90LV032AQML www.ti.com SNLS205A – NOVEMBER 2011 – REVISED APRIL 2013 DS90LV032A Electrical Characteristics AC Parameters The following conditions apply, unless otherwise specified. AC: VCC = 3.15 / 3.3 / 3.45V, CL = 20pF Symbol Parameter Conditions Notes Min Max Units Subgroups tPHLD Differential Propagation Delay High to Low VID = 200mV, Input pulse = 1.1V to 1.3V, VI = 1.2V (0V differential) to VO = 1/2 VCC Figure 3 and Figure 4 0.5 3.5 ns 9, 10, 11 tPLHD Differential Propagation Delay Low to High VID = 200mV, Input pulse = 1.1V to 1.3V, VI = 1.2V (0V differential) to VO = 1/2 VCC Figure 3 and Figure 4 0.5 3.5 ns 9, 10, 11 tSkD Differential Skew |tPHLD - tPLHD| CL = 20pF, VID = 200mV Figure 3 and Figure 4 1.5 ns 9, 10, 11 tSk1 Channel to Channel Skew CL = 20pF, VID = 200mV (1) 1.75 ns 9, 10, 11 (2) tSk2 Chip to Chip Skew CL = 20pF, VID = 200mV 3.0 ns 9, 10, 11 tPLZ Disable Time Low to Z Input pulse = 0V to 3.0V, VI = 1.5V, VO = VOL+0.5V, RL= 1kΩ. Figure 5 and Figure 6 12 ns 9, 10, 11 tPHZ Disable Time High to Z Input pulse = 0V to 3.0V, VI = 1.5V, VO = VOH-0.5V, RL = 1kΩ. Figure 5 and Figure 6 12 ns 9, 10, 11 tPZH Enable Time Z to High Input pulse = 0V to 3.0V, VI = 1.5V, VO = 50%, RL = 1kΩ. Figure 5 and Figure 6 20 ns 9, 10, 11 tPZL Enable Time Z to Low Input pulse = 0V to 3.0V, VI = 1.5V, VO = 50%, RL = 1kΩ. Figure 5 and Figure 6 20 ns 9, 10, 11 (1) (2) Channel-to-Channel Skew, is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on the inputs. Chip to chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays. PARAMETER MEASUREMENT INFORMATION Figure 3. Receiver Propagation Delay and Transition Time Test Circuit Figure 4. Receiver Propagation Delay and Transition Time Waveforms Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90LV032AQML 5 DS90LV032AQML SNLS205A – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) CL includes load and test jig capacitance. S1 = VCC for tPZL, and tPLZ measurements. S1 = Gnd for tPZH and tPHZ measurements. Figure 5. Receiver TRI-STATE Delay Test Circuit Figure 6. Receiver TRI-STATE Delay Waveforms 6 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90LV032AQML DS90LV032AQML www.ti.com SNLS205A – NOVEMBER 2011 – REVISED APRIL 2013 Typical Performance Characteristics Figure 7. ICC vs Frequency, four channels switching Figure 8. Typical Common-Mode Range variation with respect to amplitude of differential input Figure 9. Typical Pulse Skew variation versus commonmode voltage Figure 10. Variation in High to Low Propagation Delay versus VCM Figure 11. Variation in Low to High Propagation Delay versus VCM Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90LV032AQML 7 DS90LV032AQML SNLS205A – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com TYPICAL APPLICATION Balanced System Figure 12. Point-to-Point Application APPLICATION INFORMATION General application guidelines and hints for LVDS drivers and receivers may be found in the LVDS Owner's Manual at http://www.ti.com/ww/en/analog/interface/lvds.shtml LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 12. This configuration provides a clean signaling environment for the fast edge rates of the drivers . The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the driver output (current mode) into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS90LV032A differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting may be the result of a ground potential difference between the driver's ground reference and the receiver's ground reference, the common-mode effects of coupled noise, or a combination of the two. Both receiver input pins have a recommended operating input voltage range of 0V to +2.4V (measured from each pin to ground), exceeding these limits may turn on the ESD protection circuitry which will clamp the bus voltages. POWER DECOUPLING RECOMMENDATIONS Bypass capacitors must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1μF in parallel with 0.01μF, in parallel with 0.001μF at the power supply pin as well as scattered capacitors over the printed circuit board. Multiple vias should be used to connect the decoupling capacitors to the power planes A 10μF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board. PC BOARD CONSIDERATIONS Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals. Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s). Keep drivers and receivers as close to the (LVDS port side) connectors as possible. DIFFERENTIAL TRACES Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as common-mode. Lab experiments show that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is much better with the closer traces. Plus, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. 8 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90LV032AQML DS90LV032AQML www.ti.com SNLS205A – NOVEMBER 2011 – REVISED APRIL 2013 Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number of vias and other discontinuities on the line. Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable. TERMINATION Use a resistor which best matches the differential impedance of your transmission line. The resistor should be between 90Ω and 130Ω. Remember that the current mode outputs need the termination resistor to generate the differential voltage. LVDS will not work without resistor termination. Typically, connect a single resistor across the pair at the receiver end. Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination to the receiver inputs should be minimized. The distance between the termination resistor and the receiver should be <10mm (12mm MAX) PROBING LVDS TRANSMISSION LINES Always use high impedance (> 100kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz) scope. Improper probing will give deceiving results. CABLES AND CONNECTORS, GENERAL COMMENTS When choosing cable and connectors for LVDS it is important to remember: Use controlled impedance media. The cables and connectors you use should have a matched differential impedance of about 100Ω. They should not introduce major impedance discontinuities. Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation as common-mode (not differential mode) noise which is rejected by the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive. FAIL-SAFE FEATURE The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs. 1. Open Input Pins. The DS90LV032A is a quad receiver device, and if an application requires only 1, 2 or 3 receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will ensure a HIGH, stable output state for open inputs. 2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or power-off condition, the receiver output will again be in a HIGH state, even with the end of cable 100Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90LV032AQML 9 DS90LV032AQML SNLS205A – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com 3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs shorted and no external common-mode voltage applied. External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry. The footprint of the DS90LV032A is the same as the industry standard 26LS32 Quad Differential (RS-422) Receiver. PIN DESCRIPTIONS 10 Pin No. Name 2, 6, 10, 14 RI+ Non-inverting receiver input pin Description 1, 7, 9, 15 RI− Inverting receiver input pin 3, 5, 11, 13 RO Receiver output pin 4 En Active high enable pin, OR-ed with En* 12 En* Active low enable pin, OR-ed with En 16 VCC Power supply pin, +3.3V ± 0.3V 8 Gnd Ground pin Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90LV032AQML DS90LV032AQML www.ti.com SNLS205A – NOVEMBER 2011 – REVISED APRIL 2013 REVISION HISTORY Changes from Original (April 2013) to Revision A • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 10 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DS90LV032AQML 11 PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) (3) Top-Side Markings (4) 5962-9865201QFA ACTIVE CFP NAD 16 19 TBD Call TI Call TI -55 to 85 (DS90LV031AW ~ DS90LV032AW) -QML Q (5962-98651 ~ 5962-98652) 01QFA ACO 01QFA >T DS90LV032AW-MLS ACTIVE CFP NAD 16 19 TBD Call TI Call TI -55 to 85 DS90LV032AWMLS ACO MLS >T DS90LV032AW-QML ACTIVE CFP NAD 16 19 TBD Call TI Call TI -55 to 85 (DS90LV031AW ~ DS90LV032AW) -QML Q (5962-98651 ~ 5962-98652) 01QFA ACO 01QFA >T DS90LV032AWGMLS ACTIVE CFP NAC 16 42 TBD Call TI Call TI -55 to 85 (DS90C032WGL ~ DS90LV032AWG) MLS ACO MLS >T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (3) 16-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. 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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF DS90LV032AQML, DS90LV032AQML-SP : • Military: DS90LV032AQML • Space: DS90LV032AQML-SP NOTE: Qualified Version Definitions: • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 2 MECHANICAL DATA NAD0016A W16A (Rev T) www.ti.com MECHANICAL DATA NAC0016A WG16A (RevG) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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