MICROCIRCUIT DATA SHEET Original Creation Date: 08/03/98 Last Update Date: 01/12/99 Last Major Revision Date: 08/03/98 MNCLC114A-X REV 0A0 QUAD, LOW-POWER VIDEO BUFFER General Description The CLC114 is a high-performance, closed-loop quad buffer intended for power sensitive applications. Requiring only 30mW of quiescent power dissipation per channel (+5V supplies), the CLC114 offers a small signal bandwidth of 200MHz (0.5Vpp) and a slew rate of 450V/uS. Designed specifically for high density crosspoint switch and analog multiplexer applications, the CLC114 offers excellent linearity and wide channel isolation (62dB @ 10MHz). Driving a typical crosspoint switch load, the CLC114 offers differential gain and phase performance of 0.08% and 0.1%; gain flatness through 30MHz is typically 0.1dB. With its patented closed-loop topology, the CLC114 has significant performance advantages over conventional open-loop designs. Applications requiring low output impedance and true unity gain stability through very high frequencies (active filters, dynamic load buffering, etc.) will benefit from the CLC114's superior performance. Industry Part Number NS Part Numbers CLC114A CLC114AE-QML * CLC114AJ-MLS CLC114AJ-QML ** Prime Die UB1417A Controlling Document 5962-9233901MCA**, M2A* Processing Subgrp Description (blank) 1 2 3 4 5 6 7 8A 8B 9 10 11 Quality Conformance Inspection (blank) 1 Static tests at Static tests at Static tests at Dynamic tests at Dynamic tests at Dynamic tests at Functional tests at Functional tests at Functional tests at Switching tests at Switching tests at Switching tests at Temp ( oC) +25 +125 -55 +25 +125 -55 +25 +125 -55 +25 +125 -55 MICROCIRCUIT DATA SHEET MNCLC114A-X REV 0A0 Features - Closed-loop, quad buffer 200MHz small-signal bandwidth 450V/uS slew rate Low power, 30mW per channel (+5V sup.) 62dB channel isolation (10MHz) Specified for crosspoint switch loads Applications - Video crosspoint switch driver Video disribution buffers Video switching buffers Video signaling multiplexing Instrumentation amps Active filters 2 MICROCIRCUIT DATA SHEET MNCLC114A-X REV 0A0 (Absolute Maximum Ratings) (Note 1) Supply Voltage (Vs) +7V dc Output Current (Iout) 35 mA Power Dissipation (Pd) (Note 2) 1.2W Lead Temperature (soldering, 10 seconds) +300 C Junction Temperature (Tj) +175 C Storage Temperature Range -65 C to +150 C Thermal Resistance Junction-to-ambient (ThetaJA) Ceramic DIP (Still Air) (500 LFPM) LCC (Still Air) (500 LFPM) Junction-to-case (ThetaJC) Ceramic DIP LCC Package Weight (Typical) Ceramic DIP LCC ESD Tolerance (Note 3) 97 C/W 59 C/W TBD TBD 20 C/W TBD 2160 mg TBD 2200V Note 1: Note 2: Note 3: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. The maximum power dissipation must be derated at elevated temperatures and is dictated by Tjmax (maximum junction temperature), ThetaJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is Pdmax = (Tjmax - TA)/ThetaJA or the number given in the Absolute Maximum Ratings, whichever is lower. Human body model, 100pF discharged through 1.5K Ohms. Recommended Operating Conditions Supply Voltage (Vs) +5V dc Ambient Operating Temperature Range (Ta) -55 C to +125 C 3 MICROCIRCUIT DATA SHEET MNCLC114A-X REV 0A0 Electrical Characteristics PARAMETERS (The following conditions apply to all the following parameters, unless otherwise specified.) DC: Vs = +5V dc, Av = +1, and load resistance (Rl) = 100 Ohms. -55 C < Ta < +125 C SYMBOL Iin Voo Tc (Iin) Tc (Vio) Is +Rin Iout PSRR SSBW PARAMETER CONDITIONS NOTES Input Bias Current Output Offset Voltage Rs = 50 Ohms MIN MAX UNIT SUBGROUPS -5 +5 uA 1 -4 +4 uA 2 -10 +10 uA 3 -5.0 +5.0 mV 1 -8.0 +8.0 mV 2 -8.2 +8.2 mV 3 Average Input Bias Current Drift 1 -25 +25 nA/C 2 1 -62 +62 nA/C 3 Average Offset Voltage Drift 1 -30 +30 uV/C 2 1 -40 +40 uV/C 3 16.5 mA 1 16.0 mA 2 17.0 mA 3 Total Supply Current No Load Input Resistance Output Current Power Supply Rejection Ratio Small Signal Bandwidth 1 1.0 MOhms 1 1 2.0 MOhms 2 1 0.3 MOhms 3 1 25 mA 1 1 20 mA 2 1 12 mA 3 48 dB 1, 3 46 dB 2 135 MHz 4 3 120 MHz 5 3 135 MHz 6 1 70 MHz 4, 5, 6 0.2 dB 4 0.3 dB 5, 6 0.4 dB 4 3 0.7 dB 5 3 1.3 dB 6 +Vs = +4.5V to +5.0V, -Vs = -4.5V to -5.0V -3dB bandwidth, Vout < 0.5Vpp LSBW Large Signal Bandwidth -3dB bandwidth, Vout < 2.0Vpp GFPL Gain Flatness Peaking Low At 0.1MHz to 30MHz, Vout < 0.5Vpp 3 GFPH PINNAME Gain Flatness Peaking High 30MHz to 200MHz, Vout < 0.5Vpp 4 MICROCIRCUIT DATA SHEET MNCLC114A-X REV 0A0 Electrical Characteristics PARAMETERS(Continued) (The following conditions apply to all the following parameters, unless otherwise specified.) DC: Vs = +5V dc, Av = +1, and load resistance (Rl) = 100 Ohms. -55 C < Ta < +125 C SYMBOL GFR HD2 HD3 PARAMETER Gain Flatness Rolloff 2nd Harmonic Distortion 3rd Harmonic Distortion CONDITIONS NOTES PINNAME MIN 0.1MHz to 60 MHz, Vout < 0.5Vpp MAX UNIT SUBGROUPS 0.8 dB 4 3 1.0 dB 5 3 0.8 dB 6 -38 dBc 4 3 -38 dBc 5 3 -36 dBc 6 -50 dBc 4 3 -45 dBc 5 3 -50 dBc 6 -153 dBm 1Hz 4, 5, 6 2 Vpp at 20 MHz 2 Vpp at 20 MHz SNF Input Noise Floor At > 1 MHz 1 GA Small Signal Gain Rl = 100Ohms 1 0.96 V/V 4, 5 1 0.95 V/V 6 ILIN XT +Vout -Vout Cin Ro SR TRS Integral Endpoint Linearity Crosstalk Output Voltage Swing Output Voltage Swing At +1V, full scale 1 0.6 % 4 At +1V, full scale 1 0.5 % 5 At +1V, full scale 1 1.0 % 6 At 10MHz 1, 2 58 dB 4, 6 1, 2 60 dB 5 1 +1.8 V 4, 5 1 +1.0 V 6 Rl = 100Ohms Rl = 100Ohms Input Capacitance Output Impedance Slew Rate Rise and Fall Time dc 1 -1.8 V 4, 5 1 -1.0 V 6 1 3.0 pF 4 1 3.5 pF 5, 6 1 3.5 Ohms 1, 2 1 5.0 Ohms 3 Measured +1V with +4V Step 1 200 V/uS 9 Measured +1V with +4V Step 1 180 V/uS 10, 11 0.5V Step 1 2.8 nS 9, 11 1 3.0 nS 10 5 MICROCIRCUIT DATA SHEET MNCLC114A-X REV 0A0 Electrical Characteristics PARAMETERS(Continued) (The following conditions apply to all the following parameters, unless otherwise specified.) DC: Vs = +5V dc, Av = +1, and load resistance (Rl) = 100 Ohms. -55 C < Ta < +125 C SYMBOL TRL Ts PARAMETER Rise and Fall Time Settling Time CONDITIONS NOTES 2V Step 2V Step at 0.1% of the fixed value 2V Step at 0.01% of the fixed value OS Overshoot 0.5V Step PINNAME MIN MAX SUBGROUPS UNIT 1 7.0 nS 9, 11 1 8.0 nS 10 1 15 nS 9, 11 1 20 nS 10 1 30 nS 9, 11 1 40 nS 10 1 10 % 9 1 15 % 10, 11 DC: PARAMETERS: DRIFT LIMITS (The following conditions apply to all the following parameters, unless otherwise specified.) DC: Vs = +5V dc, Av = +1. "Deltas not required on B-level product. Deltas required for S-level (-MLS) product as specified on Internal Processing Instructions (IPI)." (Note 4) Iin Input Bias Current Is Total Supply Current Voo Output Offset Voltage Note 1: Note 2: Note 3: Note 4: -0.5 +0.5 uA 1 No Load -0.5 +0.5 mA 1 Rs = 50 Ohms -0.25 +0.25 mV 1 If not tested, shall be guaranteed to the limits specified in table I herein. Three channels are driven simultaneously while observing the output of the undriven fourth channel. Group A sample tested only. The algebraic convention, whereby the most negative value is a minimum and most positive is a maximum, is used in this table. Negative current shall be defined as convential current flow out of a device terminal. 6 MICROCIRCUIT DATA SHEET MNCLC114A-X REV 0A0 Graphics and Diagrams GRAPHICS# DESCRIPTION 06375HRA1 LCC (E), TYPE C, 20 TERMINAL (B/I CKT) 07084HRA2 CERDIP (J), 14 LEAD (B/I CKT) E20ARE LCC (E), TYPE C, 20 TERMINAL(P/P DWG) J14ARH CERDIP (J), 14 LEAD (P/P DWG) P000402A CERDIP (J),14 LEAD (PINOUT) P000447A LCC (E), TYPE C, 20 TERMINAL (PINOUT) See attached graphics following this page. 7 IN1 1 14 OUT1 N/C 2 13 +VCC IN2 3 12 OUT2 N/C 4 11 N/C IN3 5 10 OUT3 N/C 6 9 -VCC IN4 7 8 OUT4 CLC114J 14 - LEAD DIP CONNECTION DIAGRAM TOP VIEW P000402A N MIL/AEROSPACE OPERATIONS 2900 SEMICONDUCTOR DRIVE SANTA CLARA, CA 95050 +Vcc 20 19 4 18 5 17 6 16 7 15 8 14 10 In 4 9 11 12 13 -Vcc In 3 1 Out 4 In 2 2 Out 1 In 1 3 Out 2 Out 3 CLC114E 20 - LEAD LCC CONNECTION DIAGRAM TOP VIEW P000447A N MIL/AEROSPACE OPERATIONS 2900 SEMICONDUCTOR DRIVE SANTA CLARA, CA 95050 MICROCIRCUIT DATA SHEET MNCLC114A-X REV 0A0 Revision History Rev ECN # 0A0 M0003193 01/12/99 Rel Date Originator Changes Shaw Mead Initial MDS Release 8