EDI8F32259V 256Kx32 Static RAM CMOS, High Speed Module FEATURES DESCRIPTION n 256Kx32 bit CMOS Static RAM The EDI8F32259V is a high speed 8Mb Static RAM module organized as 256K words by 32 bits. This module is constructed from eight 256Kx4 Static RAMs in SOJ packages on an epoxy laminate (FR4) board. Access Times: 12, 15, 20, and 25ns Individual Byte Selects Fully Static, No Clocks Four chip enables (EØ-E3) are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. TTL Compatible I/O n High Density Package with JEDEC Standard Pinouts 72 Pin SIMM No. 175 (Angle) The EDI8F32259V is offered in 72 pin ZIP/SIMM package which enables eight megabits of memory to be placed in less than 1.3 square inches of board space. 72 Pin ZIP No. 176 72 Pin SIMM, No. 354 (Straight) All inputs and outputs are TTL compatible and operate from a single 3.3V supply. Fully asynchronous circuitry requires no clocks or refreshing for operation and provides equal access and cycle times for ease of use. n Single +3.3V (±10%) Supply Operation The ZIP and SIMM modules contain four PD (Presence Detect) pins which are used to identify module memory density in applications where alternate modules can be interchanged. FIG. 1 PIN NAMES PIN CONFIGURATIONS AND BLOCK DIAGRAM AØ-A17 Address Inputs EØ-E3 Chip Enables W, Write Enables G Output Enable DQØ-DQ31 Common Data Input/Output VCC Power (3.3V±10%) VSS Ground 0 PD 1,2 = VSS PD 3,4 = Open Oct. 2002 Rev. 0A ECO #15735 1 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com EDI8F32259V ABSOLUTE MAXIMUM RATINGS* Voltage on any pin relative to VSS Operating Temperature TA (Ambient) Commercial Storage Temperature, Plastic Power Dissipation Output Current RECOMMENDED DC OPERATING CONDITIONS -0.5V to 4.6V Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage 0°C to +70°C -55°C to +125°C 2.5 Watts 20 mA *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Sym VCC VSS VIH VIL Min 3.0 0 2.2 -0.3 Typ 3.3 0 --- Max Units 3.6 V 0 V VCC+0.3V V 0.8 V AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load VSS to 3.0V 5ns 1.5V 1TTL, CL = 30pF (note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF) DC ELECTRICAL CHARACTERISTICS Parameter Sym Conditions Min Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current CMOS Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage ICC1 ICC2 ICC3 W, E = VIL, II/O = 0mA, Min Cycle E ³ VIH, VIN £ VIL or VIN ³ VIH E ³ VCC-0.2V VIN ³ VCC-0.2V or VIN £ 0.2V VIN = 0V to VCC V I/O = 0V to VCC IOH = -4.0mA IOL = 8.0mA Max 12-25 800 240 40 Units ns mA mA mA --2.4 ±80 ±20 0.4 µA µA V V ILI ILO VOH VOL CAPACITANCE TRUTH TABLE E H L L L W X H L H G X L X H Mode Standby Read Write Output Deselect Output HIGH Z DOUT DIN HIGH Z (f=1.0MHz, VIN=VCC or VSS) Power ICC3 ICC1 ICC1 ICC1 Parameter Address Lines Data Lines Chip Enable Line Write Control Line Sym CI CD/Q CC CN Max 60 20 20 60 Unit pF pF pF pF These parameters are sampled, not 100% tested. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 2 Oct. 2002 Rev. 0A ECO #15735 EDI8F32259V AC CHARACTERISTICS READ CYCLE Parameter Symbol JEDEC Alt. 12ns Min Max 15ns Min Max Min Read Cycle Time TAVAV 12 15 20 TRC 20ns Max 25ns Min Max 25 Units ns Address Access Time TAVQV TAA 12 15 20 25 ns Chip Enable Access TELQV TACS 12 15 20 25 ns Chip Enable to Output in Low Z (1) TELQX TCLZ Chip Disable to Output in High Z (1) TEHQZ TCHZ 9 ns Output Hold from Address Change TAVQX TOH Output Enable to Output Valid TGLQV TOE Output Enable to Output in Low Z (1) TGLQX TOLZ Output Disable to Output in High Z (1) TGHQZ TOHZ 3 3 6 3 3 7 3 6 0 3 7 0 6 3 9 3 9 0 7 ns ns 9 0 9 ns ns 9 ns Note 1: Parameter guaranteed, but not tested. FIG. 2 READ CYCLE 1 - W HIGH, G, E LOW TAVAV A ADDRESS 1 ADDRESS 2 TAVQV TAVQX Q DATA 1 DATA 2 FIG. 3 READ CYCLE 2 - W HIGH TAVAV A TAVQV E TELQV TEHQZ TELQX G TGLQV TGHQZ TGLQX Q Oct. 2002 Rev. 0A ECO #15735 3 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com EDI8F32259V AC CHARACTERISTICS WRITE CYCLE Parameter Symbol JEDEC Alt. 12ns Min Max 15ns Min Max Min Write Cycle Time TAVAV TWC 12 15 20 25 ns Chip Enable to End of Write TELWH TWLEH TCW TCW 8 8 9 9 10 10 10 10 ns ns Address Setup Time TAVWL TAVEL TAS TAS 0 0 0 0 0 0 0 0 ns ns Address Valid to End of Write TAVWH TAVEH TAW TAW 8 8 9 9 10 10 10 10 ns ns Write Pulse Width TWLWH TWP TELEH TWP 8 8 9 9 10 10 10 10 ns ns Write Recovery Time TWHAX TEHAX TWR TWR 0 0 0 0 0 0 0 0 ns ns Data Hold Time TWHDX TEHDX TDH TDH 3 3 3 3 3 3 3 3 ns ns 6 0 7 0 20ns Max 9 25ns Min Max 0 9 Units Write to Output in High Z (1) TWLQZ TWHZ 0 Data to Write Time TDVWH TDW TDVEH TDW 6 6 7 7 8 8 8 8 ns ns ns Output Active from End of Write (1) TWHQX TWLZ 3 3 3 3 ns Note 1: Parameter guaranteed, but not tested. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 4 Oct. 2002 Rev. 0A ECO #15735 EDI8F32259V WRITE CYCLE 1 - W CONTROLLED TAVAV A E TELWH TWHAX TAVWH TWLWH W TAVWL TDVWH D TWHDX DATA VALID TWHQX TWLQZ HIGH Z Q WRITE CYCLE 2 - E CONTROLLED TAVAV A TAVEL TELEH E TAVEH TEHAX TWLEH W TDVEH D Q Oct. 2002 Rev. 0A ECO #15735 TEHDX DATA VALID HIGH Z 5 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com EDI8F32259V ORDERING INFORMATION Part Number EDI8F32259V12MNC EDI8F32259V15MNC EDI8F32259V20MNC EDI8F32259V25MNC EDI8F32259V12MMC EDI8F32259V15MMC EDI8F32259V20MMC EDI8F32259V25MMC EDI8F32259V12MZC EDI8F32259V15MZC EDI8F32259V20MZC EDI8F32259V25MZC Speed (ns) 12 15 20 25 12 15 20 25 12 15 20 25 Package No. 176 176 176 176 354 354 354 354 175 175 175 175 Note: For Gold SIMM, Change from EDI8F to EDI8G. PACKAGE DESCRIPTION PACKAGE NO. 175: 72 PIN ZIP NS G I S 3.865 MAX. DE .360 W .050 E MAX. N R FO D E .590 .050 ND MAX. E M M .175 O P1 C E .125 R.020 .100 T .250 TYP. .100 TYP. O N TYP. .052 TYP. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 6 Oct. 2002 Rev. 0A ECO #15735 EDI8F32259V PACKAGE NO. 176: 72 PIN SIMM ANGLED PACKAGE NO. 354: 72 PIN SIMM STRAIGHT ALL DIMENSIONS ARE IN INCHES Oct. 2002 Rev. 0A ECO #15735 7 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com DATASHEET APPROVALS ECO# 15735 NEW REV 0A EDI PART NO. EDI8F32259V APPROVAL: JUAN GUZMAN INITIAL DATE DATE 11/4/02 CORRECTION ON PAGES 11/4/02 L.K. 11/6/02 MUKESH TRIVEDI M.A. PAUL MARIEN 11/7/02 LARRY WINROTH DAVE KELLY MARK DOWNEY DAVE HARRISON TONY LEE BOB KHEDERIAN LUIS ESTELLA YES NO WILL THIS DATASHEET GO ON THE WEB? IS THIS A NEW DATASHEET? WILL THIS DATASHEET REPLACE AN EXISTING DATASHEET THAT’S ALREADY ON THE WEB? LINE:________ FAMILY:____________ PROD.TYPE:________ ORG:___________ DENSITY:________ SPEED:__________ PKG:____________ VOLTAGE:________ IF YES, WHAT DATASHEET IS IT REPLACING? WHAT SECTION SHOULD THIS DATASHEET BE PLACED IN ON THE WEB? AFTER REVIEWING OR MAKING CORRECTIONS ON THE DATASHEET (S) PLEASE SIGN-OFF ON THIS SHEET AND ,MAKE YOUR CORRECTIONS –ON THE ORIGINAL COPY(S). AFTER REVIEWING THE DATA SHEET, TEST ENGINEERING WILL COMPLETE THE SECTION BELOW. TEST PROGRAM CHANGE REQUIRED: YES:_________NO____________DATE:___________ TEST ENGINEER SIGNATURE___________________ IF YES, DO NOT RELEASE DATA SHEET UNTIL TEST PROGRAM CHANGE IS COMPLETED. TEST PROGRAM CHANGE COMPLETION DATE:__________ TEST PROGRAM NAME AND REVISION_________________ TEST ENGINEER SIGNATURE__________________________ FO-00342R1.DOC ECO# 14942 SHEET 1 OF 1